Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3430
-gerrit
commit c9371fb32746c4c7ad8fb5fcc4c864d5ae9d73c0
Author: Gerd Hoffmann <kraxel at redhat.com>
Date: Fri Jun 7 16:03:44 2013 +0200
qemu: minimal q35 support
Initializes the hardware, boots linux kernel.
TODO list:
More northbridge init bits (especially IRQ setup).
Add ACPI support.
Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf
Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
src/cpu/qemu-x86/Makefile.inc | 1 +
src/mainboard/emulation/Kconfig | 6 ++-
src/mainboard/emulation/qemu-q35/Kconfig | 39 ++++++++++++++++
src/mainboard/emulation/qemu-q35/Makefile.inc | 3 ++
src/mainboard/emulation/qemu-q35/devicetree.cb | 41 +++++++++++++++++
src/mainboard/emulation/qemu-q35/mainboard.c | 59 ++++++++++++++++++++++++
src/mainboard/emulation/qemu-q35/romstage.c | 63 ++++++++++++++++++++++++++
src/mainboard/emulation/qemu-x86/northbridge.c | 5 ++
8 files changed, 216 insertions(+), 1 deletion(-)
diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc
index e206b4d..c65fcd0 100644
--- a/src/cpu/qemu-x86/Makefile.inc
+++ b/src/cpu/qemu-x86/Makefile.inc
@@ -19,3 +19,4 @@
ramstage-y += qemu.c
subdirs-y += ../x86/mtrr
subdirs-y += ../x86/lapic
+subdirs-y += ../x86/smm
diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig
index 72b70af..a4ecec6 100644
--- a/src/mainboard/emulation/Kconfig
+++ b/src/mainboard/emulation/Kconfig
@@ -6,6 +6,9 @@ choice
config BOARD_EMULATION_QEMU_X86_I440FX
bool "QEMU x86 i440fx/piix4 (aka qemu -M pc)"
+config BOARD_EMULATION_QEMU_X86_Q35
+ bool "QEMU x86 i440fx/piix4 (aka qemu -M q35, since v1.4)"
+
config BOARD_EMULATION_QEMU_ARMV7
bool "QEMU armv7 (vexpress-a9)"
@@ -14,9 +17,10 @@ endchoice
config BOARD_EMULATION_QEMU_X86
bool
default y
- depends on BOARD_EMULATION_QEMU_X86_I440FX
+ depends on BOARD_EMULATION_QEMU_X86_I440FX || BOARD_EMULATION_QEMU_X86_Q35
source "src/mainboard/emulation/qemu-i440fx/Kconfig"
+source "src/mainboard/emulation/qemu-q35/Kconfig"
source "src/mainboard/emulation/qemu-armv7/Kconfig"
config MAINBOARD_VENDOR
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
new file mode 100644
index 0000000..864fe28
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -0,0 +1,39 @@
+if BOARD_EMULATION_QEMU_X86_Q35
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_QEMU_X86
+ select SOUTHBRIDGE_INTEL_I82801IX
+ select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+ select MMCONF_SUPPORT
+ select CACHE_AS_RAM
+# select HAVE_OPTION_TABLE
+# select HAVE_PIRQ_TABLE
+# select HAVE_ACPI_TABLES
+# select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_256
+ select EARLY_CBMEM_INIT
+
+config MAINBOARD_DIR
+ string
+ default emulation/qemu-q35
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "QEMU x86 q35/ich9"
+
+#config IRQ_SLOT_COUNT
+# int
+# default 6
+
+#config DCACHE_RAM_BASE
+# hex
+# default 0xd0000
+
+#config DCACHE_RAM_SIZE
+# hex
+# default 0x10000
+
+
+endif # BOARD_EMULATION_QEMU_X86
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
new file mode 100644
index 0000000..2365d28
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -0,0 +1,3 @@
+cpu_incs += $(src)/mainboard/emulation/qemu-x86/cache_as_ram.inc
+ramstage-y += ../qemu-x86/northbridge.c
+ramstage-y += ../qemu-x86/fw_cfg.c
diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb
new file mode 100644
index 0000000..1ac55a0
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/devicetree.cb
@@ -0,0 +1,41 @@
+chip mainboard/emulation/qemu-q35
+ device cpu_cluster 0 on
+ chip cpu/qemu-x86
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+ device pci 0.0 on end # northbridge (q35)
+ chip southbridge/intel/i82801ix
+ register "sata_ahci" = "1"
+
+ # present unconditionally
+ device pci 1f.0 on end # LPC
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+
+ # presence depends in qemu config
+ # (see docs/q35-chipset.cfg in qemu src tree)
+ device pci 1a.0 on end # UHCI #4
+ device pci 1a.1 on end # UHCI #5
+ device pci 1a.2 on end # UHCI #6
+ device pci 1a.7 on end # EHCI #2
+ device pci 1b.0 on end # HD Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1d.0 on end # UHCI #1
+ device pci 1d.1 on end # UHCI #2
+ device pci 1d.2 on end # UHCI #3
+ device pci 1d.7 on end # EHCI #1
+
+ # not present (not emulated by qemu)
+ device pci 19.0 off end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end
+ end
+end
diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c
new file mode 100644
index 0000000..a4c04c7
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/mainboard.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stefan.reinauer at coreboot.org>
+ * Copyright (C) 2010 Kevin O'Connor <kevin at koconnor.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/keyboard.h>
+#include <arch/io.h>
+#include <console/console.h>
+
+static void qemu_nb_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "%s: q35\n", __func__);
+
+ /* Map memory at 0xc0000 - 0xfffff */
+ int i;
+ uint8_t v = pci_read_config8(dev, 0x90);
+ v |= 0x30;
+ pci_write_config8(dev, 0x90, v);
+ for (i=0; i<6; i++)
+ pci_write_config8(dev, 0x91 + i, 0x33);
+
+ /* This sneaked in here, because Qemu does not
+ * emulate a SuperIO chip
+ */
+ pc_keyboard_init(0);
+}
+
+static struct device_operations nb_operations = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = qemu_nb_init,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver nb_driver __pci_driver = {
+ .ops = &nb_operations,
+ .vendor = 0x8086,
+ .device = 0x29c0,
+};
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
new file mode 100644
index 0000000..1104ba8
--- /dev/null
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Stefan Reinauer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <cpu/x86/bist.h>
+#include <timestamp.h>
+#include "drivers/pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+
+#include "../qemu-x86/memory.c"
+
+void main(unsigned long bist)
+{
+ int cbmem_was_initted;
+
+ /* init_timer(); */
+ post_code(0x05);
+
+ i82801ix_early_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ //print_pci_devices();
+ //dump_pci_devices();
+
+ cbmem_was_initted = !cbmem_initialize();
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(rdtsc());
+ timestamp_add_now(TS_START_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+ /* Keep this the last thing this function does. */
+ cbmemc_reinit();
+#endif
+
+}
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index c2e4ba2..0e540d7 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -189,3 +189,8 @@ struct chip_operations mainboard_emulation_qemu_i440fx_ops = {
CHIP_NAME("QEMU Northbridge i440fx")
.enable_dev = northbridge_enable,
};
+
+struct chip_operations mainboard_emulation_qemu_q35_ops = {
+ CHIP_NAME("QEMU Northbridge q35")
+ .enable_dev = northbridge_enable,
+};