[coreboot-gerrit] New patch to review for coreboot: 4157c14 cpu/x86/lapic/lapic_cpu_init.c: Remove double startup IPI for AMD AGESA processors

[Paul Menzel (paulepanter@users.sourceforge.net)]

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3468

-gerrit

commit 4157c14837bf0e02f12eb40ec4c53023cbc06de0
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Fri Jun 14 23:42:45 2013 +0200

    cpu/x86/lapic/lapic_cpu_init.c: Remove double startup IPI for AMD AGESA processors
    
    The following commit tried to do the same but used a non-existing
    Kconfig define `CONFIG_CPU_AMD_MODEL_14XXX`.
    
        commit 236aef238f6e5c735cc9f253746def582fbaf8ff
        Author: Scott Duplichan <scott at notabs.org>
        Date:   Tue Oct 19 04:36:42 2010 +0000
    
            To reduce boot time, remove the double startup IPI and 10 ms delay from lapic_cpu_init.c. The change is
            currently restricted to recent model AMD processors, though it could be applied to others after successful testing.
    
    This was the reason for it being removed – and unfortunately not
    fixed – in the following commit.
    
        commit 2bdfb48b13ab5c392ef2b1dd9a8bfda6c90b2e18
        Author: Stefan Reinauer <reinauer at chromium.org>
        Date:   Tue Apr 3 16:17:11 2012 -0700
    
            Fixes and Sandybridge support for lapic cpu init
    
            Reviewed-on: http://review.coreboot.org/871
    
    So try it again, by using `CPU_AMD_AGESA` as all AMD processors
    using AGESA – currently Family 10h to 15h – should not need it.
    
    Successfully tested on ASRock E350M1 with a Family 14h processor.
    
    • coreboot serial log without the patch
    01.026: +#startup loops: 2.
    01.026: Sending STARTUP #1 to 1.
    01.026: After apic_write.
    01.027: Startup point 1.
    01.027: Waiting for send to finish...
    01.028: +Sending STARTUP #2 to 1.
    01.027: After apic_write.
    01.027: Startup point 1.
    01.029: Waiting for send to finish...
    01.029: +After Startup.
    
    • coreboot serial log with the patch
    00.993: +#startup loops: 1.
    00.993: Sending STARTUP #1 to 1.
    00.993: After apic_write.
    00.993: Startup point 1.
    00.993: Waiting for send to finish...
    00.994: +After Startup.
    
    Change-Id: Ib310f2e5ab4b463a82bf0fa9fa9141b556cabf60
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/cpu/x86/lapic/lapic_cpu_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index fbc8aa4..08cbe96 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -167,7 +167,7 @@ static int lapic_start_cpu(unsigned long apicid)
 		return 0;
 	}
 
-#if !CONFIG_CPU_AMD_MODEL_10XXX
+#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_AGESA
 	num_starts = 2;
 #else
 	num_starts = 1;