[coreboot-gerrit] New patch to review for coreboot: 9abfac9 Add initial support for DMP Vortex86EX mainboard.
Andrew Wu (arw@dmp.com.tw)
gerrit at coreboot.org
Sat Jun 15 19:55:44 CEST 2013
Andrew Wu (arw at dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3473
-gerrit
commit 9abfac9988aa651a239f8d2c9fad2d26b14f6d52
Author: Andrew Wu <arw at dmp.com.tw>
Date: Sun Jun 16 01:47:58 2013 +0800
Add initial support for DMP Vortex86EX mainboard.
Change-Id: I74de250c69a57109362be1b2f00c0b4aa24a64e8
Signed-off-by: Andrew Wu <arw at dmp.com.tw>
---
src/cpu/Kconfig | 1 +
src/cpu/Makefile.inc | 1 +
src/cpu/dmp/Kconfig | 20 +
src/cpu/dmp/Makefile.inc | 20 +
src/cpu/dmp/vortex86ex/Kconfig | 22 +
src/cpu/dmp/vortex86ex/Makefile.inc | 31 +
src/cpu/dmp/vortex86ex/biosdata.inc | 84 ++
src/cpu/dmp/vortex86ex/biosdata.lds | 84 ++
src/cpu/dmp/vortex86ex/biosdata_ex.inc | 195 +++
src/cpu/dmp/vortex86ex/biosdata_ex.lds | 35 +
src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc | 531 +++++++++
src/mainboard/Kconfig | 3 +
src/mainboard/dmp/Kconfig | 36 +
src/mainboard/dmp/vortex86ex/Kconfig | 1651 ++++++++++++++++++++++++++
src/mainboard/dmp/vortex86ex/chip.h | 23 +
src/mainboard/dmp/vortex86ex/devicetree.cb | 34 +
src/mainboard/dmp/vortex86ex/irq_tables.c | 57 +
src/mainboard/dmp/vortex86ex/mainboard.c | 35 +
src/mainboard/dmp/vortex86ex/romstage.c | 428 +++++++
src/northbridge/Kconfig | 1 +
src/northbridge/Makefile.inc | 1 +
src/northbridge/dmp/Kconfig | 20 +
src/northbridge/dmp/Makefile.inc | 20 +
src/northbridge/dmp/vortex86ex/Kconfig | 27 +
src/northbridge/dmp/vortex86ex/Makefile.inc | 21 +
src/northbridge/dmp/vortex86ex/bootblock.c | 76 ++
src/northbridge/dmp/vortex86ex/chip.h | 26 +
src/northbridge/dmp/vortex86ex/northbridge.c | 147 +++
src/northbridge/dmp/vortex86ex/northbridge.h | 76 ++
src/northbridge/dmp/vortex86ex/raminit.c | 559 +++++++++
src/northbridge/dmp/vortex86ex/xgi_oprom.c | 35 +
src/southbridge/Kconfig | 1 +
src/southbridge/Makefile.inc | 1 +
src/southbridge/dmp/Kconfig | 20 +
src/southbridge/dmp/Makefile.inc | 20 +
src/southbridge/dmp/vortex86ex/Kconfig | 27 +
src/southbridge/dmp/vortex86ex/Makefile.inc | 22 +
src/southbridge/dmp/vortex86ex/bootblock.c | 68 ++
src/southbridge/dmp/vortex86ex/chip.h | 38 +
src/southbridge/dmp/vortex86ex/hard_reset.c | 25 +
src/southbridge/dmp/vortex86ex/ide_sd_sata.c | 171 +++
src/southbridge/dmp/vortex86ex/southbridge.c | 563 +++++++++
src/southbridge/dmp/vortex86ex/southbridge.h | 89 ++
43 files changed, 5345 insertions(+)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index d1e5237..788e219 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -12,6 +12,7 @@ endif # ARCH_ARM
if ARCH_X86
source src/cpu/amd/Kconfig
+source src/cpu/dmp/Kconfig
source src/cpu/intel/Kconfig
source src/cpu/via/Kconfig
source src/cpu/qemu-x86/Kconfig
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 8b9d074..09d36ec 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -2,6 +2,7 @@
## Subdirectories
################################################################################
subdirs-y += amd
+subdirs-y += dmp
subdirs-y += armltd
subdirs-y += intel
subdirs-y += samsung
diff --git a/src/cpu/dmp/Kconfig b/src/cpu/dmp/Kconfig
new file mode 100644
index 0000000..db7e2bd
--- /dev/null
+++ b/src/cpu/dmp/Kconfig
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+source src/cpu/dmp/vortex86ex/Kconfig
diff --git a/src/cpu/dmp/Makefile.inc b/src/cpu/dmp/Makefile.inc
new file mode 100644
index 0000000..002212c
--- /dev/null
+++ b/src/cpu/dmp/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-$(CONFIG_CPU_DMP_VORTEX86EX) += vortex86ex
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
new file mode 100644
index 0000000..54db4e0
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/Kconfig
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config CPU_DMP_VORTEX86EX
+ bool
+ select UDELAY_TSC
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
new file mode 100644
index 0000000..ff0b58c
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/Makefile.inc
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+
+chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc
+chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc
+chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata.lds
+chipset_bootblock_lds += $(src)/cpu/dmp/vortex86ex/biosdata_ex.lds
+
+ROMCCFLAGS := -mcpu=i386 -O2
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc
new file mode 100644
index 0000000..055fffe
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/biosdata.inc
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+ .section ".dmp_reserved", "a", @progbits
+
+ .skip 0x3c000 - 0x3bc00, 0xff
+
+.previous
+
+ .section ".dmp_kbd_fw_part2", "a", @progbits
+
+ .skip 0x3d000 - 0x3c000, 0xff
+
+.previous
+
+ .section ".dmp_mtbf_low_cnt", "a", @progbits
+
+ .skip 0x3e000 - 0x3d000, 0xff
+
+.previous
+
+ .section ".dmp_kbd_fw_part1", "a", @progbits
+
+ #include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc"
+
+.previous
+
+ .section ".dmp_spi_flash_disk_driver", "a", @progbits
+
+ .skip 0x3f800 - 0x3f000, 0xff
+
+.previous
+
+ .section ".dmp_frontdoor", "a", @progbits
+
+ .skip 0x3fd00 - 0x3f800, 0xff
+
+.previous
+
+ .section ".dmp_isoinfo", "a", @progbits
+
+ .skip 26 * 16, 0xff
+
+.previous
+
+ .section ".dmp_isodata_checksum", "a", @progbits
+
+ .skip 8, 0xff
+
+.previous
+
+ .section ".dmp_mac", "a", @progbits
+
+ .skip 6, 0xff
+
+.previous
+
+ .section ".dmp_mtbf_limit", "a", @progbits
+
+ .skip 3, 0xff
+
+.previous
+
+ .section ".dmp_isodata", "a", @progbits
+
+ .skip 32, 0xff
+
+.previous
diff --git a/src/cpu/dmp/vortex86ex/biosdata.lds b/src/cpu/dmp/vortex86ex/biosdata.lds
new file mode 100644
index 0000000..b525b2a
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/biosdata.lds
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+
+ /* Vortex86 ROM fixed data areas used range is too big, we need
+ * to move bootblock from default address to another place,
+ * otherwise .dmp_frontdoor section can't be included.
+ * Address before ..fbc00 is available.
+ */
+ ROMLOC_MIN = 0xffffbc00 - (_erom - _rom + 16) -
+ (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
+
+ . = 0xffffbc00;
+ .dmp_reserved (.): {
+ *(.dmp_reserved)
+ }
+
+ . = 0xffffc000;
+ .dmp_kbd_fw_part2 (.): {
+ *(.dmp_kbd_fw_part2)
+ }
+
+ . = 0xffffd000;
+ .dmp_mtbf_low_cnt (.): {
+ *(.dmp_mtbf_low_cnt)
+ }
+
+ . = 0xffffe000;
+ .dmp_kbd_fw_part1 (.): {
+ *(.dmp_kbd_fw_part1)
+ }
+
+ . = 0xfffff000;
+ .dmp_spi_flash_disk_driver (.): {
+ *(.dmp_spi_flash_disk_driver)
+ }
+
+ . = 0xfffff800;
+ .dmp_frontdoor (.): {
+ *(.dmp_frontdoor)
+ }
+
+ . = 0xfffffe00;
+ .dmp_isoinfo (.): {
+ *(.dmp_isoinfo)
+ }
+
+ . = 0xffffffa0;
+ .dmp_isodata_checksum (.): {
+ *(.dmp_isodata_checksum)
+ }
+
+ . = 0xffffffb0;
+ .dmp_mac (.): {
+ *(.dmp_mac)
+ }
+
+ . = 0xffffffb8;
+ .dmp_mtbf_limit (.): {
+ *(.dmp_mtbf_limit)
+ }
+
+ . = 0xffffffc0;
+ .dmp_isodata (.): {
+ *(.dmp_isodata)
+ }
+}
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc
new file mode 100644
index 0000000..5005dea
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/biosdata_ex.inc
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "config.h"
+
+/*
+PLL Freq = 25 * NS /(MS * 2^RS)
+CPU Freq = PLL/(CPU_DIV+2)
+DRAM Freq = PLL/2(DRAM_DIV+1)
+
+DDR3
+CPU/DRAM/PCI B6 B7 BB BC BD BF
+200/200/33 30 03 0F 02 8F 07
+300/300/33 48 03 0F 02 1F 07
+300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable
+300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable
+300/300/100 48 03 23 02 7F 07
+400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing
+400/200/100 60 43 23 02 4F 07
+400/400/33 60 03 0F 02 BF 09
+500/250/33 50 42 0F 02 DF 07
+500/500/33 78 03 0F 02 4F 09
+400/300/33 90 53 0F 02 3F 07
+400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable
+400/300/100 90 53 23 02 9F 07
+444/333/33 A0 53 0F 02 5F 08
+466/350/33 A8 53 0F 02 DF 09
+500/375/33 B4 53 0F 02 AF 09
+
+DDR3:
+Board ID
+0
+1
+2
+3
+4
+5
+6 : 200
+7 : 300
+8 : 333
+9 : 400
+A : 467
+B : 533
+C : 600
+D : 667
+E : 733
+F : 800
+*/
+
+#if CONFIG_PLL_200_200_33
+ // 200/200/33 30 03 0F 02 8F 07
+ byte_fffb6 = 0x30
+ byte_fffb7 = 0x03
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_300_300_33
+ // 300/300/33 48 03 0F 02 1F 07
+ byte_fffb6 = 0x48
+ byte_fffb7 = 0x03
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_300_300_100
+ // 300/300/100 48 03 23 02 7F 07
+ byte_fffb6 = 0x48
+ byte_fffb7 = 0x03
+ byte_fffbb = 0x23
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_400_200_33
+ // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing
+ byte_fffb6 = 0x60
+ byte_fffb7 = 0x43
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_400_200_100
+ // 400/200/100 60 43 23 02 4F 07
+ byte_fffb6 = 0x60
+ byte_fffb7 = 0x43
+ byte_fffbb = 0x23
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_400_400_33
+ // 400/400/33 60 03 0F 02 BF 09
+ byte_fffb6 = 0x60
+ byte_fffb7 = 0x03
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x09
+#elif CONFIG_PLL_500_250_33
+ // 500/250/33 50 42 0F 02 DF 07
+ byte_fffb6 = 0x50
+ byte_fffb7 = 0x42
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_500_500_33
+ // 500/500/33 78 03 0F 02 4F 09
+ byte_fffb6 = 0x78
+ byte_fffb7 = 0x03
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x09
+#elif CONFIG_PLL_400_300_33
+ // 400/300/33 90 53 0F 02 3F 07
+ byte_fffb6 = 0x90
+ byte_fffb7 = 0x53
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_400_300_100
+ // 400/300/100 90 53 23 02 9F 07
+ byte_fffb6 = 0x90
+ byte_fffb7 = 0x53
+ byte_fffbb = 0x23
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x07
+#elif CONFIG_PLL_444_333_33
+ // 444/333/33 A0 53 0F 02 5F 08
+ byte_fffb6 = 0xa0
+ byte_fffb7 = 0x53
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x08
+#elif CONFIG_PLL_466_350_33
+ // 466/350/33 A8 53 0F 02 DF 09
+ byte_fffb6 = 0xa8
+ byte_fffb7 = 0x53
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x09
+#elif CONFIG_PLL_500_375_33
+ // 500/375/33 B4 53 0F 02 AF 09
+ byte_fffb6 = 0xb4
+ byte_fffb7 = 0x53
+ byte_fffbb = 0x0f
+ byte_fffbc = 0x02
+ byte_fffbe = 0xff
+ byte_fffbf = 0x09
+#else
+ #error Error Strap PLL config.
+#endif
+
+tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc
+pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f)
+
+byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f
+
+ .section ".a9123_crossbar_config", "a", @progbits
+
+ .skip 0x3fdf0 - 0x3fd00, 0xff
+
+.previous
+
+ .section ".a9123_strap_1", "a", @progbits
+
+ .byte byte_fffb6, byte_fffb7
+
+.previous
+
+ .section ".a9123_strap_2", "a", @progbits
+
+ .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf
+
+.previous
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.lds b/src/cpu/dmp/vortex86ex/biosdata_ex.lds
new file mode 100644
index 0000000..d711648
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/biosdata_ex.lds
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+SECTIONS {
+ . = 0xfffffd00;
+ .a9123_crossbar_config (.): {
+ *(.a9123_crossbar_config)
+ }
+
+ . = 0xffffffb6;
+ .a9123_strap_1 (.): {
+ *(.a9123_strap_1)
+ }
+
+ . = 0xffffffbb;
+ .a9123_strap_2 (.): {
+ *(.a9123_strap_2)
+ }
+}
diff --git a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc
new file mode 100644
index 0000000..486bf1b
--- /dev/null
+++ b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc
@@ -0,0 +1,531 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+ .byte 0x02, 0x04, 0xa3, 0x02, 0x0a, 0xfb, 0xef, 0x75
+ .byte 0xf0, 0x03, 0xa4, 0xff, 0xae, 0x07, 0x1f, 0xee
+ .byte 0x70, 0xfa, 0x22, 0x02, 0x0a, 0xd5, 0x12, 0x09
+ .byte 0x5e, 0x7f, 0x30, 0x12, 0x05, 0xfb, 0x90, 0xe0
+ .byte 0x00, 0x74, 0x16, 0xf0, 0x12, 0x0d, 0xda, 0xc2
+ .byte 0x92, 0xc2, 0x93, 0xc2, 0x90, 0xd2, 0x91, 0xd2
+ .byte 0xb8, 0xd2, 0xba, 0xd2, 0x88, 0xd2, 0xa8, 0xd2
+ .byte 0x8a, 0xd2, 0xaa, 0x7d, 0x44, 0xe4, 0xff, 0x12
+ .byte 0x0e, 0x3a, 0x7d, 0x4d, 0x0f, 0x12, 0x0e, 0x3a
+ .byte 0x7d, 0x26, 0x0f, 0x12, 0x0e, 0x3a, 0x7d, 0x50
+ .byte 0x0f, 0x12, 0x0e, 0x3a, 0x12, 0x0e, 0x59, 0xd2
+ .byte 0xaf, 0x7f, 0xb1, 0x12, 0x0e, 0xf5, 0x90, 0x0f
+ .byte 0xfe, 0xe4, 0x93, 0xff, 0xb4, 0x55, 0x0a, 0xa3
+ .byte 0xe4, 0x93, 0xb4, 0xaa, 0x04, 0xd2, 0x08, 0x80
+ .byte 0x10, 0xef, 0xb4, 0x12, 0x0c, 0x90, 0x0f, 0xff
+ .byte 0xe4, 0x93, 0xb4, 0x34, 0x04, 0xc2, 0x08, 0xc2
+ .byte 0x12, 0x12, 0x03, 0x6c, 0x12, 0x0d, 0xa6, 0x12
+ .byte 0x01, 0x08, 0x30, 0x01, 0x27, 0x30, 0x12, 0x1f
+ .byte 0x20, 0x00, 0x1c, 0x30, 0x11, 0x19, 0x12, 0x0d
+ .byte 0x25, 0x12, 0x09, 0xc4, 0x30, 0x08, 0x05, 0xc2
+ .byte 0x1a, 0x12, 0x0a, 0x26, 0x12, 0x0d, 0x92, 0xd2
+ .byte 0x00, 0x12, 0x0d, 0x3b, 0x12, 0x07, 0xc2, 0x12
+ .byte 0x0d, 0xda, 0xc2, 0x01, 0x12, 0x03, 0x6c, 0x12
+ .byte 0x07, 0x2e, 0x30, 0x12, 0xc4, 0x30, 0x00, 0xc1
+ .byte 0x90, 0xd0, 0x00, 0xe0, 0x30, 0xe0, 0xba, 0xc2
+ .byte 0xaf, 0x12, 0x0e, 0x07, 0x50, 0x0e, 0x12, 0x0e
+ .byte 0xb6, 0x12, 0x0e, 0xbc, 0xd2, 0x1a, 0x12, 0x0a
+ .byte 0x26, 0x12, 0x0d, 0x3b, 0xd2, 0xaf, 0x80, 0xa1
+ .byte 0xae, 0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90
+ .byte 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e
+ .byte 0x33, 0x7f, 0x20, 0x12, 0x0d, 0x51, 0x43, 0x1a
+ .byte 0x10, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22
+ .byte 0xda, 0x7e, 0x10, 0x09, 0x14, 0x12, 0x0d, 0xa6
+ .byte 0x90, 0xe0, 0x00, 0xe0, 0xff, 0x20, 0xe1, 0x03
+ .byte 0x02, 0x02, 0xc8, 0xc2, 0xa8, 0xc2, 0xaa, 0x20
+ .byte 0x04, 0x03, 0x30, 0x07, 0x05, 0xd2, 0xa8, 0xd2
+ .byte 0xaa, 0x22, 0xef, 0xa2, 0xe3, 0x92, 0x1c, 0x90
+ .byte 0xf0, 0x00, 0xe0, 0xf5, 0x2c, 0x12, 0x0e, 0x2f
+ .byte 0xd2, 0xa8, 0xd2, 0xaa, 0x30, 0x1c, 0x03, 0x02
+ .byte 0x01, 0xee, 0xc2, 0x1d, 0xc2, 0x1e, 0x20, 0x17
+ .byte 0x03, 0x02, 0x01, 0xd4, 0xe5, 0x18, 0x24, 0xe1
+ .byte 0x60, 0x3b, 0x24, 0x54, 0x70, 0x03, 0x02, 0x01
+ .byte 0xd0, 0x24, 0xfa, 0x60, 0x14, 0x14, 0x60, 0x1e
+ .byte 0x14, 0x60, 0x1f, 0x14, 0x60, 0x23, 0x24, 0x74
+ .byte 0x70, 0x6c, 0xaf, 0x2c, 0x12, 0x05, 0xfb, 0x80
+ .byte 0x67, 0xe5, 0x2c, 0x30, 0xe1, 0x04, 0xd2, 0x90
+ .byte 0x80, 0x5e, 0xc2, 0x90, 0x80, 0x5a, 0xc2, 0x1f
+ .byte 0x80, 0x02, 0xd2, 0x1f, 0x85, 0x2c, 0x2f, 0x80
+ .byte 0x46, 0xd2, 0x1e, 0x80, 0x4b, 0xe5, 0x2c, 0x70
+ .byte 0x1a, 0x12, 0x0c, 0xed, 0x12, 0x08, 0xf2, 0x85
+ .byte 0x38, 0x12, 0x85, 0x39, 0x13, 0x85, 0x3a, 0x14
+ .byte 0x85, 0x09, 0x15, 0x85, 0x0a, 0x16, 0x85, 0x0b
+ .byte 0x17, 0x80, 0x2d, 0xe5, 0x2c, 0xc3, 0x94, 0x01
+ .byte 0x40, 0x13, 0xe5, 0x2c, 0xd3, 0x94, 0x06, 0x50
+ .byte 0x0c, 0xc2, 0x1f, 0x74, 0x11, 0x25, 0x2c, 0xf8
+ .byte 0xe6, 0xf5, 0x2f, 0x80, 0x0a, 0xe5, 0x2c, 0xb4
+ .byte 0x07, 0x0e, 0xc2, 0x1f, 0x85, 0x3b, 0x2f, 0xd2
+ .byte 0x20, 0x12, 0x0d, 0xb8, 0x80, 0x02, 0xd2, 0x1d
+ .byte 0xc2, 0x17, 0x80, 0x02, 0xd2, 0x1d, 0x30, 0x1d
+ .byte 0x07, 0xaf, 0x2c, 0x12, 0x05, 0x2f, 0x80, 0x08
+ .byte 0x30, 0x1e, 0x05, 0xaf, 0x2c, 0x12, 0x05, 0x97
+ .byte 0x12, 0x0e, 0x85, 0x02, 0x02, 0xc2, 0xc2, 0x1d
+ .byte 0xe5, 0x2c, 0x12, 0x0b, 0x21, 0x02, 0xb7, 0x1f
+ .byte 0x02, 0x35, 0x20, 0x02, 0xb7, 0x60, 0x02, 0x56
+ .byte 0xa7, 0x02, 0x5d, 0xa8, 0x02, 0x64, 0xa9, 0x02
+ .byte 0x48, 0xaa, 0x02, 0x64, 0xab, 0x02, 0x6d, 0xad
+ .byte 0x02, 0x74, 0xae, 0x02, 0x41, 0xc0, 0x02, 0xb7
+ .byte 0xcb, 0x02, 0x7b, 0xd0, 0x02, 0xb7, 0xd1, 0x02
+ .byte 0xb7, 0xd2, 0x02, 0xb7, 0xd3, 0x02, 0xb7, 0xd4
+ .byte 0x02, 0x98, 0xdd, 0x02, 0x8d, 0xdf, 0x02, 0xa8
+ .byte 0xfe, 0x00, 0x00, 0x02, 0xb5, 0x12, 0x0a, 0x83
+ .byte 0x8f, 0x2d, 0xc2, 0x1f, 0x85, 0x2d, 0x2f, 0x80
+ .byte 0x28, 0xc2, 0x1f, 0x75, 0x2f, 0xff, 0x80, 0x21
+ .byte 0x7f, 0x30, 0x12, 0x05, 0xfb, 0xc2, 0x1f, 0x75
+ .byte 0x2f, 0x55, 0xc2, 0x20, 0x80, 0x4b, 0x12, 0x0e
+ .byte 0x8d, 0xd2, 0x1d, 0x80, 0x5a, 0x12, 0x0e, 0xe6
+ .byte 0xd2, 0x1d, 0x80, 0x53, 0xc2, 0x1f, 0xe4, 0xf5
+ .byte 0x2f, 0xd2, 0x20, 0x80, 0x34, 0x12, 0x0e, 0x94
+ .byte 0xd2, 0x1d, 0x80, 0x43, 0x12, 0x0e, 0xf0, 0xd2
+ .byte 0x1d, 0x80, 0x3c, 0x75, 0x2e, 0x01, 0x30, 0x90
+ .byte 0x03, 0x43, 0x2e, 0x02, 0xc2, 0x1f, 0x85, 0x2e
+ .byte 0x2f, 0xd2, 0x20, 0x80, 0x14, 0xd2, 0x90, 0xc2
+ .byte 0x1f, 0x85, 0x0f, 0x2f, 0xd2, 0x20, 0x80, 0x09
+ .byte 0xc2, 0x90, 0xc2, 0x1f, 0x85, 0x0f, 0x2f, 0xd2
+ .byte 0x20, 0x12, 0x0d, 0xb8, 0xd2, 0x1d, 0x80, 0x0f
+ .byte 0xc2, 0x91, 0x7f, 0x05, 0x12, 0x00, 0x06, 0xd2
+ .byte 0x91, 0xd2, 0x1d, 0x80, 0x02, 0xd2, 0x1d, 0x30
+ .byte 0x1d, 0x03, 0x12, 0x0e, 0x85, 0xd2, 0x17, 0x85
+ .byte 0x2c, 0x18, 0x20, 0x01, 0x03, 0x12, 0x0d, 0xda
+ .byte 0x22, 0x44, 0x4d, 0x26, 0x50, 0x00, 0xff, 0x43
+ .byte 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, 0x64, 0x44
+ .byte 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, 0x65, 0x38
+ .byte 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a, 0x66, 0x71
+ .byte 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b, 0x67, 0x2e
+ .byte 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c, 0x68, 0x39
+ .byte 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, 0x69, 0x31
+ .byte 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, 0x6a, 0x72
+ .byte 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f, 0x6b, 0x33
+ .byte 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60, 0x6c, 0x34
+ .byte 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61, 0x6d, 0x73
+ .byte 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, 0x3a, 0x36
+ .byte 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, 0x55, 0x56
+ .byte 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b, 0x7c, 0x4f
+ .byte 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f, 0x52, 0x53
+ .byte 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45, 0x57, 0x4e
+ .byte 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54, 0x00, 0x00
+ .byte 0x00, 0x41, 0x54, 0x00, 0x01, 0x01, 0x02, 0x01
+ .byte 0x02, 0x02, 0x03, 0x01, 0x02, 0x02, 0x03, 0x02
+ .byte 0x03, 0x03, 0x04, 0x14, 0x23, 0x14, 0x3a, 0x14
+ .byte 0x4d, 0x42, 0x32, 0x23, 0x20, 0x0c, 0x03, 0x02
+ .byte 0x04, 0x08, 0xc2, 0x1a, 0xc2, 0x1b, 0xe5, 0x10
+ .byte 0x30, 0xe7, 0x57, 0xe5, 0x11, 0xae, 0x10, 0x78
+ .byte 0x06, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9
+ .byte 0xf5, 0x26, 0xff, 0x12, 0x0d, 0xca, 0x8f, 0x27
+ .byte 0xe5, 0x10, 0xc4, 0x13, 0x13, 0x54, 0x03, 0xff
+ .byte 0xe5, 0x27, 0x54, 0x01, 0xb5, 0x07, 0x05, 0xe4
+ .byte 0x7f, 0x01, 0x80, 0x02, 0x7f, 0x00, 0xef, 0x30
+ .byte 0xe0, 0x04, 0xd2, 0x1b, 0x80, 0x24, 0x20, 0x13
+ .byte 0x1f, 0xaf, 0x26, 0x12, 0x07, 0x79, 0xaf, 0x26
+ .byte 0x12, 0x09, 0xf6, 0x8e, 0x28, 0x8f, 0x29, 0xe5
+ .byte 0x29, 0xf4, 0x70, 0x03, 0xe5, 0x28, 0xf4, 0x60
+ .byte 0x09, 0x85, 0x29, 0x26, 0xd2, 0x1a, 0x80, 0x02
+ .byte 0xd2, 0x1a, 0x30, 0x1a, 0x1b, 0xc2, 0x27, 0x7f
+ .byte 0x07, 0x12, 0x0b, 0x6c, 0xc2, 0x27, 0x7f, 0x06
+ .byte 0x12, 0x0b, 0x6c, 0xa2, 0x13, 0x92, 0x25, 0x85
+ .byte 0x26, 0x31, 0x12, 0x08, 0xbb, 0xc2, 0x0c, 0x22
+ .byte 0x30, 0x1b, 0x10, 0xa2, 0x13, 0x92, 0x21, 0x75
+ .byte 0x30, 0xff, 0xd2, 0x22, 0xc2, 0x23, 0xd2, 0x24
+ .byte 0x02, 0x06, 0xee, 0xc2, 0x0c, 0x12, 0x0e, 0x7d
+ .byte 0x22, 0xe4, 0xf5, 0x26, 0xf5, 0x27, 0x75, 0x28
+ .byte 0x0f, 0x75, 0x29, 0xff, 0xe5, 0x27, 0x25, 0x29
+ .byte 0xff, 0xe5, 0x26, 0x35, 0x28, 0xc3, 0x13, 0xf5
+ .byte 0x2a, 0xef, 0x13, 0xf5, 0x2b, 0xff, 0xae, 0x2a
+ .byte 0x12, 0x0e, 0x15, 0xbf, 0xff, 0x0e, 0xe5, 0x2b
+ .byte 0x24, 0xff, 0xf5, 0x29, 0xe5, 0x2a, 0x34, 0xff
+ .byte 0xf5, 0x28, 0x80, 0x47, 0xef, 0x70, 0x0d, 0xe5
+ .byte 0x2b, 0x24, 0x01, 0xf5, 0x27, 0xe4, 0x35, 0x2a
+ .byte 0xf5, 0x26, 0x80, 0x37, 0x75, 0x2c, 0xff, 0xe4
+ .byte 0xf5, 0x2d, 0xe5, 0x2c, 0xc3, 0x13, 0xf5, 0x2c
+ .byte 0xb5, 0x07, 0x1c, 0xe5, 0x2b, 0xae, 0x2a, 0x78
+ .byte 0x03, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, 0xf9
+ .byte 0x7c, 0x00, 0x25, 0x2d, 0xff, 0xec, 0x3e, 0xcf
+ .byte 0x24, 0x01, 0xcf, 0x34, 0x00, 0xfe, 0x22, 0x05
+ .byte 0x2d, 0xe5, 0x2d, 0xb4, 0x07, 0xd4, 0x7e, 0xff
+ .byte 0x7f, 0xff, 0x22, 0xd3, 0xe5, 0x27, 0x95, 0x29
+ .byte 0xe5, 0x28, 0x64, 0x80, 0xf8, 0xe5, 0x26, 0x64
+ .byte 0x80, 0x98, 0x40, 0x80, 0xe5, 0x27, 0xae, 0x26
+ .byte 0x78, 0x03, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8
+ .byte 0xf9, 0xff, 0x22, 0x78, 0x7f, 0xe4, 0xf6, 0xd8
+ .byte 0xfd, 0x75, 0x81, 0x3b, 0x02, 0x04, 0xea, 0x02
+ .byte 0x00, 0x16, 0xe4, 0x93, 0xa3, 0xf8, 0xe4, 0x93
+ .byte 0xa3, 0x40, 0x03, 0xf6, 0x80, 0x01, 0xf2, 0x08
+ .byte 0xdf, 0xf4, 0x80, 0x29, 0xe4, 0x93, 0xa3, 0xf8
+ .byte 0x54, 0x07, 0x24, 0x0c, 0xc8, 0xc3, 0x33, 0xc4
+ .byte 0x54, 0x0f, 0x44, 0x20, 0xc8, 0x83, 0x40, 0x04
+ .byte 0xf4, 0x56, 0x80, 0x01, 0x46, 0xf6, 0xdf, 0xe4
+ .byte 0x80, 0x0b, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20
+ .byte 0x40, 0x80, 0x90, 0x08, 0x80, 0xe4, 0x7e, 0x01
+ .byte 0x93, 0x60, 0xbc, 0xa3, 0xff, 0x54, 0x3f, 0x30
+ .byte 0xe5, 0x09, 0x54, 0x1f, 0xfe, 0xe4, 0x93, 0xa3
+ .byte 0x60, 0x01, 0x0e, 0xcf, 0x54, 0xc0, 0x25, 0xe0
+ .byte 0x60, 0xa8, 0x40, 0xb8, 0xe4, 0x93, 0xa3, 0xfa
+ .byte 0xe4, 0x93, 0xa3, 0xf8, 0xe4, 0x93, 0xa3, 0xc8
+ .byte 0xc5, 0x82, 0xc8, 0xca, 0xc5, 0x83, 0xca, 0xf0
+ .byte 0xa3, 0xc8, 0xc5, 0x82, 0xc8, 0xca, 0xc5, 0x83
+ .byte 0xca, 0xdf, 0xe9, 0xde, 0xe7, 0x80, 0xbe, 0xd2
+ .byte 0x0d, 0xc2, 0x96, 0xd2, 0x0e, 0xd2, 0x10, 0xc2
+ .byte 0x94, 0x8f, 0x08, 0x12, 0x0d, 0xca, 0xef, 0x13
+ .byte 0xb3, 0x92, 0x14, 0xd2, 0x16, 0xe4, 0xf5, 0x0c
+ .byte 0x7f, 0x28, 0x12, 0x00, 0x06, 0xc2, 0x97, 0xd2
+ .byte 0x03, 0xc2, 0x0a, 0x7f, 0xe8, 0x7e, 0xfd, 0x12
+ .byte 0x0c, 0x79, 0xc2, 0x0d, 0xd2, 0x96, 0x30, 0x16
+ .byte 0x16, 0x12, 0x0e, 0x62, 0x50, 0xf8, 0xc2, 0xaf
+ .byte 0xd2, 0x97, 0xc2, 0x21, 0x12, 0x06, 0xe5, 0xc2
+ .byte 0x16, 0xe4, 0xf5, 0x0c, 0xd2, 0xaf, 0x22, 0x7f
+ .byte 0xe8, 0x7e, 0xfd, 0x12, 0x0c, 0x79, 0x20, 0x04
+ .byte 0x12, 0x20, 0x0a, 0x0f, 0x12, 0x0e, 0x62, 0x50
+ .byte 0xf5, 0xc2, 0xaf, 0xc2, 0x21, 0x12, 0x06, 0xe5
+ .byte 0xd2, 0xaf, 0x22, 0x12, 0x07, 0x2e, 0x22, 0xd2
+ .byte 0x10, 0xc2, 0x94, 0xd2, 0x0a, 0xd2, 0x0d, 0xc2
+ .byte 0x96, 0x8f, 0x08, 0x12, 0x0d, 0xca, 0xef, 0x13
+ .byte 0xb3, 0x92, 0x14, 0xd2, 0x16, 0xe4, 0xf5, 0x0e
+ .byte 0x7f, 0x28, 0x12, 0x00, 0x06, 0xc2, 0x95, 0xd2
+ .byte 0x05, 0xc2, 0x0e, 0x7f, 0xe8, 0x7e, 0xfd, 0x12
+ .byte 0x0c, 0x79, 0xc2, 0x10, 0xd2, 0x94, 0x30, 0x16
+ .byte 0x14, 0x12, 0x0e, 0x62, 0x50, 0xf8, 0xc2, 0xaf
+ .byte 0xd2, 0x95, 0x12, 0x06, 0xe3, 0xc2, 0x16, 0xe4
+ .byte 0xf5, 0x0e, 0xd2, 0xaf, 0x22, 0x7f, 0xe8, 0x7e
+ .byte 0xfd, 0x12, 0x0c, 0x79, 0x20, 0x07, 0x10, 0x20
+ .byte 0x0e, 0x0d, 0x12, 0x0e, 0x62, 0x50, 0xf5, 0xc2
+ .byte 0xaf, 0x12, 0x06, 0xe3, 0xd2, 0xaf, 0x22, 0x12
+ .byte 0x07, 0x2e, 0x22, 0xad, 0x07, 0xed, 0x30, 0xe6
+ .byte 0x04, 0xd2, 0x0f, 0x80, 0x02, 0xc2, 0x0f, 0xed
+ .byte 0x30, 0xe5, 0x05, 0x12, 0x0e, 0x8d, 0x80, 0x03
+ .byte 0x12, 0x0e, 0xe6, 0xed, 0x30, 0xe4, 0x05, 0x12
+ .byte 0x0e, 0x94, 0x80, 0x03, 0x12, 0x0e, 0xf0, 0xed
+ .byte 0x30, 0xe2, 0x04, 0xd2, 0x27, 0x80, 0x02, 0xc2
+ .byte 0x27, 0x7f, 0x02, 0x12, 0x0b, 0x6c, 0xed, 0x30
+ .byte 0xe1, 0x05, 0x12, 0x0f, 0x14, 0x80, 0x03, 0x12
+ .byte 0x0f, 0x11, 0xed, 0x30, 0xe0, 0x0b, 0x12, 0x0f
+ .byte 0x1a, 0x20, 0x11, 0x08, 0xd2, 0x11, 0xd2, 0x01
+ .byte 0x22, 0x12, 0x0f, 0x17, 0x22, 0x7f, 0x02, 0x12
+ .byte 0x00, 0x06, 0x20, 0x94, 0x42, 0xa2, 0x95, 0x92
+ .byte 0x18, 0x05, 0x0e, 0xe5, 0x0e, 0xb4, 0x01, 0x12
+ .byte 0x20, 0x18, 0x0a, 0xd2, 0x07, 0xd2, 0x0a, 0xd2
+ .byte 0x0d, 0xc2, 0x96, 0x80, 0x19, 0xe4, 0xf5, 0x0e
+ .byte 0x80, 0x14, 0xe5, 0x0e, 0xb4, 0x0b, 0x0f, 0xd2
+ .byte 0x0e, 0xd2, 0x10, 0xc2, 0x94, 0xd2, 0x13, 0xd2
+ .byte 0x0c, 0xe4, 0xf5, 0x0e, 0xc2, 0x07, 0xe5, 0x10
+ .byte 0xc3, 0x13, 0xf5, 0x10, 0xe5, 0x11, 0x13, 0xf5
+ .byte 0x11, 0x30, 0x18, 0x03, 0x43, 0x10, 0x80, 0x22
+ .byte 0x7f, 0x02, 0x12, 0x00, 0x06, 0x20, 0x96, 0x42
+ .byte 0xa2, 0x97, 0x92, 0x19, 0x05, 0x0c, 0xe5, 0x0c
+ .byte 0xb4, 0x01, 0x12, 0x20, 0x19, 0x0a, 0xd2, 0x04
+ .byte 0xd2, 0x0e, 0xd2, 0x10, 0xc2, 0x94, 0x80, 0x19
+ .byte 0xe4, 0xf5, 0x0c, 0x80, 0x14, 0xe5, 0x0c, 0xb4
+ .byte 0x0b, 0x0f, 0xd2, 0x0a, 0xd2, 0x0d, 0xc2, 0x96
+ .byte 0xc2, 0x13, 0xd2, 0x0c, 0xe4, 0xf5, 0x0c, 0xc2
+ .byte 0x04, 0xe5, 0x10, 0xc3, 0x13, 0xf5, 0x10, 0xe5
+ .byte 0x11, 0x13, 0xf5, 0x11, 0x30, 0x19, 0x03, 0x43
+ .byte 0x10, 0x80, 0x22, 0xd2, 0x21, 0x75, 0x30, 0xfe
+ .byte 0xd2, 0x22, 0xd2, 0x23, 0xc2, 0x24, 0xd2, 0x0a
+ .byte 0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x0e, 0xd2, 0x10
+ .byte 0xc2, 0x94, 0xa2, 0x23, 0x92, 0x27, 0x7f, 0x06
+ .byte 0x12, 0x0b, 0x6c, 0xa2, 0x24, 0x92, 0x27, 0x7f
+ .byte 0x07, 0x12, 0x0b, 0x6c, 0x30, 0x22, 0x0c, 0xa2
+ .byte 0x21, 0x92, 0x25, 0x85, 0x30, 0x31, 0x12, 0x08
+ .byte 0xbb, 0x80, 0x10, 0xa2, 0x21, 0x92, 0x26, 0x85
+ .byte 0x30, 0x32, 0x12, 0x0b, 0xf9, 0xc2, 0x92, 0xc2
+ .byte 0x93, 0xd2, 0x09, 0xc2, 0x0c, 0x22, 0x20, 0x04
+ .byte 0x03, 0x30, 0x07, 0x44, 0x7f, 0xe8, 0x7e, 0xfd
+ .byte 0x12, 0x0c, 0x79, 0x20, 0x04, 0x03, 0x30, 0x07
+ .byte 0x37, 0x12, 0x0e, 0x62, 0x50, 0xf5, 0xc2, 0xaf
+ .byte 0x20, 0x04, 0x03, 0x30, 0x07, 0x26, 0x30, 0x04
+ .byte 0x04, 0xc2, 0x1f, 0x80, 0x02, 0xd2, 0x1f, 0xe4
+ .byte 0xf5, 0x0c, 0xc2, 0x04, 0xf5, 0x0e, 0xc2, 0x07
+ .byte 0x12, 0x0e, 0xeb, 0x12, 0x0e, 0x80, 0xd2, 0xaf
+ .byte 0xa2, 0x1f, 0x92, 0x21, 0x75, 0x30, 0xff, 0x12
+ .byte 0x06, 0xe8, 0x80, 0xc7, 0xd2, 0xaf, 0x80, 0xc3
+ .byte 0x22, 0xe5, 0x19, 0x60, 0x03, 0xb4, 0x02, 0x09
+ .byte 0xe5, 0x0d, 0x90, 0x03, 0x63, 0x93, 0x6f, 0x60
+ .byte 0x0b, 0xe5, 0x19, 0x64, 0x01, 0x70, 0x2d, 0xef
+ .byte 0x64, 0xf0, 0x70, 0x28, 0x05, 0x19, 0xe5, 0x19
+ .byte 0xd3, 0x94, 0x02, 0x40, 0x24, 0xe4, 0xf5, 0x19
+ .byte 0x05, 0x0d, 0xe5, 0x0d, 0x94, 0x09, 0x40, 0x19
+ .byte 0x75, 0x2a, 0x05, 0xe4, 0xff, 0x12, 0x0c, 0x3b
+ .byte 0x7f, 0x07, 0x12, 0x0c, 0x3b, 0xd5, 0x2a, 0xf3
+ .byte 0xe4, 0xf5, 0x0d, 0x22, 0xe4, 0xf5, 0x0d, 0xf5
+ .byte 0x19, 0x22, 0xe5, 0x3b, 0x64, 0x15, 0x70, 0x41
+ .byte 0x12, 0x0c, 0xed, 0xe5, 0x3a, 0x30, 0xe0, 0x05
+ .byte 0x75, 0x26, 0x80, 0x80, 0x03, 0xe4, 0xf5, 0x26
+ .byte 0xe5, 0x3a, 0xc3, 0x13, 0xf5, 0x3a, 0xe5, 0x39
+ .byte 0x30, 0xe0, 0x03, 0x43, 0x3a, 0x80, 0xe5, 0x39
+ .byte 0xc3, 0x13, 0xf5, 0x39, 0xe5, 0x38, 0x30, 0xe0
+ .byte 0x03, 0x43, 0x39, 0x80, 0xc2, 0xb6, 0x90, 0xd0
+ .byte 0x01, 0xe4, 0xf0, 0xa3, 0xe5, 0x26, 0xf0, 0xa3
+ .byte 0xe5, 0x3a, 0xf0, 0xa3, 0xe5, 0x39, 0xf0, 0xd2
+ .byte 0xb6, 0x22, 0x20, 0x94, 0x37, 0x05, 0x0e, 0xe5
+ .byte 0x0e, 0xd3, 0x94, 0x08, 0x50, 0x12, 0xe5, 0x08
+ .byte 0x30, 0xe0, 0x04, 0xd2, 0x95, 0x80, 0x02, 0xc2
+ .byte 0x95, 0xe5, 0x08, 0xc3, 0x13, 0xf5, 0x08, 0x22
+ .byte 0xe5, 0x0e, 0xb4, 0x09, 0x05, 0xa2, 0x14, 0x92
+ .byte 0x95, 0x22, 0xe5, 0x0e, 0xb4, 0x0a, 0x03, 0xd2
+ .byte 0x95, 0x22, 0xe5, 0x0e, 0xb4, 0x0b, 0x05, 0xc2
+ .byte 0x16, 0xe4, 0xf5, 0x0e, 0x22, 0x20, 0x96, 0x37
+ .byte 0x05, 0x0c, 0xe5, 0x0c, 0xd3, 0x94, 0x08, 0x50
+ .byte 0x12, 0xe5, 0x08, 0x30, 0xe0, 0x04, 0xd2, 0x97
+ .byte 0x80, 0x02, 0xc2, 0x97, 0xe5, 0x08, 0xc3, 0x13
+ .byte 0xf5, 0x08, 0x22, 0xe5, 0x0c, 0xb4, 0x09, 0x05
+ .byte 0xa2, 0x14, 0x92, 0x97, 0x22, 0xe5, 0x0c, 0xb4
+ .byte 0x0a, 0x03, 0xd2, 0x97, 0x22, 0xe5, 0x0c, 0xb4
+ .byte 0x0b, 0x05, 0xc2, 0x16, 0xe4, 0xf5, 0x0c, 0x22
+ .byte 0x01, 0x0c, 0x00, 0xc1, 0x04, 0xc1, 0x0a, 0xc1
+ .byte 0x83, 0xc1, 0x0c, 0xc1, 0x09, 0xc1, 0x02, 0xc1
+ .byte 0x16, 0xc1, 0x08, 0x01, 0x0e, 0x00, 0xc1, 0x07
+ .byte 0xc1, 0x0e, 0xc1, 0x85, 0xc1, 0x8b, 0xc1, 0x86
+ .byte 0xc1, 0x8f, 0xc1, 0x12, 0xc1, 0x00, 0xc1, 0x11
+ .byte 0xc1, 0x01, 0xc1, 0x17, 0x01, 0x0d, 0x00, 0x01
+ .byte 0x19, 0x00, 0x01, 0x1a, 0x00, 0x01, 0x34, 0x03
+ .byte 0xc1, 0x29, 0x00, 0xa2, 0x25, 0x92, 0x26, 0x85
+ .byte 0x31, 0x32, 0x12, 0x0b, 0xf9, 0xc2, 0x92, 0xc2
+ .byte 0x93, 0x20, 0x25, 0x03, 0x20, 0x06, 0x06, 0x30
+ .byte 0x25, 0x1d, 0x30, 0x0b, 0x1a, 0x7f, 0x69, 0x7e
+ .byte 0x00, 0x12, 0x0c, 0x79, 0x12, 0x0e, 0x62, 0x50
+ .byte 0xfb, 0x12, 0x0e, 0xb0, 0x50, 0x09, 0x20, 0x25
+ .byte 0x04, 0xd2, 0x92, 0x80, 0x02, 0xd2, 0x93, 0xd2
+ .byte 0x09, 0x22, 0x90, 0x0f, 0xfc, 0xe4, 0x93, 0xfe
+ .byte 0x74, 0x01, 0x93, 0xff, 0xc3, 0x95, 0x3a, 0xf5
+ .byte 0x0b, 0xee, 0x95, 0x39, 0xf5, 0x0a, 0x90, 0x0f
+ .byte 0xfb, 0xe4, 0x93, 0xc3, 0x95, 0x38, 0xf5, 0x09
+ .byte 0xc3, 0xef, 0x95, 0x3a, 0xee, 0x95, 0x39, 0x50
+ .byte 0x02, 0x15, 0x09, 0xe5, 0x09, 0x30, 0xe7, 0x07
+ .byte 0xe4, 0xf5, 0x09, 0xf5, 0x0a, 0xf5, 0x0b, 0x22
+ .byte 0x05, 0x35, 0xaf, 0x35, 0xae, 0x07, 0xee, 0x14
+ .byte 0x13, 0x13, 0x13, 0x54, 0x1f, 0xfd, 0xee, 0x54
+ .byte 0x07, 0xff, 0x70, 0x06, 0xf5, 0x26, 0xf5, 0x27
+ .byte 0x80, 0x15, 0x74, 0xff, 0x7e, 0x00, 0xa8, 0x07
+ .byte 0x08, 0x80, 0x06, 0xce, 0xa2, 0xe7, 0x13, 0xce
+ .byte 0x13, 0xd8, 0xf8, 0xf5, 0x27, 0x8e, 0x26, 0xaf
+ .byte 0x05, 0xad, 0x27, 0x02, 0x0c, 0x5a, 0xe4, 0xff
+ .byte 0x7e, 0x01, 0xef, 0xc3, 0x94, 0x08, 0x50, 0x27
+ .byte 0xef, 0x60, 0x1d, 0x64, 0x01, 0x60, 0x19, 0xef
+ .byte 0x64, 0x03, 0x60, 0x14, 0xee, 0x44, 0x02, 0x54
+ .byte 0xfe, 0x90, 0xe0, 0x00, 0xf0, 0x54, 0xf4, 0xfd
+ .byte 0xee, 0x54, 0xf4, 0x6d, 0x60, 0x02, 0xd3, 0x22
+ .byte 0x0f, 0xee, 0x25, 0xe0, 0xfe, 0x80, 0xd3, 0xc3
+ .byte 0x22, 0xad, 0x07, 0xac, 0x06, 0xed, 0x24, 0xff
+ .byte 0xff, 0xec, 0x34, 0xff, 0xfe, 0xef, 0x78, 0x03
+ .byte 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0xff
+ .byte 0xed, 0x54, 0x07, 0xfd, 0x70, 0x04, 0xf5, 0x26
+ .byte 0x80, 0x0d, 0x74, 0xff, 0xa8, 0x05, 0x08, 0x80
+ .byte 0x02, 0xc3, 0x13, 0xd8, 0xfc, 0xf5, 0x26, 0xad
+ .byte 0x26, 0x02, 0x0a, 0xad, 0xc2, 0x28, 0x20, 0x29
+ .byte 0x0f, 0x12, 0x0f, 0x0d, 0x8f, 0x3b, 0xe5, 0x3b
+ .byte 0xb4, 0x15, 0x03, 0x75, 0x34, 0x1f, 0xd2, 0x29
+ .byte 0x12, 0x0a, 0x56, 0x8f, 0x35, 0xe5, 0x35, 0x30
+ .byte 0xe0, 0x0c, 0x12, 0x0d, 0x7d, 0x12, 0x09, 0x28
+ .byte 0xe4, 0xf5, 0x36, 0xf5, 0x37, 0x22, 0x12, 0x04
+ .byte 0x09, 0x8e, 0x36, 0x8f, 0x37, 0x22, 0x20, 0x0f
+ .byte 0x03, 0x7e, 0x00, 0x22, 0xbf, 0xf0, 0x07, 0xd2
+ .byte 0x15, 0x7e, 0xff, 0x7f, 0xff, 0x22, 0xef, 0xc3
+ .byte 0x94, 0x85, 0x40, 0x03, 0x7e, 0x00, 0x22, 0xef
+ .byte 0x90, 0x02, 0xce, 0x93, 0xfe, 0x70, 0x02, 0xfe
+ .byte 0x22, 0x30, 0x15, 0x03, 0x43, 0x06, 0x80, 0xc2
+ .byte 0x15, 0xaf, 0x06, 0x7e, 0x00, 0x22, 0xa2, 0x1a
+ .byte 0x92, 0x28, 0x05, 0x37, 0xe5, 0x37, 0x70, 0x02
+ .byte 0x05, 0x36, 0xc3, 0xe5, 0x36, 0x94, 0x80, 0x50
+ .byte 0x07, 0xaf, 0x37, 0xae, 0x36, 0x02, 0x09, 0x91
+ .byte 0xe5, 0x35, 0xc3, 0x94, 0x10, 0x50, 0x0e, 0x12
+ .byte 0x09, 0x28, 0x12, 0x0d, 0x7d, 0x12, 0x09, 0x28
+ .byte 0xe4, 0xf5, 0x36, 0xf5, 0x37, 0x22, 0xe4, 0xff
+ .byte 0x12, 0x0e, 0x23, 0x7e, 0xff, 0xe4, 0xf5, 0x26
+ .byte 0xe5, 0x26, 0xb4, 0x08, 0x07, 0x7f, 0x01, 0x12
+ .byte 0x0e, 0x23, 0x7e, 0xff, 0xee, 0xb5, 0x07, 0x03
+ .byte 0xaf, 0x26, 0x22, 0xee, 0xc3, 0x13, 0xfe, 0x05
+ .byte 0x26, 0xe5, 0x26, 0xd3, 0x94, 0x10, 0x40, 0xe0
+ .byte 0x7f, 0xff, 0x22, 0xe4, 0xff, 0x30, 0x0f, 0x02
+ .byte 0x7f, 0x40, 0x20, 0x05, 0x03, 0x43, 0x07, 0x20
+ .byte 0x20, 0x03, 0x03, 0x43, 0x07, 0x10, 0x90, 0xe0
+ .byte 0x00, 0xe0, 0x30, 0xe2, 0x03, 0x43, 0x07, 0x04
+ .byte 0x30, 0x0b, 0x03, 0x43, 0x07, 0x02, 0x30, 0x06
+ .byte 0x03, 0x43, 0x07, 0x01, 0x22, 0x8e, 0x27, 0x8f
+ .byte 0x28, 0x8d, 0x29, 0x12, 0x0e, 0x74, 0xe5, 0x27
+ .byte 0x24, 0xd0, 0xf5, 0x2a, 0xe5, 0x28, 0xf5, 0x2b
+ .byte 0x12, 0x0e, 0xa2, 0x85, 0x29, 0x2f, 0xab, 0x2b
+ .byte 0xad, 0x2a, 0xaf, 0x34, 0x12, 0x0b, 0x47, 0x12
+ .byte 0x0e, 0xa9, 0x02, 0x0d, 0xea, 0xc0, 0xe0, 0xc0
+ .byte 0xf0, 0xc0, 0xd0, 0x75, 0xd0, 0x00, 0xc0, 0x06
+ .byte 0xc0, 0x07, 0x20, 0x10, 0x0b, 0x30, 0x16, 0x05
+ .byte 0x12, 0x08, 0x0a, 0x80, 0x03, 0x12, 0x06, 0x4d
+ .byte 0xd0, 0x07, 0xd0, 0x06, 0xd0, 0xd0, 0xd0, 0xf0
+ .byte 0xd0, 0xe0, 0x32, 0xc0, 0xe0, 0xc0, 0xf0, 0xc0
+ .byte 0xd0, 0x75, 0xd0, 0x00, 0xc0, 0x06, 0xc0, 0x07
+ .byte 0x20, 0x0d, 0x0b, 0x30, 0x16, 0x05, 0x12, 0x08
+ .byte 0x45, 0x80, 0x03, 0x12, 0x06, 0x98, 0xd0, 0x07
+ .byte 0xd0, 0x06, 0xd0, 0xd0, 0xd0, 0xf0, 0xd0, 0xe0
+ .byte 0x32, 0xd0, 0x83, 0xd0, 0x82, 0xf8, 0xe4, 0x93
+ .byte 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0d, 0xa3
+ .byte 0xa3, 0x93, 0xf8, 0x74, 0x01, 0x93, 0xf5, 0x82
+ .byte 0x88, 0x83, 0xe4, 0x73, 0x74, 0x02, 0x93, 0x68
+ .byte 0x60, 0xef, 0xa3, 0xa3, 0xa3, 0x80, 0xdf, 0xae
+ .byte 0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90, 0xd0
+ .byte 0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e, 0x33
+ .byte 0x7f, 0x02, 0x12, 0x0d, 0x51, 0xaf, 0x2f, 0x12
+ .byte 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00
+ .byte 0xe5, 0x1a, 0xf0, 0x22, 0x74, 0x01, 0xa8, 0x07
+ .byte 0x08, 0x80, 0x02, 0xc3, 0x33, 0xd8, 0xfc, 0xff
+ .byte 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02, 0xfe, 0xef
+ .byte 0x30, 0x27, 0x04, 0x42, 0x06, 0x80, 0x03, 0xf4
+ .byte 0x52, 0x06, 0x90, 0xe0, 0x00, 0xee, 0xf0, 0x22
+ .byte 0x12, 0x0e, 0x07, 0x40, 0x05, 0x12, 0x01, 0x05
+ .byte 0x80, 0xf6, 0x12, 0x0e, 0xc8, 0x12, 0x0e, 0xd4
+ .byte 0xc2, 0x1f, 0x75, 0x2f, 0xee, 0xa2, 0x06, 0x92
+ .byte 0x20, 0x12, 0x0d, 0xb8, 0x90, 0xd0, 0x00, 0xe0
+ .byte 0x30, 0xe1, 0xf9, 0x22, 0xae, 0x03, 0xab, 0x05
+ .byte 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a
+ .byte 0xf0, 0xad, 0x07, 0x8e, 0x33, 0x7f, 0x03, 0x12
+ .byte 0x0d, 0x51, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10
+ .byte 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0xe5
+ .byte 0x1a, 0x54, 0x9f, 0xfd, 0x44, 0x20, 0xfe, 0x7c
+ .byte 0x08, 0xef, 0x25, 0xe0, 0xff, 0x90, 0xd0, 0x00
+ .byte 0xed, 0xf0, 0xe0, 0x30, 0xe4, 0x03, 0x43, 0x07
+ .byte 0x01, 0x90, 0xd0, 0x00, 0xee, 0xf0, 0xdc, 0xe9
+ .byte 0x22, 0x90, 0xf0, 0x00, 0xe5, 0x32, 0xf0, 0xf5
+ .byte 0x0f, 0xa2, 0x26, 0x92, 0x27, 0x7f, 0x05, 0x12
+ .byte 0x0b, 0x6c, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02
+ .byte 0x54, 0xfe, 0xfe, 0xf0, 0x44, 0x01, 0xf0, 0xee
+ .byte 0xf0, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00
+ .byte 0xe5, 0x1a, 0xf0, 0x7f, 0x9f, 0x12, 0x0c, 0xd0
+ .byte 0x12, 0x0b, 0xd7, 0x12, 0x0b, 0xd7, 0x12, 0x0b
+ .byte 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00, 0xe5
+ .byte 0x1a, 0xf0, 0x22, 0x8f, 0x2b, 0x7f, 0xed, 0x12
+ .byte 0x05, 0x2f, 0xaf, 0x2b, 0x12, 0x05, 0x2f, 0x75
+ .byte 0x2c, 0x0a, 0x7f, 0xe8, 0x7e, 0xfd, 0x12, 0x0c
+ .byte 0x79, 0x12, 0x0e, 0x62, 0x50, 0xfb, 0xd5, 0x2c
+ .byte 0xf1, 0x22, 0x8f, 0x28, 0x8d, 0x29, 0x12, 0x0e
+ .byte 0x74, 0x12, 0x0e, 0xa2, 0xe5, 0x28, 0x24, 0xfe
+ .byte 0xfb, 0x85, 0x29, 0x2f, 0x7d, 0xef, 0xaf, 0x34
+ .byte 0x12, 0x0b, 0x47, 0x12, 0x0e, 0xa9, 0x02, 0x0d
+ .byte 0xea, 0xad, 0x07, 0xac, 0x06, 0xc2, 0x8c, 0xed
+ .byte 0xf4, 0xff, 0xec, 0xf4, 0xfe, 0xef, 0x24, 0x01
+ .byte 0xfd, 0xe4, 0x3e, 0xf5, 0x8c, 0xaf, 0x05, 0x8f
+ .byte 0x8a, 0xc2, 0x8d, 0xd2, 0x8c, 0x22, 0xad, 0x07
+ .byte 0xac, 0x06, 0xc2, 0xca, 0xed, 0xf4, 0xff, 0xec
+ .byte 0xf4, 0xfe, 0xef, 0x24, 0x01, 0xfd, 0xe4, 0x3e
+ .byte 0xf5, 0xcd, 0xaf, 0x05, 0x8f, 0xcc, 0xc2, 0xcf
+ .byte 0xd2, 0xca, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0
+ .byte 0x00, 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c
+ .byte 0xd0, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90
+ .byte 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xef, 0x13, 0x22
+ .byte 0xe5, 0x1a, 0x54, 0x9f, 0xfe, 0x44, 0x40, 0xfd
+ .byte 0x7c, 0x08, 0x90, 0xd0, 0x00, 0xef, 0x33, 0xff
+ .byte 0x50, 0x03, 0xed, 0x80, 0x01, 0xee, 0xf0, 0x44
+ .byte 0x20, 0xf0, 0xdc, 0xf1, 0x22, 0x12, 0x0f, 0x04
+ .byte 0x8e, 0x39, 0x8f, 0x3a, 0x12, 0x0f, 0x1d, 0x8f
+ .byte 0x38, 0xe5, 0x38, 0x30, 0xe1, 0x03, 0x43, 0x39
+ .byte 0x80, 0xe5, 0x38, 0x13, 0x13, 0x54, 0x3f, 0xf5
+ .byte 0x38, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00
+ .byte 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c, 0xd0
+ .byte 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0
+ .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0xc8
+ .byte 0x12, 0x0e, 0xd4, 0x90, 0xd0, 0x00, 0xe0, 0x20
+ .byte 0xe1, 0x08, 0x12, 0x03, 0x6c, 0x12, 0x01, 0x05
+ .byte 0x80, 0xf1, 0x22, 0x12, 0x0c, 0xed, 0x12, 0x08
+ .byte 0xf2, 0xe5, 0x09, 0x70, 0x0b, 0xe5, 0x0a, 0x70
+ .byte 0x07, 0xe5, 0x0b, 0x70, 0x03, 0x12, 0x0e, 0xda
+ .byte 0x22, 0x8d, 0x31, 0x8b, 0x32, 0x12, 0x0c, 0xd0
+ .byte 0xaf, 0x31, 0x12, 0x0c, 0xd0, 0xaf, 0x32, 0x12
+ .byte 0x0c, 0xd0, 0xaf, 0x33, 0x02, 0x0c, 0xd0, 0x53
+ .byte 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0
+ .byte 0x12, 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0
+ .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0x74
+ .byte 0x12, 0x0e, 0xa2, 0xe4, 0xfb, 0x7d, 0xd0, 0xaf
+ .byte 0x34, 0x12, 0x00, 0xe0, 0x12, 0x0e, 0xa9, 0x02
+ .byte 0x0d, 0xea, 0x53, 0x1a, 0xfb, 0x90, 0xd0, 0x00
+ .byte 0xe5, 0x1a, 0xf0, 0x53, 0x1a, 0xfd, 0xe5, 0x1a
+ .byte 0xf0, 0x7f, 0x3c, 0x02, 0x00, 0x06, 0x30, 0x09
+ .byte 0x0e, 0x12, 0x0e, 0xb0, 0x40, 0x09, 0xc2, 0x92
+ .byte 0xc2, 0x93, 0xc2, 0x09, 0x12, 0x0e, 0x7d, 0x22
+ .byte 0xa2, 0x1f, 0x92, 0x21, 0x85, 0x2f, 0x30, 0xa2
+ .byte 0x20, 0x92, 0x22, 0xc2, 0x23, 0xc2, 0x24, 0x02
+ .byte 0x06, 0xee, 0xef, 0xc4, 0x54, 0x0f, 0x90, 0x03
+ .byte 0x53, 0x93, 0xfe, 0xef, 0x54, 0x0f, 0x93, 0x2e
+ .byte 0xff, 0x22, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02
+ .byte 0x54, 0xfe, 0xfe, 0xf0, 0x54, 0xfd, 0xf0, 0xee
+ .byte 0xf0, 0x22, 0x12, 0x0e, 0xa2, 0x12, 0x0c, 0xb3
+ .byte 0x92, 0x1b, 0x12, 0x0e, 0xa9, 0x20, 0x1b, 0xf2
+ .byte 0x22, 0x30, 0x05, 0x09, 0x20, 0x0e, 0x06, 0x20
+ .byte 0x02, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x22, 0x30
+ .byte 0x03, 0x09, 0x20, 0x0a, 0x06, 0x20, 0x02, 0x03
+ .byte 0xd3, 0x80, 0x01, 0xc3, 0x22, 0xaa, 0x06, 0xea
+ .byte 0x24, 0xd0, 0xfd, 0xef, 0xfb, 0xaf, 0x34, 0x12
+ .byte 0x0b, 0xb4, 0x22, 0xef, 0x24, 0xfe, 0xfb, 0x7d
+ .byte 0xef, 0xaf, 0x34, 0x12, 0x0b, 0xb4, 0x22, 0xd2
+ .byte 0x02, 0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x10, 0xc2
+ .byte 0x94, 0x22, 0xef, 0x90, 0x02, 0xc9, 0x93, 0x6d
+ .byte 0x60, 0x02, 0x80, 0xfe, 0x22, 0x12, 0x0d, 0xf9
+ .byte 0x50, 0x04, 0xc2, 0x10, 0xd2, 0x94, 0x22, 0x12
+ .byte 0x0e, 0x07, 0x50, 0x04, 0xc2, 0x0d, 0xd2, 0x96
+ .byte 0x22, 0xe5, 0x89, 0x54, 0xf0, 0x44, 0x01, 0xf5
+ .byte 0x89, 0x22, 0x30, 0x8d, 0x04, 0xc2, 0x8c, 0xd3
+ .byte 0x22, 0xc3, 0x22, 0x30, 0xcf, 0x04, 0xc2, 0xca
+ .byte 0xd3, 0x22, 0xc3, 0x22, 0x12, 0x0e, 0xa2, 0x12
+ .byte 0x0e, 0xfa, 0x02, 0x0e, 0xa9, 0x12, 0x0e, 0xeb
+ .byte 0xc2, 0x0e, 0x02, 0x0e, 0x45, 0xc2, 0x02, 0x12
+ .byte 0x0e, 0x4f, 0x02, 0x0e, 0x45, 0xc2, 0x05, 0xd2
+ .byte 0x10, 0xc2, 0x94, 0x22, 0xc2, 0x03, 0xd2, 0x0d
+ .byte 0xc2, 0x96, 0x22, 0x90, 0xd0, 0x00, 0xe5, 0x1a
+ .byte 0xf0, 0x22, 0x30, 0x28, 0x03, 0x12, 0x0b, 0x90
+ .byte 0x22, 0x30, 0x28, 0x03, 0x12, 0x0d, 0x92, 0x22
+ .byte 0x90, 0xe0, 0x00, 0xe0, 0x13, 0x22, 0x53, 0x1a
+ .byte 0xfe, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x01, 0x02
+ .byte 0x0e, 0x9b, 0x53, 0x1a, 0xfd, 0x02, 0x0e, 0x9b
+ .byte 0x43, 0x1a, 0x02, 0x02, 0x0e, 0x9b, 0x53, 0x1a
+ .byte 0xfb, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x04, 0x02
+ .byte 0x0e, 0x9b, 0x53, 0x1a, 0x7f, 0x02, 0x0e, 0x9b
+ .byte 0x43, 0x1a, 0x80, 0x02, 0x0e, 0x9b, 0xd2, 0x05
+ .byte 0x02, 0x0e, 0x45, 0xc2, 0x0a, 0x02, 0x0e, 0x4f
+ .byte 0xd2, 0x03, 0x02, 0x0e, 0x4f, 0x8f, 0x1a, 0x02
+ .byte 0x0e, 0x9b, 0x7f, 0x06, 0x02, 0x0d, 0x67, 0x7f
+ .byte 0x04, 0x02, 0x0d, 0x67, 0xae, 0x36, 0xaf, 0x37
+ .byte 0x22, 0xe4, 0xf5, 0xc8, 0x22, 0x12, 0x0c, 0x1a
+ .byte 0x22, 0xc2, 0x0b, 0x22, 0xd2, 0x0b, 0x22, 0xc2
+ .byte 0x06, 0x22, 0xd2, 0x06, 0x22, 0xaf, 0x35, 0x22
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 1e5d4bd..d6413c9 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -50,6 +50,8 @@ config VENDOR_COMPAQ
bool "Compaq"
config VENDOR_DIGITALLOGIC
bool "DIGITAL-LOGIC"
+config VENDOR_DMP
+ bool "DMP"
config VENDOR_EAGLELION
bool "EagleLion"
config VENDOR_ECS
@@ -160,6 +162,7 @@ source "src/mainboard/biostar/Kconfig"
source "src/mainboard/broadcom/Kconfig"
source "src/mainboard/compaq/Kconfig"
source "src/mainboard/digitallogic/Kconfig"
+source "src/mainboard/dmp/Kconfig"
source "src/mainboard/eaglelion/Kconfig"
source "src/mainboard/ecs/Kconfig"
source "src/mainboard/emulation/Kconfig"
diff --git a/src/mainboard/dmp/Kconfig b/src/mainboard/dmp/Kconfig
new file mode 100644
index 0000000..c3196d2
--- /dev/null
+++ b/src/mainboard/dmp/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if VENDOR_DMP
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_DMP_EX
+ bool "Vortex86EX"
+
+endchoice
+
+source "src/mainboard/dmp/vortex86ex/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "DMP"
+
+endif # VENDOR_DMP
diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig
new file mode 100644
index 0000000..7b81c85
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/Kconfig
@@ -0,0 +1,1651 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_DMP_EX
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_DMP_VORTEX86EX
+ select NORTHBRIDGE_DMP_VORTEX86EX
+ select SOUTHBRIDGE_DMP_VORTEX86EX
+ select HAVE_PIRQ_TABLE
+ select BOARD_ROMSIZE_KB_256
+ select ROMCC
+ select DEFAULT_EARLY_CONSOLE
+ select HAVE_DEBUG_RAM_SETUP
+
+config MAINBOARD_DIR
+ string
+ default dmp/vortex86ex
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Vortex86EX"
+
+config IRQ_SLOT_COUNT
+ int
+ default 12
+
+config ID_SECTION_OFFSET
+ # Vortex86 ROM fixed data areas used too big range, we need
+ # to move ID from default address to another place.
+ # 18K below top of ROM should be ok.
+ hex
+ default 0x4800
+
+# ROM Strap PLL config setting :
+
+choice
+ prompt "ROM Strap PLL config"
+ default PLL_300_300_33
+
+config PLL_200_200_33
+ bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz"
+
+config PLL_300_300_33
+ bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz"
+
+config PLL_300_300_100
+ bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz"
+
+config PLL_400_200_33
+ bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz"
+
+config PLL_400_200_100
+ bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz"
+
+config PLL_400_400_33
+ bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz"
+
+config PLL_500_250_33
+ bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz"
+
+config PLL_500_500_33
+ bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz"
+
+config PLL_400_300_33
+ bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz"
+
+config PLL_400_300_100
+ bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz"
+
+config PLL_444_333_33
+ bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz"
+
+config PLL_466_350_33
+ bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz"
+
+config PLL_500_375_33
+ bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz"
+
+endchoice
+
+menu "On-Chip Device Power Down Control"
+
+ config TEMP_POWERDOWN
+ bool "Temperature sensor power-down"
+
+ config SATA_POWERDOWN
+ bool "SATA power-down"
+
+ config ADC_POWERDOWN
+ bool "ADC power-down"
+
+ config PCIE0_POWERDOWN
+ bool "PCIE0 power-down"
+
+ config MAC_POWERDOWN
+ bool "MAC power-down"
+
+ config USB1_POWERDOWN
+ bool "USB2.0 Host Controller 1 power-down"
+
+ config IDE_POWERDOWN
+ bool "IDE power-down"
+
+endmenu
+
+menu "Watchdog Timer setting"
+
+config WDT1_INITIALIZE
+ bool "Initialize WDT1"
+ default n
+
+config WDT1_ENABLE
+ depends on WDT1_INITIALIZE
+ bool "Enable WDT1"
+ default n
+
+choice
+ depends on WDT1_INITIALIZE
+ prompt "WDT1 Signal Select"
+ default WDT1_SIGNAL_RESET
+
+config WDT1_SINGAL_NMI
+ bool "NMI"
+config WDT1_SIGNAL_RESET
+ bool "Reset"
+config WDT1_SIGNAL_SMI
+ bool "SMI"
+
+endchoice
+
+endmenu
+
+menu "IDE controller setting"
+
+choice
+ prompt "Operation Mode"
+ default IDE_NATIVE_MODE
+
+config IDE_NATIVE_MODE
+ bool "Native Mode"
+config IDE_LEGACY_MODE
+ bool "Legacy Mode"
+
+endchoice
+
+config IDE1_ENABLE
+ bool "IDE Primary channel Enable"
+ default y
+
+config IDE2_ENABLE
+ bool "IDE Secondary channel Enable"
+ default y
+
+config IDE_STANDARD_COMPATIBLE
+ bool "Standard IDE Compatible"
+ default n
+
+config IDE_COMPATIBLE_SELECTION
+ depends on IDE_STANDARD_COMPATIBLE
+ hex "IDE Compatible Selection"
+ default 0x808624db
+
+endmenu
+
+# GPIO setting :
+menu "GPIO setting"
+
+# Begin of GPIO0
+config GPIO_P0_ENABLE
+ bool "GPIO port 0 Enable"
+ default n
+
+config GPIO_P0_DATA_ADDR
+ hex "GPIO port 0 data address"
+ depends on GPIO_P0_ENABLE
+
+config GPIO_P0_DIR_ADDR
+ hex "GPIO port 0 direction address"
+ depends on GPIO_P0_ENABLE
+
+config GPIO_P0_INIT_DIR
+ hex "GPIO port 0 initial direction"
+ default 0x00
+ depends on GPIO_P0_ENABLE
+
+config GPIO_P0_INIT_DATA
+ hex "GPIO port 0 initial data"
+ depends on GPIO_P0_ENABLE
+# end of GPIO0
+
+# Begin of GPIO1
+config GPIO_P1_ENABLE
+ bool "GPIO port 1 Enable"
+ default n
+
+config GPIO_P1_DATA_ADDR
+ hex "GPIO port 1 data address"
+ depends on GPIO_P1_ENABLE
+
+config GPIO_P1_DIR_ADDR
+ hex "GPIO port 1 direction address"
+ depends on GPIO_P1_ENABLE
+
+config GPIO_P1_INIT_DIR
+ hex "GPIO port 1 initial direction"
+ default 0x00
+ depends on GPIO_P1_ENABLE
+
+config GPIO_P1_INIT_DATA
+ hex "GPIO port 1 initial data"
+ depends on GPIO_P1_ENABLE
+# end of GPIO1
+
+# Begin of GPIO2
+config GPIO_P2_ENABLE
+ bool "GPIO port 2 Enable"
+ default n
+
+config GPIO_P2_DATA_ADDR
+ hex "GPIO port 2 data address"
+ depends on GPIO_P2_ENABLE
+
+config GPIO_P2_DIR_ADDR
+ hex "GPIO port 2 direction address"
+ depends on GPIO_P2_ENABLE
+
+config GPIO_P2_INIT_DIR
+ hex "GPIO port 2 initial direction"
+ default 0x00
+ depends on GPIO_P2_ENABLE
+
+config GPIO_P2_INIT_DATA
+ hex "GPIO port 2 initial data"
+ depends on GPIO_P2_ENABLE
+# end of GPIO2
+
+# Begin of GPIO3
+config GPIO_P3_ENABLE
+ bool "GPIO port 3 Enable"
+ default n
+
+config GPIO_P3_DATA_ADDR
+ hex "GPIO port 3 data address"
+ depends on GPIO_P3_ENABLE
+
+config GPIO_P3_DIR_ADDR
+ hex "GPIO port 3 direction address"
+ depends on GPIO_P3_ENABLE
+
+config GPIO_P3_INIT_DIR
+ hex "GPIO port 3 initial direction"
+ default 0x00
+ depends on GPIO_P3_ENABLE
+
+config GPIO_P3_INIT_DATA
+ hex "GPIO port 3 initial data"
+ depends on GPIO_P3_ENABLE
+# end of GPIO3
+
+# Begin of GPIO4
+config GPIO_P4_ENABLE
+ bool "GPIO port 4 Enable"
+ default n
+
+config GPIO_P4_DATA_ADDR
+ hex "GPIO port 4 data address"
+ depends on GPIO_P4_ENABLE
+
+config GPIO_P4_DIR_ADDR
+ hex "GPIO port 4 direction address"
+ depends on GPIO_P4_ENABLE
+
+config GPIO_P4_INIT_DIR
+ hex "GPIO port 4 initial direction"
+ default 0x00
+ depends on GPIO_P4_ENABLE
+
+config GPIO_P4_INIT_DATA
+ hex "GPIO port 4 initial data"
+ depends on GPIO_P4_ENABLE
+# end of GPIO4
+
+# Begin of GPIO5
+config GPIO_P5_ENABLE
+ bool "GPIO port 5 Enable"
+ default n
+
+config GPIO_P5_DATA_ADDR
+ hex "GPIO port 5 data address"
+ depends on GPIO_P5_ENABLE
+
+config GPIO_P5_DIR_ADDR
+ hex "GPIO port 5 direction address"
+ depends on GPIO_P5_ENABLE
+
+config GPIO_P5_INIT_DIR
+ hex "GPIO port 5 initial direction"
+ default 0x00
+ depends on GPIO_P5_ENABLE
+
+config GPIO_P5_INIT_DATA
+ hex "GPIO port 5 initial data"
+ depends on GPIO_P5_ENABLE
+# end of GPIO5
+
+# Begin of GPIO6
+config GPIO_P6_ENABLE
+ bool "GPIO port 6 Enable"
+ default n
+
+config GPIO_P6_DATA_ADDR
+ hex "GPIO port 6 data address"
+ depends on GPIO_P6_ENABLE
+
+config GPIO_P6_DIR_ADDR
+ hex "GPIO port 6 direction address"
+ depends on GPIO_P6_ENABLE
+
+config GPIO_P6_INIT_DIR
+ hex "GPIO port 6 initial direction"
+ default 0x00
+ depends on GPIO_P6_ENABLE
+
+config GPIO_P6_INIT_DATA
+ hex "GPIO port 6 initial data"
+ depends on GPIO_P6_ENABLE
+# end of GPIO6
+
+# Begin of GPIO7
+config GPIO_P7_ENABLE
+ bool "GPIO port 7 Enable"
+ default n
+
+config GPIO_P7_DATA_ADDR
+ hex "GPIO port 7 data address"
+ depends on GPIO_P7_ENABLE
+
+config GPIO_P7_DIR_ADDR
+ hex "GPIO port 7 direction address"
+ depends on GPIO_P7_ENABLE
+
+config GPIO_P7_INIT_DIR
+ hex "GPIO port 7 initial direction"
+ default 0x00
+ depends on GPIO_P7_ENABLE
+
+config GPIO_P7_INIT_DATA
+ hex "GPIO port 7 initial data"
+ depends on GPIO_P7_ENABLE
+# end of GPIO7
+
+# Begin of GPIO8
+config GPIO_P8_ENABLE
+ bool "GPIO port 8 Enable"
+ default n
+
+config GPIO_P8_DATA_ADDR
+ hex "GPIO port 8 data address"
+ depends on GPIO_P8_ENABLE
+
+config GPIO_P8_DIR_ADDR
+ hex "GPIO port 8 direction address"
+ depends on GPIO_P8_ENABLE
+
+config GPIO_P8_INIT_DIR
+ hex "GPIO port 8 initial direction"
+ default 0x00
+ depends on GPIO_P8_ENABLE
+
+config GPIO_P8_INIT_DATA
+ hex "GPIO port 8 initial data"
+ depends on GPIO_P8_ENABLE
+# end of GPIO8
+
+# Begin of GPIO9
+config GPIO_P9_ENABLE
+ bool "GPIO port 9 Enable"
+ default n
+
+config GPIO_P9_DATA_ADDR
+ hex "GPIO port 9 data address"
+ depends on GPIO_P9_ENABLE
+
+config GPIO_P9_DIR_ADDR
+ hex "GPIO port 9 direction address"
+ depends on GPIO_P9_ENABLE
+
+config GPIO_P9_INIT_DIR
+ hex "GPIO port 9 initial direction"
+ default 0x00
+ depends on GPIO_P9_ENABLE
+
+config GPIO_P9_INIT_DATA
+ hex "GPIO port 9 initial data"
+ depends on GPIO_P9_ENABLE
+# end of GPIO9
+
+endmenu
+
+# UART setting :
+menu "UART setting"
+
+# Begin of UART1
+config UART1_ENABLE
+ bool "UART1 Enable"
+ default y
+
+choice
+ prompt "UART1 I/O port"
+ default UART1_IO_PORT_3F8
+ depends on UART1_ENABLE
+
+config UART1_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART1_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART1_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART1_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART1_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART1_IO_PORT_OTHER_INPUT
+ hex "UART1 I/O port"
+ depends on UART1_ENABLE && UART1_IO_PORT_OTHER
+
+config UART1_IO
+ hex
+ depends on UART1_ENABLE
+ default 0x3f8 if UART1_IO_PORT_3F8
+ default 0x2f8 if UART1_IO_PORT_2F8
+ default 0x3e8 if UART1_IO_PORT_3E8
+ default 0x2e8 if UART1_IO_PORT_2E8
+ default UART1_IO_PORT_OTHER_INPUT if UART1_IO_PORT_OTHER
+
+choice
+ prompt "UART1 IRQ"
+ default UART1_IRQ4
+ depends on UART1_ENABLE
+
+config UART1_IRQ_DISABLE
+ bool "Disable"
+config UART1_IRQ3
+ bool "IRQ3, COM2"
+config UART1_IRQ4
+ bool "IRQ4, COM1"
+config UART1_IRQ5
+ bool "IRQ5"
+config UART1_IRQ6
+ bool "IRQ6"
+config UART1_IRQ7
+ bool "IRQ7"
+config UART1_IRQ9
+ bool "IRQ9"
+config UART1_IRQ10
+ bool "IRQ10, COM3"
+config UART1_IRQ11
+ bool "IRQ11, COM4"
+config UART1_IRQ12
+ bool "IRQ12"
+config UART1_IRQ14
+ bool "IRQ14"
+config UART1_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART1_IRQ
+ int
+ depends on UART1_ENABLE
+ default 0 if UART1_IRQ_DISABLE
+ default 3 if UART1_IRQ3
+ default 4 if UART1_IRQ4
+ default 5 if UART1_IRQ5
+ default 6 if UART1_IRQ6
+ default 7 if UART1_IRQ7
+ default 9 if UART1_IRQ9
+ default 10 if UART1_IRQ10
+ default 11 if UART1_IRQ11
+ default 12 if UART1_IRQ12
+ default 14 if UART1_IRQ14
+ default 15 if UART1_IRQ15
+
+choice
+ prompt "UART1 Baud rate"
+ default UART1_BAUD_115200
+ depends on UART1_ENABLE
+
+config UART1_BAUD_115200
+ bool "115200"
+config UART1_BAUD_57600
+ bool "57600"
+config UART1_BAUD_38400
+ bool "38400"
+config UART1_BAUD_19200
+ bool "19200"
+config UART1_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART1_BAUD
+ int
+ depends on UART1_ENABLE
+ default 115200 if UART1_BAUD_115200
+ default 57600 if UART1_BAUD_57600
+ default 38400 if UART1_BAUD_38400
+ default 19200 if UART1_BAUD_19200
+ default 9600 if UART1_BAUD_9600
+# end of UART1
+
+# Begin of UART2
+config UART2_ENABLE
+ bool "UART2 Enable"
+ default y
+
+choice
+ prompt "UART2 I/O port"
+ default UART2_IO_PORT_2F8
+ depends on UART2_ENABLE
+
+config UART2_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART2_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART2_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART2_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART2_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART2_IO_PORT_OTHER_INPUT
+ hex "UART2 I/O port"
+ depends on UART2_ENABLE && UART2_IO_PORT_OTHER
+
+config UART2_IO
+ hex
+ depends on UART2_ENABLE
+ default 0x3f8 if UART2_IO_PORT_3F8
+ default 0x2f8 if UART2_IO_PORT_2F8
+ default 0x3e8 if UART2_IO_PORT_3E8
+ default 0x2e8 if UART2_IO_PORT_2E8
+ default UART2_IO_PORT_OTHER_INPUT if UART2_IO_PORT_OTHER
+
+choice
+ prompt "UART2 IRQ"
+ default UART2_IRQ3
+ depends on UART2_ENABLE
+
+config UART2_IRQ_DISABLE
+ bool "Disable"
+config UART2_IRQ3
+ bool "IRQ3, COM2"
+config UART2_IRQ4
+ bool "IRQ4, COM1"
+config UART2_IRQ5
+ bool "IRQ5"
+config UART2_IRQ6
+ bool "IRQ6"
+config UART2_IRQ7
+ bool "IRQ7"
+config UART2_IRQ9
+ bool "IRQ9"
+config UART2_IRQ10
+ bool "IRQ10, COM3"
+config UART2_IRQ11
+ bool "IRQ11, COM4"
+config UART2_IRQ12
+ bool "IRQ12"
+config UART2_IRQ14
+ bool "IRQ14"
+config UART2_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART2_IRQ
+ int
+ depends on UART2_ENABLE
+ default 0 if UART2_IRQ_DISABLE
+ default 3 if UART2_IRQ3
+ default 4 if UART2_IRQ4
+ default 5 if UART2_IRQ5
+ default 6 if UART2_IRQ6
+ default 7 if UART2_IRQ7
+ default 9 if UART2_IRQ9
+ default 10 if UART2_IRQ10
+ default 11 if UART2_IRQ11
+ default 12 if UART2_IRQ12
+ default 14 if UART2_IRQ14
+ default 15 if UART2_IRQ15
+
+choice
+ prompt "UART2 Baud rate"
+ default UART2_BAUD_115200
+ depends on UART2_ENABLE
+
+config UART2_BAUD_115200
+ bool "115200"
+config UART2_BAUD_57600
+ bool "57600"
+config UART2_BAUD_38400
+ bool "38400"
+config UART2_BAUD_19200
+ bool "19200"
+config UART2_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART2_BAUD
+ int
+ depends on UART2_ENABLE
+ default 115200 if UART2_BAUD_115200
+ default 57600 if UART2_BAUD_57600
+ default 38400 if UART2_BAUD_38400
+ default 19200 if UART2_BAUD_19200
+ default 9600 if UART2_BAUD_9600
+# end of UART2
+
+# Begin of UART3
+config UART3_ENABLE
+ bool "UART3 Enable"
+ default y
+
+choice
+ prompt "UART3 I/O port"
+ default UART3_IO_PORT_3E8
+ depends on UART3_ENABLE
+
+config UART3_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART3_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART3_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART3_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART3_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART3_IO_PORT_OTHER_INPUT
+ hex "UART3 I/O port"
+ depends on UART3_ENABLE && UART3_IO_PORT_OTHER
+
+config UART3_IO
+ hex
+ depends on UART3_ENABLE
+ default 0x3f8 if UART3_IO_PORT_3F8
+ default 0x2f8 if UART3_IO_PORT_2F8
+ default 0x3e8 if UART3_IO_PORT_3E8
+ default 0x2e8 if UART3_IO_PORT_2E8
+ default UART3_IO_PORT_OTHER_INPUT if UART3_IO_PORT_OTHER
+
+choice
+ prompt "UART3 IRQ"
+ default UART3_IRQ10
+ depends on UART3_ENABLE
+
+config UART3_IRQ_DISABLE
+ bool "Disable"
+config UART3_IRQ3
+ bool "IRQ3, COM2"
+config UART3_IRQ4
+ bool "IRQ4, COM1"
+config UART3_IRQ5
+ bool "IRQ5"
+config UART3_IRQ6
+ bool "IRQ6"
+config UART3_IRQ7
+ bool "IRQ7"
+config UART3_IRQ9
+ bool "IRQ9"
+config UART3_IRQ10
+ bool "IRQ10, COM3"
+config UART3_IRQ11
+ bool "IRQ11, COM4"
+config UART3_IRQ12
+ bool "IRQ12"
+config UART3_IRQ14
+ bool "IRQ14"
+config UART3_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART3_IRQ
+ int
+ depends on UART3_ENABLE
+ default 0 if UART3_IRQ_DISABLE
+ default 3 if UART3_IRQ3
+ default 4 if UART3_IRQ4
+ default 5 if UART3_IRQ5
+ default 6 if UART3_IRQ6
+ default 7 if UART3_IRQ7
+ default 9 if UART3_IRQ9
+ default 10 if UART3_IRQ10
+ default 11 if UART3_IRQ11
+ default 12 if UART3_IRQ12
+ default 14 if UART3_IRQ14
+ default 15 if UART3_IRQ15
+
+choice
+ prompt "UART3 Baud rate"
+ default UART3_BAUD_115200
+ depends on UART3_ENABLE
+
+config UART3_BAUD_115200
+ bool "115200"
+config UART3_BAUD_57600
+ bool "57600"
+config UART3_BAUD_38400
+ bool "38400"
+config UART3_BAUD_19200
+ bool "19200"
+config UART3_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART3_BAUD
+ int
+ depends on UART3_ENABLE
+ default 115200 if UART3_BAUD_115200
+ default 57600 if UART3_BAUD_57600
+ default 38400 if UART3_BAUD_38400
+ default 19200 if UART3_BAUD_19200
+ default 9600 if UART3_BAUD_9600
+# end of UART3
+
+# Begin of UART4
+config UART4_ENABLE
+ bool "UART4 Enable"
+ default y
+
+choice
+ prompt "UART4 I/O port"
+ default UART4_IO_PORT_2E8
+ depends on UART4_ENABLE
+
+config UART4_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART4_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART4_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART4_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART4_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART4_IO_PORT_OTHER_INPUT
+ hex "UART4 I/O port"
+ depends on UART4_ENABLE && UART4_IO_PORT_OTHER
+
+config UART4_IO
+ hex
+ depends on UART4_ENABLE
+ default 0x3f8 if UART4_IO_PORT_3F8
+ default 0x2f8 if UART4_IO_PORT_2F8
+ default 0x3e8 if UART4_IO_PORT_3E8
+ default 0x2e8 if UART4_IO_PORT_2E8
+ default UART4_IO_PORT_OTHER_INPUT if UART4_IO_PORT_OTHER
+
+choice
+ prompt "UART4 IRQ"
+ default UART4_IRQ11
+ depends on UART4_ENABLE
+
+config UART4_IRQ_DISABLE
+ bool "Disable"
+config UART4_IRQ3
+ bool "IRQ3, COM2"
+config UART4_IRQ4
+ bool "IRQ4, COM1"
+config UART4_IRQ5
+ bool "IRQ5"
+config UART4_IRQ6
+ bool "IRQ6"
+config UART4_IRQ7
+ bool "IRQ7"
+config UART4_IRQ9
+ bool "IRQ9"
+config UART4_IRQ10
+ bool "IRQ10, COM3"
+config UART4_IRQ11
+ bool "IRQ11, COM4"
+config UART4_IRQ12
+ bool "IRQ12"
+config UART4_IRQ14
+ bool "IRQ14"
+config UART4_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART4_IRQ
+ int
+ depends on UART4_ENABLE
+ default 0 if UART4_IRQ_DISABLE
+ default 3 if UART4_IRQ3
+ default 4 if UART4_IRQ4
+ default 5 if UART4_IRQ5
+ default 6 if UART4_IRQ6
+ default 7 if UART4_IRQ7
+ default 9 if UART4_IRQ9
+ default 10 if UART4_IRQ10
+ default 11 if UART4_IRQ11
+ default 12 if UART4_IRQ12
+ default 14 if UART4_IRQ14
+ default 15 if UART4_IRQ15
+
+choice
+ prompt "UART4 Baud rate"
+ default UART4_BAUD_115200
+ depends on UART4_ENABLE
+
+config UART4_BAUD_115200
+ bool "115200"
+config UART4_BAUD_57600
+ bool "57600"
+config UART4_BAUD_38400
+ bool "38400"
+config UART4_BAUD_19200
+ bool "19200"
+config UART4_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART4_BAUD
+ int
+ depends on UART4_ENABLE
+ default 115200 if UART4_BAUD_115200
+ default 57600 if UART4_BAUD_57600
+ default 38400 if UART4_BAUD_38400
+ default 19200 if UART4_BAUD_19200
+ default 9600 if UART4_BAUD_9600
+# end of UART4
+
+# Begin of UART5
+config UART5_ENABLE
+ bool "UART5 Enable"
+ default n
+
+choice
+ prompt "UART5 I/O port"
+ default UART5_IO_PORT_OTHER
+ depends on UART5_ENABLE
+
+config UART5_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART5_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART5_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART5_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART5_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART5_IO_PORT_OTHER_INPUT
+ hex "UART5 I/O port"
+ depends on UART5_ENABLE && UART5_IO_PORT_OTHER
+
+config UART5_IO
+ hex
+ depends on UART5_ENABLE
+ default 0x3f8 if UART5_IO_PORT_3F8
+ default 0x2f8 if UART5_IO_PORT_2F8
+ default 0x3e8 if UART5_IO_PORT_3E8
+ default 0x2e8 if UART5_IO_PORT_2E8
+ default UART5_IO_PORT_OTHER_INPUT if UART5_IO_PORT_OTHER
+
+choice
+ prompt "UART5 IRQ"
+ default UART5_IRQ_DISABLE
+ depends on UART5_ENABLE
+
+config UART5_IRQ_DISABLE
+ bool "Disable"
+config UART5_IRQ3
+ bool "IRQ3, COM2"
+config UART5_IRQ4
+ bool "IRQ4, COM1"
+config UART5_IRQ5
+ bool "IRQ5"
+config UART5_IRQ6
+ bool "IRQ6"
+config UART5_IRQ7
+ bool "IRQ7"
+config UART5_IRQ9
+ bool "IRQ9"
+config UART5_IRQ10
+ bool "IRQ10, COM3"
+config UART5_IRQ11
+ bool "IRQ11, COM4"
+config UART5_IRQ12
+ bool "IRQ12"
+config UART5_IRQ14
+ bool "IRQ14"
+config UART5_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART5_IRQ
+ int
+ depends on UART5_ENABLE
+ default 0 if UART5_IRQ_DISABLE
+ default 3 if UART5_IRQ3
+ default 4 if UART5_IRQ4
+ default 5 if UART5_IRQ5
+ default 6 if UART5_IRQ6
+ default 7 if UART5_IRQ7
+ default 9 if UART5_IRQ9
+ default 10 if UART5_IRQ10
+ default 11 if UART5_IRQ11
+ default 12 if UART5_IRQ12
+ default 14 if UART5_IRQ14
+ default 15 if UART5_IRQ15
+
+choice
+ prompt "UART5 Baud rate"
+ default UART5_BAUD_115200
+ depends on UART5_ENABLE
+
+config UART5_BAUD_115200
+ bool "115200"
+config UART5_BAUD_57600
+ bool "57600"
+config UART5_BAUD_38400
+ bool "38400"
+config UART5_BAUD_19200
+ bool "19200"
+config UART5_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART5_BAUD
+ int
+ depends on UART5_ENABLE
+ default 115200 if UART5_BAUD_115200
+ default 57600 if UART5_BAUD_57600
+ default 38400 if UART5_BAUD_38400
+ default 19200 if UART5_BAUD_19200
+ default 9600 if UART5_BAUD_9600
+# end of UART5
+
+# Begin of UART6
+config UART6_ENABLE
+ bool "UART6 Enable"
+ default n
+
+choice
+ prompt "UART6 I/O port"
+ default UART6_IO_PORT_OTHER
+ depends on UART6_ENABLE
+
+config UART6_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART6_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART6_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART6_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART6_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART6_IO_PORT_OTHER_INPUT
+ hex "UART6 I/O port"
+ depends on UART6_ENABLE && UART6_IO_PORT_OTHER
+
+config UART6_IO
+ hex
+ depends on UART6_ENABLE
+ default 0x3f8 if UART6_IO_PORT_3F8
+ default 0x2f8 if UART6_IO_PORT_2F8
+ default 0x3e8 if UART6_IO_PORT_3E8
+ default 0x2e8 if UART6_IO_PORT_2E8
+ default UART6_IO_PORT_OTHER_INPUT if UART6_IO_PORT_OTHER
+
+choice
+ prompt "UART6 IRQ"
+ default UART6_IRQ_DISABLE
+ depends on UART6_ENABLE
+
+config UART6_IRQ_DISABLE
+ bool "Disable"
+config UART6_IRQ3
+ bool "IRQ3, COM2"
+config UART6_IRQ4
+ bool "IRQ4, COM1"
+config UART6_IRQ5
+ bool "IRQ5"
+config UART6_IRQ6
+ bool "IRQ6"
+config UART6_IRQ7
+ bool "IRQ7"
+config UART6_IRQ9
+ bool "IRQ9"
+config UART6_IRQ10
+ bool "IRQ10, COM3"
+config UART6_IRQ11
+ bool "IRQ11, COM4"
+config UART6_IRQ12
+ bool "IRQ12"
+config UART6_IRQ14
+ bool "IRQ14"
+config UART6_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART6_IRQ
+ int
+ depends on UART6_ENABLE
+ default 0 if UART6_IRQ_DISABLE
+ default 3 if UART6_IRQ3
+ default 4 if UART6_IRQ4
+ default 5 if UART6_IRQ5
+ default 6 if UART6_IRQ6
+ default 7 if UART6_IRQ7
+ default 9 if UART6_IRQ9
+ default 10 if UART6_IRQ10
+ default 11 if UART6_IRQ11
+ default 12 if UART6_IRQ12
+ default 14 if UART6_IRQ14
+ default 15 if UART6_IRQ15
+
+choice
+ prompt "UART6 Baud rate"
+ default UART6_BAUD_115200
+ depends on UART6_ENABLE
+
+config UART6_BAUD_115200
+ bool "115200"
+config UART6_BAUD_57600
+ bool "57600"
+config UART6_BAUD_38400
+ bool "38400"
+config UART6_BAUD_19200
+ bool "19200"
+config UART6_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART6_BAUD
+ int
+ depends on UART6_ENABLE
+ default 115200 if UART6_BAUD_115200
+ default 57600 if UART6_BAUD_57600
+ default 38400 if UART6_BAUD_38400
+ default 19200 if UART6_BAUD_19200
+ default 9600 if UART6_BAUD_9600
+# end of UART6
+
+# Begin of UART7
+config UART7_ENABLE
+ bool "UART7 Enable"
+ default n
+
+choice
+ prompt "UART7 I/O port"
+ default UART7_IO_PORT_OTHER
+ depends on UART7_ENABLE
+
+config UART7_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART7_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART7_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART7_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART7_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART7_IO_PORT_OTHER_INPUT
+ hex "UART7 I/O port"
+ depends on UART7_ENABLE && UART7_IO_PORT_OTHER
+
+config UART7_IO
+ hex
+ depends on UART7_ENABLE
+ default 0x3f8 if UART7_IO_PORT_3F8
+ default 0x2f8 if UART7_IO_PORT_2F8
+ default 0x3e8 if UART7_IO_PORT_3E8
+ default 0x2e8 if UART7_IO_PORT_2E8
+ default UART7_IO_PORT_OTHER_INPUT if UART7_IO_PORT_OTHER
+
+choice
+ prompt "UART7 IRQ"
+ default UART7_IRQ_DISABLE
+ depends on UART7_ENABLE
+
+config UART7_IRQ_DISABLE
+ bool "Disable"
+config UART7_IRQ3
+ bool "IRQ3, COM2"
+config UART7_IRQ4
+ bool "IRQ4, COM1"
+config UART7_IRQ5
+ bool "IRQ5"
+config UART7_IRQ6
+ bool "IRQ6"
+config UART7_IRQ7
+ bool "IRQ7"
+config UART7_IRQ9
+ bool "IRQ9"
+config UART7_IRQ10
+ bool "IRQ10, COM3"
+config UART7_IRQ11
+ bool "IRQ11, COM4"
+config UART7_IRQ12
+ bool "IRQ12"
+config UART7_IRQ14
+ bool "IRQ14"
+config UART7_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART7_IRQ
+ int
+ depends on UART7_ENABLE
+ default 0 if UART7_IRQ_DISABLE
+ default 3 if UART7_IRQ3
+ default 4 if UART7_IRQ4
+ default 5 if UART7_IRQ5
+ default 6 if UART7_IRQ6
+ default 7 if UART7_IRQ7
+ default 9 if UART7_IRQ9
+ default 10 if UART7_IRQ10
+ default 11 if UART7_IRQ11
+ default 12 if UART7_IRQ12
+ default 14 if UART7_IRQ14
+ default 15 if UART7_IRQ15
+
+choice
+ prompt "UART7 Baud rate"
+ default UART7_BAUD_115200
+ depends on UART7_ENABLE
+
+config UART7_BAUD_115200
+ bool "115200"
+config UART7_BAUD_57600
+ bool "57600"
+config UART7_BAUD_38400
+ bool "38400"
+config UART7_BAUD_19200
+ bool "19200"
+config UART7_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART7_BAUD
+ int
+ depends on UART7_ENABLE
+ default 115200 if UART7_BAUD_115200
+ default 57600 if UART7_BAUD_57600
+ default 38400 if UART7_BAUD_38400
+ default 19200 if UART7_BAUD_19200
+ default 9600 if UART7_BAUD_9600
+# end of UART7
+
+# Begin of UART8
+config UART8_ENABLE
+ bool "UART8 Enable"
+ default n
+
+choice
+ prompt "UART8 I/O port"
+ default UART8_IO_PORT_OTHER
+ depends on UART8_ENABLE
+
+config UART8_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART8_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART8_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART8_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART8_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART8_IO_PORT_OTHER_INPUT
+ hex "UART8 I/O port"
+ depends on UART8_ENABLE && UART8_IO_PORT_OTHER
+
+config UART8_IO
+ hex
+ depends on UART8_ENABLE
+ default 0x3f8 if UART8_IO_PORT_3F8
+ default 0x2f8 if UART8_IO_PORT_2F8
+ default 0x3e8 if UART8_IO_PORT_3E8
+ default 0x2e8 if UART8_IO_PORT_2E8
+ default UART8_IO_PORT_OTHER_INPUT if UART8_IO_PORT_OTHER
+
+choice
+ prompt "UART8 IRQ"
+ default UART8_IRQ_DISABLE
+ depends on UART8_ENABLE
+
+config UART8_IRQ_DISABLE
+ bool "Disable"
+config UART8_IRQ3
+ bool "IRQ3, COM2"
+config UART8_IRQ4
+ bool "IRQ4, COM1"
+config UART8_IRQ5
+ bool "IRQ5"
+config UART8_IRQ6
+ bool "IRQ6"
+config UART8_IRQ7
+ bool "IRQ7"
+config UART8_IRQ9
+ bool "IRQ9"
+config UART8_IRQ10
+ bool "IRQ10, COM3"
+config UART8_IRQ11
+ bool "IRQ11, COM4"
+config UART8_IRQ12
+ bool "IRQ12"
+config UART8_IRQ14
+ bool "IRQ14"
+config UART8_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART8_IRQ
+ int
+ depends on UART8_ENABLE
+ default 0 if UART8_IRQ_DISABLE
+ default 3 if UART8_IRQ3
+ default 4 if UART8_IRQ4
+ default 5 if UART8_IRQ5
+ default 6 if UART8_IRQ6
+ default 7 if UART8_IRQ7
+ default 9 if UART8_IRQ9
+ default 10 if UART8_IRQ10
+ default 11 if UART8_IRQ11
+ default 12 if UART8_IRQ12
+ default 14 if UART8_IRQ14
+ default 15 if UART8_IRQ15
+
+choice
+ prompt "UART8 Baud rate"
+ default UART8_BAUD_115200
+ depends on UART8_ENABLE
+
+config UART8_BAUD_115200
+ bool "115200"
+config UART8_BAUD_57600
+ bool "57600"
+config UART8_BAUD_38400
+ bool "38400"
+config UART8_BAUD_19200
+ bool "19200"
+config UART8_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART8_BAUD
+ int
+ depends on UART8_ENABLE
+ default 115200 if UART8_BAUD_115200
+ default 57600 if UART8_BAUD_57600
+ default 38400 if UART8_BAUD_38400
+ default 19200 if UART8_BAUD_19200
+ default 9600 if UART8_BAUD_9600
+# end of UART8
+
+# Begin of UART9
+config UART9_ENABLE
+ bool "UART9 Enable"
+ default n
+
+choice
+ prompt "UART9 I/O port"
+ default UART9_IO_PORT_OTHER
+ depends on UART9_ENABLE
+
+config UART9_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART9_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART9_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART9_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART9_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART9_IO_PORT_OTHER_INPUT
+ hex "UART9 I/O port"
+ depends on UART9_ENABLE && UART9_IO_PORT_OTHER
+
+config UART9_IO
+ hex
+ depends on UART9_ENABLE
+ default 0x3f8 if UART9_IO_PORT_3F8
+ default 0x2f8 if UART9_IO_PORT_2F8
+ default 0x3e8 if UART9_IO_PORT_3E8
+ default 0x2e8 if UART9_IO_PORT_2E8
+ default UART9_IO_PORT_OTHER_INPUT if UART9_IO_PORT_OTHER
+
+choice
+ prompt "UART9 IRQ"
+ default UART9_IRQ_DISABLE
+ depends on UART9_ENABLE
+
+config UART9_IRQ_DISABLE
+ bool "Disable"
+config UART9_IRQ3
+ bool "IRQ3, COM2"
+config UART9_IRQ4
+ bool "IRQ4, COM1"
+config UART9_IRQ5
+ bool "IRQ5"
+config UART9_IRQ6
+ bool "IRQ6"
+config UART9_IRQ7
+ bool "IRQ7"
+config UART9_IRQ9
+ bool "IRQ9"
+config UART9_IRQ10
+ bool "IRQ10, COM3"
+config UART9_IRQ11
+ bool "IRQ11, COM4"
+config UART9_IRQ12
+ bool "IRQ12"
+config UART9_IRQ14
+ bool "IRQ14"
+config UART9_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART9_IRQ
+ int
+ depends on UART9_ENABLE
+ default 0 if UART9_IRQ_DISABLE
+ default 3 if UART9_IRQ3
+ default 4 if UART9_IRQ4
+ default 5 if UART9_IRQ5
+ default 6 if UART9_IRQ6
+ default 7 if UART9_IRQ7
+ default 9 if UART9_IRQ9
+ default 10 if UART9_IRQ10
+ default 11 if UART9_IRQ11
+ default 12 if UART9_IRQ12
+ default 14 if UART9_IRQ14
+ default 15 if UART9_IRQ15
+
+choice
+ prompt "UART9 Baud rate"
+ default UART9_BAUD_115200
+ depends on UART9_ENABLE
+
+config UART9_BAUD_115200
+ bool "115200"
+config UART9_BAUD_57600
+ bool "57600"
+config UART9_BAUD_38400
+ bool "38400"
+config UART9_BAUD_19200
+ bool "19200"
+config UART9_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART9_BAUD
+ int
+ depends on UART9_ENABLE
+ default 115200 if UART9_BAUD_115200
+ default 57600 if UART9_BAUD_57600
+ default 38400 if UART9_BAUD_38400
+ default 19200 if UART9_BAUD_19200
+ default 9600 if UART9_BAUD_9600
+# end of UART9
+
+# Begin of UART10
+config UART10_ENABLE
+ bool "UART10 Enable"
+ default n
+
+choice
+ prompt "UART10 I/O port"
+ default UART10_IO_PORT_OTHER
+ depends on UART10_ENABLE
+
+config UART10_IO_PORT_3F8
+ bool "0x3f8, COM1"
+config UART10_IO_PORT_2F8
+ bool "0x2f8, COM2"
+config UART10_IO_PORT_3E8
+ bool "0x3e8, COM3"
+config UART10_IO_PORT_2E8
+ bool "0x2e8, COM4"
+config UART10_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config UART10_IO_PORT_OTHER_INPUT
+ hex "UART10 I/O port"
+ depends on UART10_ENABLE && UART10_IO_PORT_OTHER
+
+config UART10_IO
+ hex
+ depends on UART10_ENABLE
+ default 0x3f8 if UART10_IO_PORT_3F8
+ default 0x2f8 if UART10_IO_PORT_2F8
+ default 0x3e8 if UART10_IO_PORT_3E8
+ default 0x2e8 if UART10_IO_PORT_2E8
+ default UART10_IO_PORT_OTHER_INPUT if UART10_IO_PORT_OTHER
+
+choice
+ prompt "UART10 IRQ"
+ default UART10_IRQ_DISABLE
+ depends on UART10_ENABLE
+
+config UART10_IRQ_DISABLE
+ bool "Disable"
+config UART10_IRQ3
+ bool "IRQ3, COM2"
+config UART10_IRQ4
+ bool "IRQ4, COM1"
+config UART10_IRQ5
+ bool "IRQ5"
+config UART10_IRQ6
+ bool "IRQ6"
+config UART10_IRQ7
+ bool "IRQ7"
+config UART10_IRQ9
+ bool "IRQ9"
+config UART10_IRQ10
+ bool "IRQ10, COM3"
+config UART10_IRQ11
+ bool "IRQ11, COM4"
+config UART10_IRQ12
+ bool "IRQ12"
+config UART10_IRQ14
+ bool "IRQ14"
+config UART10_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config UART10_IRQ
+ int
+ depends on UART10_ENABLE
+ default 0 if UART10_IRQ_DISABLE
+ default 3 if UART10_IRQ3
+ default 4 if UART10_IRQ4
+ default 5 if UART10_IRQ5
+ default 6 if UART10_IRQ6
+ default 7 if UART10_IRQ7
+ default 9 if UART10_IRQ9
+ default 10 if UART10_IRQ10
+ default 11 if UART10_IRQ11
+ default 12 if UART10_IRQ12
+ default 14 if UART10_IRQ14
+ default 15 if UART10_IRQ15
+
+choice
+ prompt "UART10 Baud rate"
+ default UART10_BAUD_115200
+ depends on UART10_ENABLE
+
+config UART10_BAUD_115200
+ bool "115200"
+config UART10_BAUD_57600
+ bool "57600"
+config UART10_BAUD_38400
+ bool "38400"
+config UART10_BAUD_19200
+ bool "19200"
+config UART10_BAUD_9600
+ bool "9600"
+
+endchoice
+
+config UART10_BAUD
+ int
+ depends on UART10_ENABLE
+ default 115200 if UART10_BAUD_115200
+ default 57600 if UART10_BAUD_57600
+ default 38400 if UART10_BAUD_38400
+ default 19200 if UART10_BAUD_19200
+ default 9600 if UART10_BAUD_9600
+# end of UART10
+
+endmenu
+
+# LPT setting :
+menu "LPT setting"
+
+# Begin of LPT
+config LPT_ENABLE
+ bool "LPT Enable"
+ default n
+
+choice
+ prompt "LPT I/O port"
+ default LPT_IO_PORT_278
+ depends on LPT_ENABLE
+
+config LPT_IO_PORT_378
+ bool "0x378, LPT1"
+config LPT_IO_PORT_278
+ bool "0x278, LPT2"
+config LPT_IO_PORT_OTHER
+ bool "Other"
+
+endchoice
+
+config LPT_IO_PORT_OTHER_INPUT
+ hex "LPT I/O port"
+ depends on LPT_ENABLE && LPT_IO_PORT_OTHER
+
+config LPT_IO
+ hex
+ depends on LPT_ENABLE
+ default 0x378 if LPT_IO_PORT_378
+ default 0x278 if LPT_IO_PORT_278
+ default LPT_IO_PORT_OTHER_INPUT if LPT_IO_PORT_OTHER
+
+choice
+ prompt "LPT IRQ"
+ default LPT_IRQ_DISABLE
+ depends on LPT_ENABLE
+
+config LPT_IRQ_DISABLE
+ bool "Disable"
+config LPT_IRQ3
+ bool "IRQ3"
+config LPT_IRQ4
+ bool "IRQ4"
+config LPT_IRQ5
+ bool "IRQ5"
+config LPT_IRQ6
+ bool "IRQ6"
+config LPT_IRQ7
+ bool "IRQ7"
+config LPT_IRQ9
+ bool "IRQ9"
+config LPT_IRQ10
+ bool "IRQ10"
+config LPT_IRQ11
+ bool "IRQ11"
+config LPT_IRQ12
+ bool "IRQ12"
+config LPT_IRQ14
+ bool "IRQ14"
+config LPT_IRQ15
+ bool "IRQ15"
+
+endchoice
+
+config LPT_IRQ
+ int
+ depends on LPT_ENABLE
+ default 0 if LPT_IRQ_DISABLE
+ default 3 if LPT_IRQ3
+ default 4 if LPT_IRQ4
+ default 5 if LPT_IRQ5
+ default 6 if LPT_IRQ6
+ default 7 if LPT_IRQ7
+ default 9 if LPT_IRQ9
+ default 10 if LPT_IRQ10
+ default 11 if LPT_IRQ11
+ default 12 if LPT_IRQ12
+ default 14 if LPT_IRQ14
+ default 15 if LPT_IRQ15
+
+choice
+ prompt "LPT Mode Setting"
+ default LPT_MODE_SPP
+ depends on LPT_ENABLE
+
+config LPT_MODE_BPP
+ bool "BPP mode"
+config LPT_MODE_EPP_19_AND_SPP
+ bool "EPP 1.9 and SPP mode"
+config LPT_MODE_ECP
+ bool "ECP Mode"
+config LPT_MODE_ECP_AND_EPP_19
+ bool "ECP and EPP 1.9 mode"
+config LPT_MODE_SPP
+ bool "SPP Mode"
+config LPT_MODE_EPP_17_AND_SPP
+ bool "EPP 1.7 and SPP mode"
+config LPT_MODE_ECP_AND_EPP_17
+ bool "ECP and EPP 1.7 mode"
+
+endchoice
+
+# end of LPT
+
+endmenu
+
+endif # BOARD_DMP_EX
diff --git a/src/mainboard/dmp/vortex86ex/chip.h b/src/mainboard/dmp/vortex86ex/chip.h
new file mode 100644
index 0000000..446e596
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+};
diff --git a/src/mainboard/dmp/vortex86ex/devicetree.cb b/src/mainboard/dmp/vortex86ex/devicetree.cb
new file mode 100644
index 0000000..1fbfe7b
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/devicetree.cb
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip northbridge/dmp/vortex86ex # North Bridge
+ device domain 0 on
+ device pci 0.0 on end # Host Bridge
+ chip southbridge/dmp/vortex86ex # South Bridge
+ device pci 7.0 on end # ISA Bridge
+ device pci 8.0 on end # Ethernet
+ device pci a.0 on end # USB 1.1
+ device pci a.1 on end # USB 2.0
+ device pci b.0 on end # USB 1.1
+ device pci b.1 on end # USB 2.0
+ device pci c.0 on end # IDE
+ end
+ end # pci domain 0
+ chip cpu/dmp/vortex86ex end # CPU
+end
diff --git a/src/mainboard/dmp/vortex86ex/irq_tables.c b/src/mainboard/dmp/vortex86ex/irq_tables.c
new file mode 100644
index 0000000..c185c4f
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/irq_tables.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 12, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x07 << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x17f3, /* Vendor */
+ 0x6031, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xa, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0},
+ {0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0},
+ {0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0},
+ {0x00, (0x04 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x4, 0x0},
+ {0x00, (0x05 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x5, 0x0},
+ {0x00, (0x06 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x6, 0x0},
+ {0x00, (0x08 << 3) | 0x0, {{0x05, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0a << 3) | 0x0, {{0x07, 0xdef8}, {0x08, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0b << 3) | 0x0, {{0x09, 0xdef8}, {0x0a, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0c << 3) | 0x0, {{0x0b, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0f << 3) | 0x0, {{0x0d, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x0e << 3) | 0x0, {{0x0e, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c
new file mode 100644
index 0000000..934c898
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/mainboard.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <device/pci_def.h>
+#include "chip.h"
+
+static void mb_enable(device_t dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("DMP VORTEX86EX Mainboard")
+ .enable_dev = mb_enable,
+};
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
new file mode 100644
index 0000000..8f02305
--- /dev/null
+++ b/src/mainboard/dmp/vortex86ex/romstage.c
@@ -0,0 +1,428 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Andrew Wu <arw at dmp.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "drivers/pc80/i8254.c"
+#include "northbridge/dmp/vortex86ex/northbridge.h"
+#include "southbridge/dmp/vortex86ex/southbridge.h"
+#include "northbridge/dmp/vortex86ex/raminit.c"
+
+#define DMP_CPUID_SX 0x31504d44
+#define DMP_CPUID_DX 0x32504d44
+#define DMP_CPUID_MX 0x33504d44
+#define DMP_CPUID_DX2 0x34504d44
+#define DMP_CPUID_MX_PLUS 0x35504d44
+#define DMP_CPUID_EX 0x37504d44
+
+static u32 get_dmp_id(void)
+{
+ return pci_read_config32(NB, NB_REG_CID);
+}
+
+static void check_dmp_cpu(u32 dmp_id)
+{
+ if (dmp_id & 0x00ffffff != 0x00504d44) {
+ while (1)
+ post_code(0x81);
+ }
+}
+
+static void check_memtype_ddr2(void)
+{
+ /* Check STRAP register for MEMSEL, we only support DDRII. */
+ u32 strap;
+ strap = pci_read_config32(NB, NB_REG_STRAP);
+ if (((strap >> 12) & 0x3) != 0x3) {
+ while (1)
+ post_code(0x83);
+ }
+}
+
+/* Indirect access registers for Watch-dog timer, GPIO PORT 0,1
+ * Index port is for I/O port 22h
+ * Index port 13h (00: lock register, C5h: unlock register) for lock/unlock function
+ * Index port 37h, 39h, 3Ah, 3Bh, 3Ch for Watchdog timer
+ * Index port 46h, 47h, 4Ch, 4Dh, 4Eh, 4Fh for GPIO port 0, 1
+ */
+static void write_indirect_reg(u8 index, u8 data)
+{
+ outb(index, 0x22);
+ outb(data, 0x23);
+}
+
+static void lock_indirect_reg(void)
+{
+ write_indirect_reg(0x13, 0x00);
+}
+
+static void unlock_indirect_reg(void)
+{
+ write_indirect_reg(0x13, 0xc5);
+}
+
+static void disable_watchdog(void)
+{
+ unlock_indirect_reg();
+ // disable watchdog timer
+ write_indirect_reg(0x37, 0x0);
+}
+
+void set_ex_powerdown_control(void)
+{
+ u32 powerdown_ctrl;
+ powerdown_ctrl = pci_read_config32(SB, 0xbc);
+#if CONFIG_TEMP_POWERDOWN
+ powerdown_ctrl |= (1 << 31);
+#endif
+#if CONFIG_SATA_POWERDOWN
+ powerdown_ctrl |= (1 << 30);
+#endif
+#if CONFIG_ADC_POWERDOWN
+ powerdown_ctrl |= (1 << 28);
+#endif
+#if CONFIG_PCIE0_POWERDOWN
+ powerdown_ctrl |= (1 << 13);
+#endif
+#if CONFIG_MAC_POWERDOWN
+ powerdown_ctrl |= (1 << 3);
+#endif
+#if CONFIG_USB1_POWERDOWN
+ powerdown_ctrl |= (1 << 1);
+#endif
+#if CONFIG_IDE_POWERDOWN
+ powerdown_ctrl |= (1 << 0);
+#endif
+ pci_write_config32(SB, 0xbc, powerdown_ctrl);
+}
+
+static u32 make_uart_config(u16 base, u8 irq)
+{
+ /* Set base IO address only, skip IRQ. IRQ will be setup in
+ * southbridge stage. */
+ u32 cfg = 0;
+ cfg |= 1 << 23; // UE = enabled.
+ cfg |= base; // UIOA.
+ return cfg;
+}
+
+#define SETUP_UART(n) \
+ uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\
+ outl(uart_cfg, 0xc00 + (n - 1) * 4);
+
+static void ex_uart_early_init(void)
+{
+#if CONFIG_TTYS0_BASE
+ u32 uart_cfg = 0;
+ /* Set UART Config I/O base address to 0xc00 */
+ pci_write_config16(SB, 0x60, 0xc01);
+ /* If serial console base address is defined, find out which
+ * UART uses this address, and setup this UART first. */
+#if CONFIG_TTYS0_BASE == CONFIG_UART1_IO
+ SETUP_UART(1)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART2_IO
+ SETUP_UART(2)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART3_IO
+ SETUP_UART(3)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART4_IO
+ SETUP_UART(4)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART5_IO
+ SETUP_UART(5)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART6_IO
+ SETUP_UART(6)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART7_IO
+ SETUP_UART(7)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART8_IO
+ SETUP_UART(8)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART9_IO
+ SETUP_UART(9)
+#elif CONFIG_TTYS0_BASE == CONFIG_UART10_IO
+ SETUP_UART(10)
+#endif
+ /* Keep UART Config I/O base address */
+ //pci_write_config16(SB, 0x60, 0x0);
+#endif
+}
+
+static void init_wdt1(void)
+{
+#if CONFIG_WDT1_INITIALIZE
+#if CONFIG_WDT1_ENABLE
+ outb(0x1 << 6, 0xa8);
+#endif
+ u8 wdt1_signal_reg = 0;
+#if CONFIG_WDT1_SINGAL_NMI
+ wdt1_signal_reg = 0x0c << 4;
+#elif CONFIG_WDT1_SIGNAL_RESET
+ wdt1_signal_reg = 0x0d << 4;
+#elif CONFIG_WDT1_SIGNAL_SMI
+ wdt1_signal_reg = 0x0e << 4;
+#endif
+ outb(wdt1_signal_reg, 0xa9);
+#endif
+}
+
+/* Fill 32bit pattern into specified DRAM region. */
+static void fill_dram(u32 * p, u32 pattern, u32 test_len)
+{
+ if (test_len == 0)
+ return;
+#if 0
+ // C version, very slow.
+ for (p = (u32 *) 0; (u32) p < test_len; p++) {
+ *p = pattern;
+ }
+#endif
+ // ASM version, much faster.
+ asm volatile (
+ "cld\n\t"
+ "rep\n\t"
+ "stosl"
+ : /* no output registers */
+ : "c" (test_len / 4), "a" (pattern), "D" (p)
+ );
+}
+
+/* Verify 32bit pattern in specified DRAM region.
+ * Return -1 if ok, failed memory address if error. */
+static int verify_dram(u32 * p, u32 pattern, u32 test_len)
+{
+ if (test_len == 0)
+ return -1;
+#if 0
+ // C version, very slow.
+ for (p = (u32 *) 0; (u32) p < test_len; p++) {
+ if (*p != pattern) {
+ return (int)p;
+ }
+ }
+ return -1;
+#endif
+ u16 flags;
+ int addr;
+ asm volatile (
+ "cld\n\t"
+ "rep\n\t"
+ "scasl\n\t"
+ "lahf\n\t"
+ : "=a" (flags), "=D" (addr)
+ : "c" (test_len / 4), "a" (pattern), "D" (p)
+ );
+ if (flags & (1 << (6 + 8))) // x86 zero flag = bit 6.
+ {
+ return -1; // verify ok
+ }
+ return addr - 4; // verify error, return error address.
+}
+
+static void test_dram_stability(void)
+{
+ u32 test_len = 2048 * 1024;
+ u32 pat = 0x5aa5a55a;
+ u32 ext_mem_start = 0xc0000;
+ u32 base_mem_test_len = test_len > 640 * 1024 ? 640 * 1024 : test_len;
+ u32 ext_mem_test_len = test_len > ext_mem_start ? test_len - ext_mem_start : 0;
+ if (ext_mem_test_len > 0) {
+ /* Enable all shadow RAM region C0000 - FFFFF. */
+ pci_write_config32(NB, NB_REG_MAR, 0x3ffffff0);
+ }
+ int v;
+ fill_dram((u32 *) 0, pat, base_mem_test_len);
+ fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ v = verify_dram((u32 *) 0, pat, base_mem_test_len);
+ if (v == -1) {
+ v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ }
+ /* Change pattern and test again */
+ if (v == -1) {
+ pat = 0xa55a5aa5;
+ fill_dram((u32 *) 0, pat, base_mem_test_len);
+ fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ v = verify_dram((u32 *) 0, pat, base_mem_test_len);
+ if (v == -1) {
+ v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
+ }
+ }
+ if (v != -1) {
+ post_code(0x86);
+ print_emerg("DRAM stablility test error!\nADDR = ");
+ print_emerg_hex32(v);
+ print_emerg(", WRITE = ");
+ print_emerg_hex32(pat);
+ u32 r = *(u32 *) v;
+ print_emerg(", READ = ");
+ print_emerg_hex32(r);
+ print_emerg(", XOR = ");
+ print_emerg_hex32(r ^ pat);
+ print_emerg("\n");
+ die("System halted.\n");
+ }
+ if (ext_mem_test_len > 0) {
+ /* Disable shadow RAM. */
+ pci_write_config32(NB, NB_REG_MAR, 0x0);
+ }
+}
+
+static void enable_l2_cache(void)
+{
+ /*
+ * Enable L2 cache by setting PCI N/B function 1 L2 cache
+ * control register (0xe8) bit 0 (L2_EN) and bit 1 (L2_WB_EN).
+ */
+ u32 reg_nb_f1_e8;
+ reg_nb_f1_e8 = pci_read_config8(NB1, 0xe8);
+ reg_nb_f1_e8 |= 3;
+ pci_write_config8(NB1, 0xe8, reg_nb_f1_e8);
+}
+
+static void print_ddr3_memory_setup(void)
+{
+#if CONFIG_DEBUG_RAM_SETUP
+ print_debug("DDR3 Timing Reg 0-3:\n");
+ print_debug("NB 6e : ");
+ print_debug_hex16(pci_read_config16(NB, 0x6e));
+ print_debug("\nNB 74 : ");
+ print_debug_hex32(pci_read_config32(NB, 0x74));
+ print_debug("\nNB 78 : ");
+ print_debug_hex32(pci_read_config32(NB, 0x78));
+ print_debug("\nNB 7c : ");
+ print_debug_hex32(pci_read_config32(NB, 0x7c));
+ u16 mbr = pci_read_config16(NB, 0x6c);
+ print_debug("\nNB 6c(MBR) : ");
+ print_debug_hex16(mbr);
+ const char *s;
+ u8 col = (mbr & 7);
+ if (col == 0)
+ s = " (COL=10";
+ else
+ s = " (COL=11";
+ print_debug(s);
+ u8 row = (mbr >> 5) & 7;
+ switch (row) {
+ case 0:
+ s = ", ROW = 13";
+ break;
+ case 1:
+ s = ", ROW = 14";
+ break;
+ case 2:
+ s = ", ROW = 15";
+ break;
+ default:
+ s = ", ROW = 16";
+ break;
+ }
+ print_debug(s);
+ u8 size = (mbr >> 8) & 0xf;
+ switch (size) {
+ case 5:
+ s = ", 64M";
+ break;
+ case 6:
+ s = ", 128M";
+ break;
+ case 7:
+ s = ", 256M";
+ break;
+ case 8:
+ s = ", 512M";
+ break;
+ case 9:
+ s = ", 1GB";
+ break;
+ case 10:
+ s = ", 2GB";
+ break;
+ }
+ print_debug(s);
+ u8 mask = (mbr >> 13) & 1;
+ if (mask == 0)
+ s = ", CS MASK Enable)\n";
+ else
+ s = ", CS Mask Disable)\n";
+ print_debug(s);
+#endif
+}
+
+static void main(unsigned long bist)
+{
+ device_t dev;
+ u32 dmp_id;
+
+ dmp_id = get_dmp_id();
+ check_dmp_cpu(dmp_id);
+ disable_watchdog();
+ if (dmp_id == DMP_CPUID_EX) {
+ set_ex_powerdown_control();
+ ex_uart_early_init();
+ }
+
+ console_init();
+
+ if (dmp_id == DMP_CPUID_EX) {
+ init_wdt1();
+ }
+
+ /* Initialize i8254 timers */
+ post_code(0x42);
+ setup_i8254();
+
+ /* Initialize DRAM */
+ switch (dmp_id) {
+ case DMP_CPUID_DX:
+ check_memtype_ddr2();
+ config_pci_northbridge_f1();
+ config_pci_northbridge_f0();
+ detect_dram_size();
+ break;
+ case DMP_CPUID_EX:
+ u8 reg_nb_f1_cc;
+ /* Setup DDR3 Timing reg 0-3 / Config reg */
+ pci_write_config16(NB, 0x6e, 0x0a2f);
+ pci_write_config32(NB, 0x74, 0x84010200);
+ pci_write_config32(NB, 0x78, 0x33405544);
+ pci_write_config32(NB, 0x7c, 0x2e0f0e0b);
+ /* Disable enhance read push write */
+ reg_nb_f1_cc = pci_read_config8(NB1, 0xcc);
+ reg_nb_f1_cc &= ~(1 << 4);
+ pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
+ detect_ddr3_dram_size();
+ /* Reset enhance read push write to default(enable) */
+ reg_nb_f1_cc |= (1 << 4);
+ pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
+
+ print_ddr3_memory_setup();
+ break;
+ default:
+ /* Other CPU type is not supported yet. */
+ post_code(0x85);
+ die("Unknown CPU model.\n");
+ }
+ test_dram_stability();
+
+ /* CPU setup, romcc pukes on invd() */
+ asm volatile ("invd");
+ enable_cache();
+
+ enable_l2_cache();
+}
diff --git a/src/northbridge/Kconfig b/src/northbridge/Kconfig
index b2b8abe..0ac09a6 100644
--- a/src/northbridge/Kconfig
+++ b/src/northbridge/Kconfig
@@ -1,4 +1,5 @@
source src/northbridge/amd/Kconfig
+source src/northbridge/dmp/Kconfig
source src/northbridge/intel/Kconfig
source src/northbridge/rdc/Kconfig
source src/northbridge/via/Kconfig
diff --git a/src/northbridge/Makefile.inc b/src/northbridge/Makefile.inc
index 283ba4e..1a5b1c8 100644
--- a/src/northbridge/Makefile.inc
+++ b/src/northbridge/Makefile.inc
@@ -1,4 +1,5 @@
subdirs-y += amd
+subdirs-y += dmp
subdirs-y += intel
subdirs-y += rdc
subdirs-y += via
diff --git a/src/northbridge/dmp/Kconfig b/src/northbridge/dmp/Kconfig
new file mode 100644
index 0000000..a69d1d9
--- /dev/null
+++ b/src/northbridge/dmp/Kconfig
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+source src/northbridge/dmp/vortex86ex/Kconfig
diff --git a/src/northbridge/dmp/Makefile.inc b/src/northbridge/dmp/Makefile.inc
new file mode 100644
index 0000000..3cfcc48
--- /dev/null
+++ b/src/northbridge/dmp/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-$(CONFIG_NORTHBRIDGE_DMP_VORTEX86EX) += vortex86ex
diff --git a/src/northbridge/dmp/vortex86ex/Kconfig b/src/northbridge/dmp/vortex86ex/Kconfig
new file mode 100644
index 0000000..a304606
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/Kconfig
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config NORTHBRIDGE_DMP_VORTEX86EX
+ bool
+
+
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "northbridge/dmp/vortex86ex/bootblock.c"
+ depends on NORTHBRIDGE_DMP_VORTEX86EX
diff --git a/src/northbridge/dmp/vortex86ex/Makefile.inc b/src/northbridge/dmp/vortex86ex/Makefile.inc
new file mode 100644
index 0000000..82b07fd
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += northbridge.c
+ramstage-y += xgi_oprom.c
diff --git a/src/northbridge/dmp/vortex86ex/bootblock.c b/src/northbridge/dmp/vortex86ex/bootblock.c
new file mode 100644
index 0000000..a90d4b9
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/bootblock.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "northbridge.h"
+
+/************************************************************************/
+/* north bridge configuration space access routines */
+/************************************************************************/
+
+uint8_t pci_read_nb_config8(unsigned where)
+{
+ return (pci_io_read_config8(NB, where));
+}
+
+void pci_write_nb_config8(unsigned where, uint8_t value)
+{
+ pci_io_write_config8(NB, where, value);
+}
+
+uint16_t pci_read_nb_config16(unsigned where)
+{
+ return (pci_io_read_config16(NB, where));
+}
+
+void pci_write_nb_config16(unsigned where, uint16_t value)
+{
+ pci_io_write_config16(NB, where, value);
+}
+
+uint32_t pci_read_nb_config32(unsigned where)
+{
+ return (pci_io_read_config32(NB, where));
+}
+
+void pci_write_nb_config32(unsigned where, uint32_t value)
+{
+ pci_io_write_config32(NB, where, value);
+}
+
+void pci_write_nb1_config32(unsigned where, uint32_t value)
+{
+ pci_io_write_config32(NB1, where, value);
+}
+
+/************************************************************************/
+/* bootblock north bridge initialize */
+/************************************************************************/
+
+void bootblock_northbridge_init(void)
+{
+ pci_write_nb_config8(NB_REG_PMCR, (pci_read_nb_config8(NB_REG_PMCR)&~0xf0) | 0x05);
+ pci_write_nb_config8(NB_REG_MBR, (pci_read_nb_config8(NB_REG_MBR)&0xfc));
+ pci_write_nb_config8(NB_REG_SMM, 0);
+ pci_write_nb_config8(NB_REG_SDRAM_MCR, (pci_read_nb_config8(NB_REG_SDRAM_MCR)&~0xf9) | 0x06);
+ pci_write_nb_config8(NB_REG_MRR, 0);
+ pci_write_nb_config8(NB_REG_CPU_DCR+1, (pci_read_nb_config8(NB_REG_CPU_DCR+1)&~0xfb) | 0x04);
+ pci_write_nb_config8(NB_REG_PACR, (pci_read_nb_config8(NB_REG_PACR)&~0xfc) | 0x01);
+ pci_write_nb_config32(NB_REG_BUF_SC, 0x83e7cf9f);
+}
diff --git a/src/northbridge/dmp/vortex86ex/chip.h b/src/northbridge/dmp/vortex86ex/chip.h
new file mode 100644
index 0000000..93384c4
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/chip.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _NORTHBRIDGE_DMP_VORTEX86EX
+#define _NORTHBRIDGE_DMP_VORTEX86EX
+
+struct northbridge_dmp_vortex86ex_config {
+};
+
+#endif /* _NORTHBRIDGE_DMP_VORTEX86EX */
diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c
new file mode 100644
index 0000000..1218591
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/northbridge.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cbmem.h>
+#include <pc80/mc146818rtc.h>
+#include "chip.h"
+#include "northbridge.h"
+
+#define SPI_BASE 0xfc00
+
+static void northbridge_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n");
+ // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable.
+ pci_write_config32(dev, NB_REG_MAR, 0x3ff000f0);
+ // enable C0000h - C3FFFh/C4000h - C7FFF can be in L1 cache selection.
+ pci_write_config32(dev, NB_REG_HOST_CTL, (1 << 18)|(1<<19));
+ // Set SPI register base.
+ pci_write_config16(dev, NB_REG_SPI_BASE,SPI_BASE|1);
+}
+
+static struct device_operations northbridge_operations = {
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init
+};
+
+static const struct pci_driver northbridge_driver_6021 __pci_driver = {
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device =0x6021, /* DX CPU N/B ID */
+};
+
+static const struct pci_driver northbridge_driver_6025 __pci_driver = {
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device =0x6025, /* EX CPU N/B ID */
+};
+
+/* Set CMOS register 15h/16h/17h/18h for base/extended
+ * memory size. */
+static void set_cmos_memory_size(unsigned long sizek)
+{
+ unsigned long ext_mem_size;
+ u8 ext_mem_size_hb, ext_mem_size_lb;
+ /* calculate memory size between 1M - 65M. */
+ ext_mem_size = sizek - 1024;
+ if(ext_mem_size > 65535)
+ ext_mem_size = 65535;
+ ext_mem_size_hb = (u8)(ext_mem_size >> 8);
+ ext_mem_size_lb = (u8)(ext_mem_size & 0xff);
+ /* Base memory is always 640K. */
+ cmos_write(0x80, 0x15);
+ cmos_write(0x02, 0x16);
+ /* Write extended memory size. */
+ cmos_write(ext_mem_size_lb, 0x17);
+ cmos_write(ext_mem_size_hb, 0x18);
+ /* register 0x30(48) is RTC_BOOT_BYTE for CoreBoot,
+ * don't touch it. */
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+ device_t mc_dev;
+ uint32_t pci_tolm;
+
+ printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n");
+
+ pci_tolm = find_pci_tolm(dev->link_list);
+ mc_dev = dev->link_list->children;
+ if (mc_dev) {
+ unsigned long tomk, tolmk;
+ int idx;
+ int ss;
+ /* Get DDRII size setting from northbridge register. */
+ /* SS = 0 for 2MB, 1 for 4MB, 2 for 8MB, 3 for 16MB ... */
+ ss = pci_read_config16(mc_dev, 0x6c);
+ ss = ((ss >> 8) & 0xf);
+ tomk = (2 * 1024) << ss;
+ printk(BIOS_DEBUG, "I would set ram size to %ld Mbytes\n", (tomk >> 10));
+ /* Compute the top of Low memory */
+ tolmk = pci_tolm >> 10;
+ if (tolmk >= tomk) {
+ /* The PCI hole does does not overlap the memory.
+ */
+ tolmk = tomk;
+ }
+
+ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
+ high_tables_size = HIGH_MEMORY_SIZE;
+ printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
+ tomk*1024, high_tables_base, high_tables_size);
+
+ /* Report the memory regions */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 640); /* first 640k */
+ ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */
+ set_cmos_memory_size(tolmk);
+ }
+ assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+};
+
+static void enable_dev(struct device *dev)
+{
+ printk(BIOS_SPEW, "In vortex86ex enable_dev for device %s.\n", dev_path(dev));
+
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ pci_set_method(dev);
+ }
+}
+
+struct chip_operations northbridge_dmp_vortex86ex_ops = {
+ CHIP_NAME("DMP Vortex86EX Northbridge")
+ .enable_dev = enable_dev,
+};
diff --git a/src/northbridge/dmp/vortex86ex/northbridge.h b/src/northbridge/dmp/vortex86ex/northbridge.h
new file mode 100644
index 0000000..efd5274
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/northbridge.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_DMP_VORTEX86EX_H
+#define NORTHBRIDGE_DMP_VORTEX86EX_H
+
+#define NB PCI_DEV(0, 0, 0)
+#define NB_REG_VID 0x00
+#define NB_REG_DID 0x02
+#define NB_REG_CMD 0x04
+#define NB_REG_STS 0x06
+#define NB_REG_RID 0x08
+#define NB_REG_CLS_CODE 0x09
+#define NB_REG_HAD_TYPE 0x0E
+#define NB_REG_SUB_VID 0x2C
+#define NB_REG_SUB_DID 0x2E
+#define NB_REG_SPI_BASE 0x40
+#define NB_REG_BUF_SC 0x44
+#define NB_REG_NBOCDCR 0x4A
+#define NB_REG_GPUUMACR 0x4B
+#define NB_REG_STRAP 0x60
+#define NB_REG_MCPS 0x66
+#define NB_REG_SDRAM_MTR 0x68
+#define NB_REG_SDRAM_MCR 0x6A
+#define NB_REG_MBR 0x6C
+#define NB_REG_MRR 0x6E
+#define NB_REG_IO_CCR 0x70
+#define NB_REG_CPU_DCR 0x72
+#define NB_REG_DDR_MTR 0x74
+#define NB_REG_SMM 0x83
+#define NB_REG_MAR 0x84
+#define NB_REG_CID 0x90
+#define NB_REG_S1R 0x94
+#define NB_REG_S2R 0x98
+#define NB_REG_S3R 0x9C
+#define NB_REG_HOST_CTL 0xA0
+#define NB_REG_CPU_MBCR 0xC4
+#define NB_REG_CDR 0xD0
+#define NB_REG_PACR 0xF0
+#define NB_REG_PMCR 0xF4
+#define NB_REG_PCI_TARGET 0xF8
+#define NB_REG_PCSCR 0xFC
+
+/* Additional "virtual" device, just extension of NB */
+#define NB1 PCI_DEV(0, 0, 1)
+#define NB1_REG_DDRII_PHY_CTL3 0x50
+#define NB1_REG_DDR_PWR_SAV 0xBC
+#define NB1_REG_DDRII_CTL_OPT1 0xC0
+#define NB1_REG_DDRII_CTL_OPT2 0xC4
+#define NB1_REG_DDRII_CTL_OPT3 0xC8
+#define NB1_REG_DDRII_CTL_OPT4 0xCC
+#define NB1_REG_TEST_MODE 0xD0
+#define NB1_REG_PCI_DELAY_LINE 0xD1
+#define NB1_REG_L2_CACHE_CTL 0xE8
+#define NB1_REG_SSCR 0xEC
+#define NB1_REG_DDRII_CTL 0xF0
+#define NB1_REG_DDRII_PHY_CTL1 0xF4
+#define NB1_REG_DDRII_PHY_CTL2 0xF8
+
+#endif /* NORTHBRIDGE_DMP_VORTEX86EX_H */
diff --git a/src/northbridge/dmp/vortex86ex/raminit.c b/src/northbridge/dmp/vortex86ex/raminit.c
new file mode 100644
index 0000000..54355f9
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/raminit.c
@@ -0,0 +1,559 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define DDRII_CTL_REG_tRAS 0x12
+#define DDRII_CTL_REG_tRRD 0x6
+#define DDRII_CTL_REG_tFAW 0x14
+#define DDRII_CTL_REG_tRTP 0x3
+#define DDRII_CTL_REG_tWTR 0x4
+#define DDRII_CTL_REG_tRC 0x15
+#define DDRII_CTL_REG_DQSnEN 0x0
+
+#define DDR_CTRL_VAL \
+ (DDRII_CTL_REG_tRAS << 20) | \
+ (DDRII_CTL_REG_tRRD << 17) | \
+ (DDRII_CTL_REG_tFAW << 12) | \
+ (DDRII_CTL_REG_tRTP << 9) | \
+ (DDRII_CTL_REG_tWTR << 6) | \
+ (DDRII_CTL_REG_tRC << 1) | \
+ (DDRII_CTL_REG_DQSnEN)
+
+#define DDRII_PHY_CTL_1 0x000186c3
+#define DDRII_PHY_CTL_2 0x00060000
+
+static void config_pci_northbridge_f1(void)
+{
+ u16 i;
+ // DDRII PHY Control 2
+ pci_write_config32(NB1, 0xf8, DDRII_PHY_CTL_2);
+ // DDRII PHY Control 1
+ pci_write_config32(NB1, 0xf4, DDRII_PHY_CTL_1);
+ // wait PHY lock.
+ post_code(0x09);
+ while ((pci_read_config32(NB1, 0xf8) & (1 << 21)) == 0) {
+ }
+ post_code(0x0a);
+ // wait PHY stable.
+ for (i = 0; i < 0x300; i++) {
+ inb(0x80);
+ }
+ // DDRII control register.
+ pci_write_config32(NB1, 0xf0, DDR_CTRL_VAL);
+}
+
+#define MEM_CLK_PHASE_R 0x0e
+#define MEM_CLK_PHASE_W 0x01
+
+#define ODT_EN 0x0
+#define OUTPUT_DRIVER_IMPEDANCE 0x0
+#define ODT_CONTROL 0x0
+#define ADDITIVE_LATENCY 0x0
+#define DDR_CTL_CAS_LATENCY 0x5
+#define DDR_TIMING_tWR 0x5
+#define DDR_TIMING_tRFC 0x16
+#define DDR_TIMING_tRP 0x5
+#define DDR_TIMING_tRCD 0x5
+
+#define DDR_TIMING_VAL \
+ (ODT_EN << 27) | \
+ (OUTPUT_DRIVER_IMPEDANCE << 25) | \
+ (ODT_CONTROL << 23) | \
+ (ADDITIVE_LATENCY << 20) | \
+ (DDR_CTL_CAS_LATENCY << 17) | \
+ (DDR_TIMING_tWR << 14) | \
+ (DDR_TIMING_tRFC << 8) | \
+ (DDR_TIMING_tRP << 4) | \
+ (DDR_TIMING_tRCD)
+
+static void config_pci_northbridge_f0(void)
+{
+ // Memory clock phase selecton register.
+ pci_write_config8(NB, 0x66, MEM_CLK_PHASE_R << 4 | MEM_CLK_PHASE_W);
+ // DDRII memory timing register.
+ pci_write_config32(NB, 0x74, DDR_TIMING_VAL);
+}
+
+// memory bank register control:
+// bit :
+// 2 - 0 : CAT : Column Address Type : 0 0 1 = 9bit
+// : 0 1 0 = 10bit
+// 4 - 3 : BN : Bank Number : 1 0 = 4 bank
+// : 1 1 = 8 bank
+// 7 - 5 : RAT : Row Address Type : 0 1 0 = 13bit
+// : 0 1 1 = 14bit
+// : 1 0 0 : 15bit
+// 11 - 8 : SS : Size : 0 1 0 0 = 32M
+// : 0 1 0 1 = 64M
+// : 0 1 1 0 = 128M
+// : 0 1 1 1 = 256M
+// : 1 0 0 0 = 512M
+// 13 : C1M : CS#[1] Mask : 0 = actived
+// : 1 = mask
+
+#define COL_9BIT 1
+#define COL_10BIT 2
+#define BANK_2BIT 2
+#define BANK_3BIT 3
+#define ROW_13BIT 2
+#define ROW_14BIT 3
+#define ROW_15BIT 4
+#define SIZE_32M 4
+#define SIZE_64M 5
+#define SIZE_128M 6
+#define SIZE_256M 7
+#define SIZE_512M 8
+#define C1M_ACTIVE 0
+#define C1M_MASK 1
+
+static u16 get_mask(u16 bit_width, u16 bit_offset)
+{
+ u16 mask = (((1 << bit_width) - 1) << bit_offset);
+ return mask;
+}
+
+static u16 set_bitfield(u16 val, u16 bits, u16 bit_width, u16 bit_offset)
+{
+ u16 mask = get_mask(bit_width, bit_offset);
+ val = (val & ~mask) | (bits << bit_offset);
+ return val;
+}
+
+static u16 get_bitfield(u16 val, u16 bit_width, u16 bit_offset)
+{
+ u16 mask = get_mask(bit_width, bit_offset);
+ return (val & mask) >> bit_offset;
+}
+
+static u16 set_mem_bank_reg_cat(u16 reg, u16 cat)
+{
+ return set_bitfield(reg, cat, 3, 0);
+}
+
+static u16 get_mem_bank_reg_cat(u16 reg)
+{
+ return get_bitfield(reg, 3, 0);
+}
+
+static u16 set_mem_bank_reg_bn(u16 reg, u16 bn)
+{
+ return set_bitfield(reg, bn, 2, 3);
+}
+
+static u16 get_mem_bank_reg_bn(u16 reg)
+{
+ return get_bitfield(reg, 2, 3);
+}
+
+static u16 set_mem_bank_reg_rat(u16 reg, u16 rat)
+{
+ return set_bitfield(reg, rat, 3, 5);
+}
+
+static u16 get_mem_bank_reg_rat(u16 reg)
+{
+ return get_bitfield(reg, 3, 5);
+}
+
+static u16 set_mem_bank_reg_ss(u16 reg, u16 ss)
+{
+ return set_bitfield(reg, ss, 4, 8);
+}
+
+static u16 get_mem_bank_reg_ss(u16 reg)
+{
+ return get_bitfield(reg, 4, 8);
+}
+
+static u16 set_mem_bank_reg_c1m(u16 reg, u16 c1m)
+{
+ return set_bitfield(reg, c1m, 1, 13);
+}
+
+static u16 get_mem_bank_reg_c1m(u16 reg)
+{
+ return get_bitfield(reg, 1, 13);
+}
+
+static u16 auto_set_mem_bank_reg_ss(u16 reg)
+{
+ u8 ss = 0;
+ // If reg is the minimum DRAM size,
+ // SS is also the minimum size 32M.
+ // If size in reg is bigger, SS is also bigger.
+ ss += get_mem_bank_reg_cat(reg) - 1;
+ ss += get_mem_bank_reg_bn(reg) - 2;
+ ss += get_mem_bank_reg_rat(reg) - 2;
+ ss += (1 - get_mem_bank_reg_c1m(reg));
+ ss += SIZE_32M;
+ return set_mem_bank_reg_ss(reg, ss);
+}
+
+static u16 get_mem_bank_reg(u16 cat, u16 bn, u16 rat, u16 c1m)
+{
+ u16 reg;
+ reg = 0;
+ reg = set_mem_bank_reg_cat(reg, cat);
+ reg = set_mem_bank_reg_bn(reg, bn);
+ reg = set_mem_bank_reg_rat(reg, rat);
+ reg = set_mem_bank_reg_c1m(reg, c1m);
+ reg = auto_set_mem_bank_reg_ss(reg);
+ return reg;
+}
+
+static u8 check_address_bit(int addr_bit)
+{
+ u16 dummy;
+ *(volatile u16 *)(0) = 0;
+ dummy = *(volatile u16 *)(0); // read push write
+ *(volatile u16 *)(1 << addr_bit) = 0x5a5a;
+ dummy = *(volatile u16 *)(1 << addr_bit); // read push write
+ if ((*(volatile u16 *)(0)) != 0)
+ return 0; // address bit wrapped.
+ return 1; // address bit not wrapped.
+}
+
+static u8 check_dram_side(int addr_bit)
+{
+ *(volatile u16 *)(1 << addr_bit) = 0x5a5a;
+ *(volatile u16 *)(0) = 0;
+ if ((*(volatile u16 *)(1 << addr_bit)) != 0x5a5a)
+ return 0; // DRAM only one side.
+ return 1; // two sides.
+}
+
+static void detect_dram_size_failed(void)
+{
+ post_code(0x77);
+ while (1) ;
+}
+
+static void detect_dram_cs(u16 br, u8 base_addr_bit)
+{
+ br = set_mem_bank_reg_c1m(br, C1M_ACTIVE);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_dram_side(base_addr_bit + 1)) {
+ base_addr_bit += 1;
+ return;
+ }
+
+ br = set_mem_bank_reg_c1m(br, C1M_MASK);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ // no need to check CS = 0.
+}
+
+static void detect_dram_row(u16 br, u8 base_addr_bit, u8 row_from_14)
+{
+ if (row_from_14)
+ goto row_14;
+
+ br = set_mem_bank_reg_rat(br, ROW_15BIT);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_address_bit(base_addr_bit + 15)) {
+ base_addr_bit += 15;
+ detect_dram_cs(br, base_addr_bit);
+ return;
+ }
+
+row_14:
+ br = set_mem_bank_reg_rat(br, ROW_14BIT);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_address_bit(base_addr_bit + 14)) {
+ base_addr_bit += 14;
+ detect_dram_cs(br, base_addr_bit);
+ return;
+ }
+
+ br = set_mem_bank_reg_rat(br, ROW_13BIT);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_address_bit(base_addr_bit + 13)) {
+ base_addr_bit += 13;
+ detect_dram_cs(br, base_addr_bit);
+ return;
+ }
+ // row test error.
+ detect_dram_size_failed();
+}
+
+static void detect_dram_bank(u16 br, u8 base_addr_bit, u8 row_from_14)
+{
+ br = set_mem_bank_reg_bn(br, BANK_3BIT);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_address_bit(base_addr_bit + 3)) {
+ base_addr_bit += 3;
+ detect_dram_row(br, base_addr_bit, row_from_14);
+ return;
+ }
+
+ br = set_mem_bank_reg_bn(br, BANK_2BIT);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_address_bit(base_addr_bit + 2)) {
+ base_addr_bit += 2;
+ detect_dram_row(br, base_addr_bit, row_from_14);
+ return;
+ }
+ // bank test error.
+ detect_dram_size_failed();
+}
+
+static void detect_dram_col(u16 br, u8 base_addr_bit, u8 row_from_14)
+{
+ br = set_mem_bank_reg_cat(br, COL_10BIT);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_address_bit(base_addr_bit + 10)) {
+ base_addr_bit += 10;
+ detect_dram_bank(br, base_addr_bit, row_from_14);
+ return;
+ }
+
+ br = set_mem_bank_reg_cat(br, COL_9BIT);
+ br = auto_set_mem_bank_reg_ss(br);
+ pci_write_config16(NB, NB_REG_MBR, br);
+ if (check_address_bit(base_addr_bit + 9)) {
+ base_addr_bit += 9;
+ detect_dram_bank(br, base_addr_bit, row_from_14);
+ return;
+ }
+ // col test error.
+ detect_dram_size_failed();
+}
+
+static void detect_dram_size(void)
+{
+ u16 br;
+ u8 base_addr_bit = 0;
+ br = get_mem_bank_reg(COL_10BIT, BANK_2BIT, ROW_13BIT, C1M_MASK);
+ // check DX CPU model.
+ if (pci_read_config8(NB, 0x8) == 0x01 && pci_read_config8(SB, 0x8) == 0x01) {
+ // for oldest DX CPU, DRAM max row is from 14, not 15.
+ detect_dram_col(br, base_addr_bit, 1);
+ } else {
+ // for newer DX CPU, DRAM max row is from 15.
+ detect_dram_col(br, base_addr_bit, 0);
+ }
+}
+
+// DDRIII memory bank register control:
+// bit :
+// 2 - 0 : DRAMC_COLSIZE : DDRIII Column Address Type : 0 0 0 = 10bit
+// : 0 0 1 = 11bit
+// 7 - 5 : DRAMC_ROWSIZE : DDRIII Row Address Type : 0 0 0 = 13bit
+// : 0 0 1 = 14bit
+// : 0 1 0 = 15bit
+// : 0 1 1 = 16bit
+// 11 - 8 : DRAM_SIZE : DDRIII Size : 0 1 0 1 = 64M
+// : 0 1 1 0 = 128M
+// : 0 1 1 1 = 256M
+// : 1 0 0 0 = 512M
+// : 1 0 0 1 = 1GB
+// : 1 0 1 0 = 2GB
+// 13 : DRAMC_CSMASK : DDRIII CS#[1] Mask : 1 = Mask CS1 enable
+
+#define DDR3_COL_10BIT 0
+#define DDR3_COL_11BIT 1
+#define DDR3_ROW_13BIT 0
+#define DDR3_ROW_14BIT 1
+#define DDR3_ROW_15BIT 2
+#define DDR3_ROW_16BIT 3
+#define DDR3_SIZE_64M 5
+#define DDR3_SIZE_128M 6
+#define DDR3_SIZE_256M 7
+#define DDR3_SIZE_512M 8
+#define DDR3_SIZE_1GB 9
+#define DDR3_SIZE_2GB 10
+#define DDR3_C1M_ACTIVE 0
+#define DDR3_C1M_MASK 1
+
+static u16 set_ddr3_mem_reg_col(u16 reg, u16 col)
+{
+ return set_bitfield(reg, col, 3, 0);
+}
+
+static u16 get_ddr3_mem_reg_col(u16 reg)
+{
+ return get_bitfield(reg, 3, 0);
+}
+
+static u16 set_ddr3_mem_reg_row(u16 reg, u16 row)
+{
+ return set_bitfield(reg, row, 3, 5);
+}
+
+static u16 get_ddr3_mem_reg_row(u16 reg)
+{
+ return get_bitfield(reg, 3, 5);
+}
+
+static u16 set_ddr3_mem_reg_size(u16 reg, u16 size)
+{
+ return set_bitfield(reg, size, 4, 8);
+}
+
+static u16 get_ddr3_mem_reg_size(u16 reg)
+{
+ return get_bitfield(reg, 4, 8);
+}
+
+static u16 set_ddr3_mem_reg_c1m(u16 reg, u16 c1m)
+{
+ return set_bitfield(reg, c1m, 1, 13);
+}
+
+static u16 get_ddr3_mem_reg_c1m(u16 reg)
+{
+ return get_bitfield(reg, 1, 13);
+}
+
+static u16 auto_set_ddr3_mem_reg_size(u16 reg)
+{
+ u8 ss = 0;
+ // If reg is the minimum DRAM size,
+ // SS is also the minimum size 128M.
+ // If size in reg is bigger, SS is also bigger.
+ ss += get_ddr3_mem_reg_col(reg);
+ ss += get_ddr3_mem_reg_row(reg);
+ ss += (1 - get_ddr3_mem_reg_c1m(reg));
+ ss += DDR3_SIZE_128M;
+ return set_ddr3_mem_reg_size(reg, ss);
+}
+
+static u16 get_ddr3_mem_reg(u16 col, u16 row, u16 c1m)
+{
+ u16 reg;
+ reg = 0;
+ reg = set_ddr3_mem_reg_col(reg, col);
+ reg = set_ddr3_mem_reg_row(reg, row);
+ reg = set_ddr3_mem_reg_c1m(reg, c1m);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ return reg;
+}
+
+static void ddr3_phy_reset(void)
+{
+ // PCI N/B reg FAh bit 6 = RST_DRAM_PHY.
+ pci_write_config8(NB1, 0xfa, 0x40);
+ while ((pci_read_config8(NB1, 0xfa) & 0x40) == 0x40) {
+ }
+ // reload mode.
+ pci_write_config32(NB, 0x74, pci_read_config32(NB, 0x74));
+}
+
+static void detect_ddr3_dram_cs(u16 reg, u8 base_addr_bit)
+{
+ reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_ACTIVE);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ if (check_dram_side(base_addr_bit + 1)) {
+ base_addr_bit += 1;
+ return;
+ }
+
+ reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_MASK);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ // no need to check CS = 0.
+ // Need to reset DDR3 PHY.
+ ddr3_phy_reset();
+}
+
+static void detect_ddr3_dram_row(u16 reg, u8 base_addr_bit)
+{
+ reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_16BIT);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ if (check_address_bit(base_addr_bit + 16)) {
+ base_addr_bit += 16;
+ detect_ddr3_dram_cs(reg, base_addr_bit);
+ return;
+ }
+
+ reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_15BIT);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ if (check_address_bit(base_addr_bit + 15)) {
+ base_addr_bit += 15;
+ detect_ddr3_dram_cs(reg, base_addr_bit);
+ return;
+ }
+
+ reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_14BIT);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ if (check_address_bit(base_addr_bit + 14)) {
+ base_addr_bit += 14;
+ detect_ddr3_dram_cs(reg, base_addr_bit);
+ return;
+ }
+
+ reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_13BIT);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ if (check_address_bit(base_addr_bit + 13)) {
+ base_addr_bit += 13;
+ detect_ddr3_dram_cs(reg, base_addr_bit);
+ return;
+ }
+ // row test error.
+ detect_dram_size_failed();
+}
+
+static void detect_ddr3_dram_bank(u16 reg, u8 base_addr_bit)
+{
+ /* DDR3 is always 3 bank bits */
+ base_addr_bit += 3;
+ detect_ddr3_dram_row(reg, base_addr_bit);
+}
+
+static void detect_ddr3_dram_col(u16 reg, u8 base_addr_bit)
+{
+ reg = set_ddr3_mem_reg_col(reg, DDR3_COL_11BIT);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ if (check_address_bit(base_addr_bit + 11)) {
+ base_addr_bit += 11;
+ detect_ddr3_dram_bank(reg, base_addr_bit);
+ return;
+ }
+
+ reg = set_ddr3_mem_reg_col(reg, DDR3_COL_10BIT);
+ reg = auto_set_ddr3_mem_reg_size(reg);
+ pci_write_config16(NB, NB_REG_MBR, reg);
+ if (check_address_bit(base_addr_bit + 10)) {
+ base_addr_bit += 10;
+ detect_ddr3_dram_bank(reg, base_addr_bit);
+ return;
+ }
+ // col test error.
+ detect_dram_size_failed();
+}
+
+static void detect_ddr3_dram_size(void)
+{
+ u16 reg;
+ u8 base_addr_bit = 0;
+ reg = get_ddr3_mem_reg(DDR3_COL_10BIT, DDR3_ROW_13BIT, DDR3_C1M_MASK);
+ detect_ddr3_dram_col(reg, base_addr_bit);
+}
diff --git a/src/northbridge/dmp/vortex86ex/xgi_oprom.c b/src/northbridge/dmp/vortex86ex/xgi_oprom.c
new file mode 100644
index 0000000..dc814c2
--- /dev/null
+++ b/src/northbridge/dmp/vortex86ex/xgi_oprom.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/********************************************************************
+ * Change the vendor / device IDs to match the XGI Z9S VBIOS header.
+ ********************************************************************/
+#include <device/pci.h>
+u32 map_oprom_vendev(u32 vendev)
+{
+ u32 new_vendev = vendev;
+
+ switch (vendev) {
+ case 0x18ca0020:
+ new_vendev = 0x18ca0021;
+ break;
+ }
+
+ return new_vendev;
+}
diff --git a/src/southbridge/Kconfig b/src/southbridge/Kconfig
index 31b7cc6..84b5f8d 100644
--- a/src/southbridge/Kconfig
+++ b/src/southbridge/Kconfig
@@ -1,5 +1,6 @@
source src/southbridge/amd/Kconfig
source src/southbridge/broadcom/Kconfig
+source src/southbridge/dmp/Kconfig
source src/southbridge/intel/Kconfig
source src/southbridge/nvidia/Kconfig
source src/southbridge/rdc/Kconfig
diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc
index 130d459..106752b 100644
--- a/src/southbridge/Makefile.inc
+++ b/src/southbridge/Makefile.inc
@@ -1,5 +1,6 @@
subdirs-y += amd
subdirs-y += broadcom
+subdirs-y += dmp
subdirs-y += intel
subdirs-y += nvidia
subdirs-y += rdc
diff --git a/src/southbridge/dmp/Kconfig b/src/southbridge/dmp/Kconfig
new file mode 100644
index 0000000..1c5b8c7
--- /dev/null
+++ b/src/southbridge/dmp/Kconfig
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+source src/southbridge/dmp/vortex86ex/Kconfig
diff --git a/src/southbridge/dmp/Makefile.inc b/src/southbridge/dmp/Makefile.inc
new file mode 100644
index 0000000..a94e935
--- /dev/null
+++ b/src/southbridge/dmp/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-$(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX) += vortex86ex
diff --git a/src/southbridge/dmp/vortex86ex/Kconfig b/src/southbridge/dmp/vortex86ex/Kconfig
new file mode 100644
index 0000000..1f73da4
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/Kconfig
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config SOUTHBRIDGE_DMP_VORTEX86EX
+ bool
+ select HAVE_HARD_RESET
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/dmp/vortex86ex/bootblock.c"
+ depends on SOUTHBRIDGE_DMP_VORTEX86EX
diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc
new file mode 100644
index 0000000..6d2a921
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 DMP Electronics Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += southbridge.c
+ramstage-y += hard_reset.c
+ramstage-y += ide_sd_sata.c
diff --git a/src/southbridge/dmp/vortex86ex/bootblock.c b/src/southbridge/dmp/vortex86ex/bootblock.c
new file mode 100644
index 0000000..165d22e
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/bootblock.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "drivers/pc80/i8254.c"
+#include "southbridge.h"
+
+/************************************************************************/
+/* south bridge configuration space access routines */
+/************************************************************************/
+
+uint8_t pci_read_sb_config8(unsigned where)
+{
+ return (pci_io_read_config8(SB, where));
+}
+
+void pci_write_sb_config8(unsigned where, uint8_t value)
+{
+ pci_io_write_config8(SB, where, value);
+}
+
+uint16_t pci_read_sb_config16(unsigned where)
+{
+ return (pci_io_read_config16(SB, where));
+}
+
+void pci_write_sb_config16(unsigned where, uint16_t value)
+{
+ pci_io_write_config16(SB, where, value);
+}
+
+uint32_t pci_read_sb_config32(unsigned where)
+{
+ return (pci_io_read_config32(SB, where));
+}
+
+void pci_write_sb_config32(unsigned where, uint32_t value)
+{
+ pci_io_write_config32(SB, where, value);
+}
+
+/************************************************************************/
+/* bootblock south bridge initialize */
+/************************************************************************/
+
+void bootblock_southbridge_init(void)
+{
+ /* enable fast ga20 */
+ pci_write_sb_config8(SB_REG_LPCCR, pci_read_sb_config8(SB_REG_LPCCR) | 0x16);
+ outb(inb(SYSTEM_CTL_PORT) | 0x02, SYSTEM_CTL_PORT);
+ setup_i8254();
+}
diff --git a/src/southbridge/dmp/vortex86ex/chip.h b/src/southbridge/dmp/vortex86ex/chip.h
new file mode 100644
index 0000000..09312f9
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/chip.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _SOUTHBRIDGE_DMP_VORTEX86EX
+#define _SOUTHBRIDGE_DMP_VORTEX86EX
+
+struct southbridge_dmp_vortex86ex_config {
+ /* PCI function enables */
+ /* i.e. so that pci scan bus will find them. */
+ /* I am putting in IDE as an example but obviously this needs
+ * to be more complete!
+ */
+ int enable_ide;
+ /* enables of functions of devices */
+ int enable_usb;
+ int enable_native_ide;
+ int enable_com_ports;
+ int enable_keyboard;
+ int enable_nvram;
+};
+
+#endif /* _SOUTHBRIDGE_DMP_VORTEX86EX */
diff --git a/src/southbridge/dmp/vortex86ex/hard_reset.c b/src/southbridge/dmp/vortex86ex/hard_reset.c
new file mode 100644
index 0000000..5d216ab
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/hard_reset.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+}
diff --git a/src/southbridge/dmp/vortex86ex/ide_sd_sata.c b/src/southbridge/dmp/vortex86ex/ide_sd_sata.c
new file mode 100644
index 0000000..8214549
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/ide_sd_sata.c
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdlib.h>
+#include <string.h>
+#include <arch/io.h>
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+
+/* Vortex86EX IDE to SD/STAT controller need to enable ATA decoder and
+ * setup timing. */
+
+/*
+ * Primary ATA Timing Register (PATR) - Offset 40-41h
+ * Secondary ATA Timing Register (PATR) - Offset 42-43h
+ *
+ * Bit R/W Default Description
+ * 15 R/W 0h ATA Decode Enable. Decode the I/O addressing ranges assigned to this controller.
+ * 1: Enabled.
+ * 0: Disabled.
+ * 14 R/W 0b Device 1 ATA Timing Register Enable
+ * 1: Enable the device 1 ATA timing.
+ * 0: Disable the device 1 ATA timing
+ * 13-12 R/W 0h IORDY Sample Mode. Sets the setup time before IORDY are sampled.
+ * 00: PIO-0
+ * 10: PIO-2, SW-2
+ * 10: PIO-3, PIO-4, MW-1, MW-2
+ * 11: Reserved
+ * 11-10 RO 0h Reserved
+ * 9-8 R/W 0h Recovery Mode. Sets the hold time after IORDY are sampled.
+ * 00: PIO-0, PIO-2, SW-2
+ * 10: PIO-3, MW-1
+ * 10: Reserved
+ * 11: PIO-4, MW-2
+ * 7 R/W 0b DMA Timing Enable Only Select 1
+ * 1: Enable the device timings for DMA operation for device 1
+ * 0: Disable the device timings for DMA operation for device 1
+ * 6 R/W 0b ATA/ATAPI Device Indicator 1
+ * 1: Indicate presence od an ATA device
+ * 0: Indicate presence od an ATAPI device
+ * 5 R/W 0b IORDY Sample Point Enabled Select 1
+ * 1: Enable IORDY sample for PIO transfers for device 1
+ * 0: Disable IORDY sample for PIO transfers for device 1
+ * 4 R/W 0b Fast Drive Timing Select 1
+ * 1: Enable faster than PIO-0 timing modes for device 1
+ * 0: Disable faster than PIO-0 timing modes for device 1
+ * 3 R/W 0b DMA Timing Enable Only Select 0
+ * 1: Enable the device timings for DMA operation for device 0
+ * 0: Disable the device timings for DMA operation for device 0
+ * 2 R/W 0b ATA/ATAPI Device Indicator 0
+ * 1: Indicate presence od an ATA device
+ * 0: Indicate presence od an ATAPI device
+ * 1 R/W 0b IORDY Sample Point Enabled Select 0
+ * 1: Enable IORDY sample for PIO transfers for device 0
+ * 0: Disable IORDY sample for PIO transfers for device 0
+ * 0 R/W 0b Fast Drive Timing Select 0
+ * 1: Enable faster than PIO-0 timing modes for device 0
+ * 0: Disable faster than PIO-0 timing modes for device 0
+ * */
+
+static void init_ide_ata_timing(struct device *dev)
+{
+ u16 ata_timing_pri, ata_timing_sec;
+ u32 ata_timing_reg32;
+ /* Primary channel is SD. */
+#if CONFIG_IDE1_ENABLE
+ ata_timing_pri = 0x8000;
+#else
+ ata_timing_pri = 0x0000; // Disable this channel.
+#endif
+ /* Secondary channel is SATA. */
+#if CONFIG_IDE2_ENABLE
+ ata_timing_sec = 0xa30f; // This setting value works well.
+#else
+ ata_timing_sec = 0x0000; // Disable this channel.
+#endif
+ ata_timing_reg32 = (ata_timing_sec << 16) | ata_timing_pri;
+ pci_write_config32(dev, 0x40, ata_timing_reg32);
+#if CONFIG_IDE_NATIVE_MODE
+ /* Set both IDE channels to native mode. */
+ u8 prog_if;
+ prog_if = pci_read_config8(dev, 0x09);
+ prog_if |= 5;
+ pci_write_config8(dev, 0x09, prog_if);
+#endif
+ /* MMC function enable. */
+ u32 sd_ctrl_reg;
+ sd_ctrl_reg = pci_read_config32(dev, 0x94);
+ sd_ctrl_reg |= 0x0200;
+ pci_write_config32(dev, 0x94, sd_ctrl_reg);
+ printk(BIOS_INFO, "Vortex86EX IDE controller ATA TIMING reg = %08x\n", ata_timing_reg32);
+}
+
+static void setup_std_ide_compatible(struct device *dev)
+{
+#if CONFIG_IDE_STANDARD_COMPATIBLE
+ // Misc Control Register (MCR) Offset 90h
+ // bit 0 = Vendor ID Access, bit 1 = Device ID Access.
+ u8 mcr;
+ u16 vendor = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION >> 16);
+ u16 device = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION & 0xffff);
+ // unlock vendor/device ID access bits.
+ mcr = pci_read_config8(dev, 0x90);
+ pci_write_config8(dev, 0x90, mcr | 3);
+ pci_write_config16(dev, 0x00, vendor);
+ pci_write_config16(dev, 0x02, device);
+ // restore lock bits.
+ pci_write_config8(dev, 0x90, mcr);
+#endif
+}
+
+static void vortex_ide_init(struct device *dev)
+{
+ if (dev->device == 0x1010) {
+ // This is SX/old DX IDE controller.
+ // Set IOCFG bit 15/13 : IDE Decoder Enable for Primary/Secondary channel.
+ u16 iocfg = 0xa000;
+ pci_write_config16(dev, 0x40, iocfg);
+ } else if (dev->device == 0x1011 || dev->device == 0x1012) {
+ // This is new DX/MX/MX+/DX2 IDE controller.
+ init_ide_ata_timing(dev);
+ setup_std_ide_compatible(dev);
+ }
+}
+
+static struct device_operations vortex_ide_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = vortex_ide_init,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver vortex_ide_driver_1010 __pci_driver = {
+ .ops = &vortex_ide_ops,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device = 0x1010,
+};
+
+static const struct pci_driver vortex_ide_driver_1011 __pci_driver = {
+ .ops = &vortex_ide_ops,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device = 0x1011,
+};
+
+static const struct pci_driver vortex_ide_driver_1012 __pci_driver = {
+ .ops = &vortex_ide_ops,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device = 0x1012,
+};
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
new file mode 100644
index 0000000..bc8252c
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -0,0 +1,563 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <string.h>
+#include "arch/io.h"
+#include "chip.h"
+#include "southbridge.h"
+
+/* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */
+static const unsigned char irq_to_sb_int_routing[16] = {
+ 0x0, 0x0, 0x0, 0x2, // IRQ0-2 is unmappable, IRQ3 = 2.
+ 0x4, 0x5, 0x7, 0x6, // IRQ4-7 = 4, 5, 7, 6.
+ 0x0, 0x1, 0x3, 0x9, // IRQ8 is unmappable, IRQ9-11 = 1, 3, 9.
+ 0xb, 0x0, 0xd, 0xf // IRQ12 = b, IRQ13 is unmappable, IRQ14-15 = d, f.
+};
+
+/* S/B PCI Interrupt routing table reg(0x58) field bit shift. */
+#define EHCIH_IRQ_SHIFT 28
+#define OHCII_IRQ_SHIFT 24
+#define MAC_IRQ_SHIFT 16
+#define RT3_IRQ_SHIFT 12
+#define RT2_IRQ_SHIFT 8
+#define RT1_IRQ_SHIFT 4
+#define RT0_IRQ_SHIFT 0
+
+/* S/B Extend PCI Interrupt routing table reg(0xb4) field bit shift. */
+#define USBD_IRQ_SHIFT 16
+#define SIDE_IRQ_SHIFT 12
+#define PIDE_IRQ_SHIFT 8
+#define EHCI2_IRQ_SHIFT 4
+#define OHCI2_IRQ_SHIFT 0
+
+/* in-chip PCI device IRQs(0 for disabled). */
+#define EHCII_IRQ 5
+#define OHCII_IRQ 5
+#define MAC_IRQ 6
+
+#define USBD_IRQ 0
+#define PIDE_IRQ 5
+#define EHCI2_IRQ 5
+#define OHCI2_IRQ 5
+
+/* RT0-3 IRQs. */
+#define RT3_IRQ 3
+#define RT2_IRQ 4
+#define RT1_IRQ 5
+#define RT0_IRQ 6
+
+/* IDE legacy mode IRQs. */
+#define IDE1_LEGACY_IRQ 14
+#define IDE2_LEGACY_IRQ 15
+
+/* Internal parallel port */
+#define LPT_INT_C 0
+#define LPT_INT_ACK_SET 0
+#define LPT_UE 1
+#define LPT_PDMAS 0
+#define LPT_DREQS 0
+
+static u8 get_pci_dev_func(device_t dev)
+{
+ return PCI_FUNC(dev->path.pci.devfn);
+}
+
+static void verify_dmp_keyboard_error(void)
+{
+ post_code(0x82);
+ die("Internal keyboard firmware verify error!\n");
+}
+
+static void upload_dmp_keyboard_firmware(struct device *dev)
+{
+ u32 reg_sb_c0;
+ u32 fwptr;
+
+ // enable firmware uploading function by set bit 10.
+ post_code(0x06);
+ reg_sb_c0 = pci_read_config32(dev, 0xc0);
+ pci_write_config32(dev, 0xc0, reg_sb_c0 | 0x400);
+
+ outw(0, 0x62); // reset upload address to 0.
+ // upload 4096 bytes from 0xFFFFE000.
+ outsb(0x66, (u8 *) 0xffffe000, 4096);
+ // upload 4096 bytes from 0xFFFFC000.
+ outsb(0x66, (u8 *) 0xffffc000, 4096);
+
+ outw(0, 0x62); // reset upload address to 0.
+ // verify 4096 bytes from 0xFFFFE000.
+ for (fwptr = 0xffffe000; fwptr < 0xfffff000; fwptr++) {
+ if (inb(0x66) != *(u8 *) fwptr) {
+ verify_dmp_keyboard_error();
+ }
+ }
+ // verify 4096 bytes from 0xFFFFC000.
+ for (fwptr = 0xffffc000; fwptr < 0xffffd000; fwptr++) {
+ if (inb(0x66) != *(u8 *) fwptr) {
+ verify_dmp_keyboard_error();
+ }
+ }
+
+ // disable firmware uploading.
+ pci_write_config32(dev, 0xc0, reg_sb_c0 & ~0x400L);
+ // wait keyboard controller ready by checking status port bit 2.
+ post_code(0x07);
+ while ((inb(0x64) & 0x4) == 0) {
+ }
+ post_code(0x08);
+}
+
+static void pci_routing_fixup(struct device *dev)
+{
+ const unsigned slot[3] = { 0 };
+ const unsigned char slot_irqs[1][4] = {
+ {RT0_IRQ, RT1_IRQ, RT2_IRQ, RT3_IRQ},
+ };
+ const int slot_num = 1;
+ int i;
+ u32 sb_int_routing = 0;
+ u32 sb_ext_int_routing = 0;
+
+ /* assign PCI-e bridge (bus#0, dev#1, fn#0) IRQ to RT0. */
+ pci_assign_irqs(0, 1, slot_irqs[0]);
+
+ /* RT0 is enabled. */
+ sb_int_routing |= irq_to_sb_int_routing[RT0_IRQ] << RT0_IRQ_SHIFT;
+
+ /* assign PCI slot IRQs. */
+ for (i = 0; i < slot_num; i++) {
+ pci_assign_irqs(1, slot[i], slot_irqs[i]);
+ }
+
+ /* Read PCI slot IRQs to see if RT1-3 is used, and enables it */
+ for (i = 0; i < slot_num; i++) {
+ unsigned int funct;
+ device_t pdev;
+ u8 irq;
+
+ /* Each slot may contain up to eight functions. */
+ for (funct = 0; funct < 8; funct++) {
+ pdev = dev_find_slot(1, (slot[i] << 3) + funct);
+ if (!pdev)
+ continue;
+ irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
+ if (irq == RT1_IRQ) {
+ sb_int_routing |= irq_to_sb_int_routing[RT1_IRQ] << RT1_IRQ_SHIFT;
+ } else if (irq == RT2_IRQ) {
+ sb_int_routing |= irq_to_sb_int_routing[RT2_IRQ] << RT2_IRQ_SHIFT;
+ } else if (irq == RT3_IRQ) {
+ sb_int_routing |= irq_to_sb_int_routing[RT3_IRQ] << RT3_IRQ_SHIFT;
+ }
+ }
+ }
+
+ /* Setup S/B PCI Interrupt routing table reg(0x58). */
+ sb_int_routing |= irq_to_sb_int_routing[EHCII_IRQ] << EHCIH_IRQ_SHIFT;
+ sb_int_routing |= irq_to_sb_int_routing[OHCII_IRQ] << OHCII_IRQ_SHIFT;
+ sb_int_routing |= irq_to_sb_int_routing[MAC_IRQ] << MAC_IRQ_SHIFT;
+ pci_write_config32(dev, SB_REG_PIRQ_X_ROUT, sb_int_routing);
+
+ /* Setup S/B PCI Extend Interrupt routing table reg(0xb4). */
+ sb_ext_int_routing |= irq_to_sb_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT;
+#if CONFIG_IDE_NATIVE_MODE
+ /* IDE in native mode, only uses one IRQ. */
+ sb_ext_int_routing |= irq_to_sb_int_routing[0] << SIDE_IRQ_SHIFT;
+ sb_ext_int_routing |= irq_to_sb_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT;
+#else
+ /* IDE in legacy mode, use IRQ 14, 15. */
+ sb_ext_int_routing |= irq_to_sb_int_routing[IDE2_LEGACY_IRQ] << SIDE_IRQ_SHIFT;
+ sb_ext_int_routing |= irq_to_sb_int_routing[IDE1_LEGACY_IRQ] << PIDE_IRQ_SHIFT;
+#endif
+ sb_ext_int_routing |= irq_to_sb_int_routing[EHCI2_IRQ] << EHCI2_IRQ_SHIFT;
+ sb_ext_int_routing |= irq_to_sb_int_routing[OHCI2_IRQ] << OHCI2_IRQ_SHIFT;
+ pci_write_config32(dev, SB_REG_PIRQ_X_ROUT2, sb_ext_int_routing);
+
+ /* Assign in-chip PCI device IRQs. */
+ if (MAC_IRQ) {
+ unsigned char irqs[4] = { MAC_IRQ, 0, 0, 0 };
+ pci_assign_irqs(0, 0x8, irqs);
+ }
+ if (OHCII_IRQ && EHCII_IRQ) {
+ unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 };
+ pci_assign_irqs(0, 0xa, irqs);
+ }
+ if (OHCI2_IRQ && EHCI2_IRQ) {
+ unsigned char irqs[4] = { OHCI2_IRQ, EHCI2_IRQ, 0, 0 };
+ pci_assign_irqs(0, 0xb, irqs);
+ }
+ if (CONFIG_IDE_NATIVE_MODE && PIDE_IRQ) {
+ /* IDE in native mode, setup PCI IRQ. */
+ unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 };
+ pci_assign_irqs(0, 0xc, irqs);
+ }
+ if (USBD_IRQ) {
+ unsigned char irqs[4] = { USBD_IRQ, 0, 0, 0 };
+ pci_assign_irqs(0, 0xf, irqs);
+ }
+}
+
+static void vortex_sb_init(struct device *dev)
+{
+ u32 lpt_reg = 0;
+
+#if CONFIG_LPT_ENABLE
+ int ppmod = 0;
+#if CONFIG_LPT_MODE_BPP
+ ppmod = 0;
+#elif CONFIG_LPT_MODE_EPP_19_AND_SPP
+ ppmod = 1;
+#elif CONFIG_LPT_MODE_ECP
+ ppmod = 2;
+#elif CONFIG_LPT_MODE_ECP_AND_EPP_19
+ ppmod = 3;
+#elif CONFIG_LPT_MODE_SPP
+ ppmod = 4;
+#elif CONFIG_LPT_MODE_EPP_17_AND_SPP
+ ppmod = 5;
+#elif CONFIG_LPT_MODE_ECP_AND_EPP_17
+ ppmod = 7;
+#else
+#error CONFIG_LPT_MODE error.
+#endif
+
+ /* Setup internal parallel port */
+ lpt_reg |= (LPT_INT_C << 28);
+ lpt_reg |= (LPT_INT_ACK_SET << 27);
+ lpt_reg |= (ppmod << 24);
+ lpt_reg |= (LPT_UE << 23);
+ lpt_reg |= (LPT_PDMAS << 22);
+ lpt_reg |= (LPT_DREQS << 20);
+ lpt_reg |= (irq_to_sb_int_routing[CONFIG_LPT_IRQ] << 16);
+ lpt_reg |= (CONFIG_LPT_IO << 0);
+#endif // CONFIG_LPT_ENABLE
+ pci_write_config32(dev, SB_REG_IPPCR, lpt_reg);
+}
+
+#define SETUP_GPIO_ADDR(n) \
+ u32 cfg##n = (CONFIG_GPIO_P##n##_DIR_ADDR << 16) | (CONFIG_GPIO_P##n##_DATA_ADDR);\
+ outl(cfg##n, base + 4 + (n * 4));\
+ gpio_enable_mask |= (1 << n);
+
+#define INIT_GPIO(n) \
+ outb(CONFIG_GPIO_P##n##_INIT_DIR, CONFIG_GPIO_P##n##_DIR_ADDR);\
+ outb(CONFIG_GPIO_P##n##_INIT_DATA, CONFIG_GPIO_P##n##_DATA_ADDR);
+
+static void ex_sb_gpio_init(struct device *dev)
+{
+ const int base = 0xb00;
+ u32 gpio_enable_mask = 0;
+ /* S/B register 63h - 62h : GPIO Port Config IO Base Address */
+ pci_write_config16(dev, 0x62, base | 1);
+ /* Set GPIO port 0~9 base address.
+ * Config Base + 04h, 08h, 0ch... : GPIO port 0~9 data/dir decode addr.
+ * Bit 31-16 : DBA, GPIO direction base address.
+ * Bit 15-0 : DPBA, GPIO data port base address.
+ * */
+#if CONFIG_GPIO_P0_ENABLE
+ SETUP_GPIO_ADDR(0)
+#endif
+#if CONFIG_GPIO_P1_ENABLE
+ SETUP_GPIO_ADDR(1)
+#endif
+#if CONFIG_GPIO_P2_ENABLE
+ SETUP_GPIO_ADDR(2)
+#endif
+#if CONFIG_GPIO_P3_ENABLE
+ SETUP_GPIO_ADDR(3)
+#endif
+#if CONFIG_GPIO_P4_ENABLE
+ SETUP_GPIO_ADDR(4)
+#endif
+#if CONFIG_GPIO_P5_ENABLE
+ SETUP_GPIO_ADDR(5)
+#endif
+#if CONFIG_GPIO_P6_ENABLE
+ SETUP_GPIO_ADDR(6)
+#endif
+#if CONFIG_GPIO_P7_ENABLE
+ SETUP_GPIO_ADDR(7)
+#endif
+#if CONFIG_GPIO_P8_ENABLE
+ SETUP_GPIO_ADDR(8)
+#endif
+#if CONFIG_GPIO_P9_ENABLE
+ SETUP_GPIO_ADDR(9)
+#endif
+ /* Enable GPIO port 0~9. */
+ outl(gpio_enable_mask, base);
+ /* Set GPIO port 0-9 initial dir and data. */
+#if CONFIG_GPIO_P0_ENABLE
+ INIT_GPIO(0)
+#endif
+#if CONFIG_GPIO_P1_ENABLE
+ INIT_GPIO(1)
+#endif
+#if CONFIG_GPIO_P2_ENABLE
+ INIT_GPIO(2)
+#endif
+#if CONFIG_GPIO_P3_ENABLE
+ INIT_GPIO(3)
+#endif
+#if CONFIG_GPIO_P4_ENABLE
+ INIT_GPIO(4)
+#endif
+#if CONFIG_GPIO_P5_ENABLE
+ INIT_GPIO(5)
+#endif
+#if CONFIG_GPIO_P6_ENABLE
+ INIT_GPIO(6)
+#endif
+#if CONFIG_GPIO_P7_ENABLE
+ INIT_GPIO(7)
+#endif
+#if CONFIG_GPIO_P8_ENABLE
+ INIT_GPIO(8)
+#endif
+#if CONFIG_GPIO_P9_ENABLE
+ INIT_GPIO(9)
+#endif
+ /* Disable GPIO Port Config IO Base Address. */
+ pci_write_config16(dev, 0x62, 0x0);
+}
+
+static u32 make_uart_config(u16 base, u8 irq)
+{
+ u8 mapped_irq = irq_to_sb_int_routing[irq];
+ u32 cfg = 0;
+ cfg |= 1 << 23; // UE = enabled.
+ cfg |= (mapped_irq << 16); // UIRT.
+ cfg |= base; // UIOA.
+ return cfg;
+}
+
+#define SETUP_UART(n) \
+ uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\
+ outl(uart_cfg, base + (n - 1) * 4);\
+ uart8250_init(CONFIG_UART##n##_IO, 115200 / CONFIG_UART##n##_BAUD);
+
+static void ex_sb_uart_init(struct device *dev)
+{
+ const int base = 0xc00;
+ u32 uart_cfg = 0;
+ /* S/B register 61h - 60h : UART Config IO Base Address */
+ pci_write_config16(dev, 0x60, 0xc01);
+ /* setup UART */
+#if CONFIG_UART1_ENABLE
+ SETUP_UART(1)
+#endif
+#if CONFIG_UART2_ENABLE
+ SETUP_UART(2)
+#endif
+#if CONFIG_UART3_ENABLE
+ SETUP_UART(3)
+#endif
+#if CONFIG_UART4_ENABLE
+ SETUP_UART(4)
+#endif
+#if CONFIG_UART5_ENABLE
+ SETUP_UART(5)
+#endif
+#if CONFIG_UART6_ENABLE
+ SETUP_UART(6)
+#endif
+#if CONFIG_UART7_ENABLE
+ SETUP_UART(7)
+#endif
+#if CONFIG_UART8_ENABLE
+ SETUP_UART(8)
+#endif
+#if CONFIG_UART9_ENABLE
+ SETUP_UART(9)
+#endif
+#if CONFIG_UART10_ENABLE
+ SETUP_UART(10)
+#endif
+ /* Keep UART Config I/O base address */
+ //pci_write_config16(SB, 0x60, 0x0);
+}
+
+static int get_rtc_update_in_progress(void)
+{
+ if (cmos_read(RTC_REG_A) & RTC_UIP)
+ return 1;
+ return 0;
+}
+
+static void unsafe_read_cmos_rtc(u8 rtc[7])
+{
+ rtc[0] = cmos_read(RTC_CLK_ALTCENTURY);
+ rtc[1] = cmos_read(RTC_CLK_YEAR);
+ rtc[2] = cmos_read(RTC_CLK_MONTH);
+ rtc[3] = cmos_read(RTC_CLK_DAYOFMONTH);
+ rtc[4] = cmos_read(RTC_CLK_HOUR);
+ rtc[5] = cmos_read(RTC_CLK_MINUTE);
+ rtc[6] = cmos_read(RTC_CLK_SECOND);
+}
+
+static void read_cmos_rtc(u8 rtc[7])
+{
+ /* Read RTC twice and check update-in-progress flag, to make
+ * sure RTC is correct */
+ u8 rtc_old[7], rtc_new[7];
+ while (get_rtc_update_in_progress()) ;
+ unsafe_read_cmos_rtc(rtc_new);
+ do {
+ memcpy(rtc_old, rtc_new, 7);
+ while (get_rtc_update_in_progress()) ;
+ unsafe_read_cmos_rtc(rtc_new);
+ } while (memcmp(rtc_new, rtc_old, 7) != 0);
+}
+
+static u8 convert_bcd_to_bin(u8 bcd)
+{
+ u8 h, l;
+ h = bcd >> 4;
+ l = bcd & 0xf;
+ if (h > 9 || l > 9)
+ return 255;
+ return h * 10 + l;
+}
+
+static void fix_cmos_rtc_time(void)
+{
+ /* Read RTC data. */
+ u8 rtc[7];
+ read_cmos_rtc(rtc);
+
+ /* Convert RTC from BCD format to binary. */
+ u8 bin_rtc[7];
+ int i;
+ for (i = 0; i < 8; i++) {
+ bin_rtc[i] = convert_bcd_to_bin(rtc[i]);
+ }
+
+ /* If RTC date is invalid, fix it. */
+ if (bin_rtc[0] > 99 || bin_rtc[1] > 99 || bin_rtc[2] > 12 || bin_rtc[3] > 31) {
+ /* Set PC compatible timing mode. */
+ cmos_write(0x26, RTC_REG_A);
+ cmos_write(0x02, RTC_REG_B);
+ /* Now setup a default date 2008/08/08 08:08:08. */
+ cmos_write(0x8, RTC_CLK_SECOND);
+ cmos_write(0x8, RTC_CLK_MINUTE);
+ cmos_write(0x8, RTC_CLK_HOUR);
+ cmos_write(0x6, RTC_CLK_DAYOFWEEK); /* Friday */
+ cmos_write(0x8, RTC_CLK_DAYOFMONTH);
+ cmos_write(0x8, RTC_CLK_MONTH);
+ cmos_write(0x8, RTC_CLK_YEAR);
+ cmos_write(0x20, RTC_CLK_ALTCENTURY);
+ }
+}
+
+static void vortex86_sb_set_io_resv(device_t dev, u32 io_resv_size)
+{
+ struct resource *res;
+ res = new_resource(dev, 1);
+ res->base = 0x0UL;
+ res->size = io_resv_size;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void vortex86_sb_set_spi_flash_size(device_t dev, u32 flash_size)
+{
+ /* SPI flash is in topmost of 4G memory space */
+ struct resource *res;
+ res = new_resource(dev, 2);
+ res->base = 0x100000000LL - flash_size;
+ res->size = flash_size;
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void vortex86_sb_read_resources(device_t dev)
+{
+ u32 flash_size = 8 * 1024 * 1024;
+
+ pci_dev_read_resources(dev);
+
+ if (dev->device == 0x6011) {
+ /* It is EX CPU southbridge */
+ if (get_pci_dev_func(dev) != 0) {
+ /* only for function 0, skip function 1 */
+ return;
+ }
+ /* default SPI flash ROM is 64MB */
+ flash_size = 64 * 1024 * 1024;
+ }
+
+ /* Reserve space for I/O */
+ vortex86_sb_set_io_resv(dev, 0x1000UL);
+
+ /* Reserve space for flash */
+ vortex86_sb_set_spi_flash_size(dev, flash_size);
+}
+
+static void southbridge_init(struct device *dev)
+{
+ if (dev->device == 0x6011) {
+ /* It is EX CPU southbridge */
+ if (get_pci_dev_func(dev) != 0) {
+ /* only for function 0, skip function 1 */
+ return;
+ }
+ }
+ upload_dmp_keyboard_firmware(dev);
+ vortex_sb_init(dev);
+ if (dev->device == 0x6011) {
+ ex_sb_gpio_init(dev);
+ ex_sb_uart_init(dev);
+ }
+ pci_routing_fixup(dev);
+
+ fix_cmos_rtc_time();
+ rtc_init(0);
+}
+
+static struct device_operations vortex_sb_ops = {
+ .read_resources = vortex86_sb_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = &southbridge_init,
+ .scan_bus = scan_static_bus,
+ .enable = 0,
+ .ops_pci = 0,
+};
+
+static const struct pci_driver pci_driver_6031 __pci_driver = {
+ .ops = &vortex_sb_ops,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device = 0x6031, /* DX CPU S/B ID */
+};
+
+static const struct pci_driver pci_driver_6011 __pci_driver = {
+ .ops = &vortex_sb_ops,
+ .vendor = PCI_VENDOR_ID_RDC,
+ .device = 0x6011, /* EX CPU S/B ID */
+};
+
+struct chip_operations southbridge_dmp_vortex86ex_ops = {
+ CHIP_NAME("DMP Vortex86EX Southbridge")
+ .enable_dev = 0
+};
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h
new file mode 100644
index 0000000..0d95407
--- /dev/null
+++ b/src/southbridge/dmp/vortex86ex/southbridge.h
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 DMP Electronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_DMP_VORTEX86_H
+#define SOUTHBRIDGE_DMP_VORTEX86_H
+
+#define SB PCI_DEV(0, 7, 0)
+#define SB_REG_VID 0x00
+#define SB_REG_DID 0x02
+#define SB_REG_CMD 0x04
+#define SB_REG_STS 0x06
+#define SB_REG_RID 0x08
+#define SB_REG_PI 0x09
+#define SB_REG_HDR 0x0E
+#define SB_REG_SVID 0x2C
+#define SB_REG_SID 0x2E
+#define SB_REG_BSR 0x40
+#define SB_REG_LPCCR 0x41
+#define SB_REG_FRCSCR 0x42
+#define SB_REG_WTC 0x44
+#define SB_REG_GPIO_CNT 0x48
+#define SB_REG_GPIO_DAT 0x4C
+#define SB_REG_SERIRQ_CTRL 0x50
+#define SB_REG_LPC_CNT 0x51
+#define SB_REG_COMP_DEC 0x52
+#define SB_REG_INTUART_CTL 0x53
+#define SB_REG_INTUART_IO 0x54
+#define SB_REG_PIRQ_X_ROUT 0x58
+#define SB_REG_BSCR 0x5C
+#define SB_REG_GPIO_DPBA_1 0x60
+#define SB_REG_GPIO_DPBA_2 0x62
+#define SB_REG_GPIO_DPBA_3 0x64
+#define SB_REG_GPIO_DPBA_4 0x66
+#define SB_REG_GPIO_DPBA_5 0x68
+#define SB_REG_GPIO_DBA 0x6A
+#define SB_REG_GPIO_CNTL 0x6C
+#define SB_REG_RSR 0x6D
+#define SB_REG_RCR 0x6E
+#define SB_REG_LADR 0x70
+#define SB_REG_LADBAR1 0x74
+#define SB_REG_LADBAM1 0x78
+#define SB_REG_LADBAR2 0x7C
+#define SB_REG_LADBAM2 0x80
+#define SB_REG_CS_BASE2 0x88
+#define SB_REG_CS_BASE_MASK2 0x8C
+#define SB_REG_CS_BASE0 0x90
+#define SB_REG_CS_BASE_MASK0 0x94
+#define SB_REG_CS_BASE1 0x98
+#define SB_REG_CS_BASE_MASK1 0x9C
+#define SB_REG_INTUART2_IO 0xA0
+#define SB_REG_INTUART3_IO 0xA4
+#define SB_REG_INTUART4_IO 0xA8
+#define SB_REG_INTUART9_IO 0xAC
+#define SB_REG_IPPCR 0xB0
+#define SB_REG_PIRQ_X_ROUT2 0xB4
+#define SB_REG_OCDCR 0xBC
+#define SB_REG_IPFCR 0xC0
+#define SB_REG_FRWPR 0xC4
+#define SB_REG_IPFCR2 0xC8
+#define SB_REG_IPFCR3 0xCC
+#define SB_REG_STRAP 0xCE
+#define SB_REG_PM_BASE 0xF8
+#define SB_REG_ACPI_CNT 0xFC
+#define SB_REG_SMI_BASE 0x4C
+
+#define WDT1_REG_CNTL 0x68
+#define WDT1_REG_SIGN_SEL 0x69
+#define WDT1_REG_COUNTER0 0x6A
+#define WDT1_REG_COUNTER1 0x6B
+#define WDT1_REG_COUNTER2 0x6C
+#define SYSTEM_CTL_PORT 0x92
+
+#endif /* SOUTHBRIDGE_DMP_VORTEX86_H */
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