[coreboot-gerrit] Patch set updated for coreboot: 52247df usbdebug: Hard-code EHCI controller to use [NOTFORMERGE]
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Jun 16 08:45:08 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3440
-gerrit
commit 52247df1f056a9ba82e7c2af4476abb12c65146a
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Jun 13 13:51:14 2013 +0300
usbdebug: Hard-code EHCI controller to use [NOTFORMERGE]
EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config().
Similar changes take place on other boards. Better solution will be
to read back from RCBA.
Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/samsung/lumpy/Kconfig | 4 ++++
src/southbridge/intel/bd82x6x/Kconfig | 2 +-
src/southbridge/intel/common/usb_debug.c | 22 +++++++++++++++++++++-
3 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index a169726..39ec977 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -39,6 +39,10 @@ config MAX_CPUS
int
default 8
+config USBDEBUG_HCD_INDEX
+ int
+ default 1
+
config VGA_BIOS_FILE
string
default "pci8086,0106.rom"
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 79c812e..d9dd0c0 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -29,7 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_HARD_RESET
- select HAVE_USBDEBUG
+ select HAVE_USBDEBUG_OPTIONS
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index af785d3..e6f98e1 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -28,7 +28,14 @@
simple_device_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
+#if CONFIG_HAVE_USBDEBUG_OPTIONS
+ if (hcd_idx==0)
+ return PCI_DEV(0, 0x1a, 0);
+ else
+ return PCI_DEV(0, 0x1d, 0);
+#else
return PCI_DEV(0, 0x1d, 7);
+#endif
}
/* Required for successful build, but currently empty. */
@@ -39,9 +46,22 @@ void set_debug_port(unsigned int port)
void enable_usbdebug(unsigned int hcd_idx, unsigned int port)
{
- u32 dbgctl;
+ u32 dbgctl, class;
simple_device_t dev = pci_ehci_dbg_dev(hcd_idx);
+ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
+ if (class != PCI_EHCI_CLASSCODE) {
+ /* If we enter here before RCBA programming, EHCI function may
+ * appear with the highest function number instead.
+ */
+ dev |= PCI_DEV(0, 0, 7);
+ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
+ }
+
+ /* Bail out. No console to complain in. */
+ if (class != PCI_EHCI_CLASSCODE)
+ return;
+
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
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