[coreboot-gerrit] Patch set updated for coreboot: 16172a5 lynxpoint: Fix early EHCI BAR programming

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3472

-gerrit

commit 16172a53014b1566a109033b26a03cfec399bdb6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 15 12:30:13 2013 +0300

    lynxpoint: Fix early EHCI BAR programming
    
    LynxPoint LP has only EHCI controller #1.
    Change EHCI #2 to different BAR from EHCI #1.
    
    Even if the ECHI controllers are not to be addressed, it is bad idea
    to set two different devices to claim the same PCI memory cycles.
    
    Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/intel/lynxpoint/early_usb.c | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index ebd5c2c..d71467e 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -34,23 +34,19 @@
  * The BAR will be re-assigned during device
  * enumeration so these are only temporary.
  */
-void enable_usb_bar(void)
+static void enable_usb_bar_on_device(device_t dev, u32 bar)
 {
-	device_t usb0 = PCH_EHCI1_DEV;
-	device_t usb1 = PCH_EHCI2_DEV;
 	u32 cmd;
-
-	/* USB Controller 1 */
-	pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
-			   PCH_EHCI1_TEMP_BAR0);
-	cmd = pci_read_config32(usb0, PCI_COMMAND);
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar);
+	cmd = pci_read_config32(dev, PCI_COMMAND);
 	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config32(usb0, PCI_COMMAND, cmd);
+	pci_write_config32(dev, PCI_COMMAND, cmd);
+}
 
-	/* USB Controller 1 */
-	pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
-			   PCH_EHCI1_TEMP_BAR0);
-	cmd = pci_read_config32(usb1, PCI_COMMAND);
-	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config32(usb1, PCI_COMMAND, cmd);
+void enable_usb_bar(void)
+{
+	enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
+#if !CONFIG_INTEL_LYNXPOINT_LP
+	enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
+#endif
 }