[coreboot-gerrit] New patch to review for coreboot: a0cbb80 intel/i82801gx: Store initial timestamp

[Nico Huber (nico.huber@secunet.com)]

Nico Huber (nico.huber at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3498

-gerrit

commit a0cbb80bec2a0e0f646ba13cb56767450da26e40
Author: Nico Huber <nico.h at gmx.de>
Date:   Tue Jun 18 22:36:34 2013 +0200

    intel/i82801gx: Store initial timestamp
    
    Upgrade the ICH7 bootblock to store an initial timestamp like we do it
    since Sandy Brigde. I've checked the datasheets for the used scratchpad
    registers and grepped for their usage. I'm pretty sure that they aren't
    used on any ICH7 based board (for anything before the usual S3-resume
    indication).
    
    Change-Id: I28a9b90d3e6f6401a8114ecd240554a5dddc0eb5
    Signed-off-by: Nico Huber <nico.h at gmx.de>
---
 src/southbridge/intel/i82801ix/bootblock.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index b352fca..04ab221 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -19,6 +19,17 @@
 
 #include <arch/io.h>
 
+static void store_initial_timestamp(void)
+{
+	/* On i945/ICH7 we have two 32bit scratchpad registers available:
+	 * D0:F0  0xdc (SKPAD)
+	 * D31:F2 0xd0 (SATA SP)
+	 */
+	tsc_t tsc = rdtsc();
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
+
 static void enable_spi_prefetch(void)
 {
         u8 reg8;
@@ -34,6 +45,9 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
+#if CONFIG_COLLECT_TIMESTAMPS
+	store_initial_timestamp();
+#endif
         enable_spi_prefetch();
 }