[coreboot-gerrit] New patch to review for coreboot: dbe1707 bd82x6x: Fix early USB BAR programming (finally?)

[Nico Huber (nico.huber@secunet.com)]

Nico Huber (nico.huber at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3521

-gerrit

commit dbe17077932069dcae486223594b9e809164075e
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon Jun 24 12:39:53 2013 +0200

    bd82x6x: Fix early USB BAR programming (finally?)
    
    The xHCI controller's MMIO space has a length of 64KiB not 4KiB.
    Therefore, setting the xHCI BAR to 0xe8001000 worked the same like
    setting it to 0xe8000000, as bit12 is reserved and ignored. This again
    interfered with the MMIO space of the first EHCI controller and broke
    S3 resume on Ivy Bridge.
    
    AFAIK, the MRC ignores the setting of the xHCI BAR, anyway. So just drop
    these lines.
    
    Change-Id: I8af9c2ba34133f15636a9056fc8880b3b6ab95e0
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/southbridge/intel/bd82x6x/early_usb.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index baf8c4f..ea2bf38 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -26,7 +26,6 @@
 
 #define PCH_EHCI1_TEMP_BAR0 0xe8000000
 #define PCH_EHCI2_TEMP_BAR0 0xe8000400
-#define PCH_XHCI_TEMP_BAR0  0xe8001000
 
 /*
  * Setup USB controller MMIO BAR to prevent the
@@ -39,7 +38,6 @@ void enable_usb_bar(void)
 {
 	device_t usb0 = PCH_EHCI1_DEV;
 	device_t usb1 = PCH_EHCI2_DEV;
-	device_t usb3 = PCH_XHCI_DEV;
 	u32 cmd;
 
 	/* USB Controller 1 */
@@ -55,11 +53,4 @@ void enable_usb_bar(void)
 	cmd = pci_read_config32(usb1, PCI_COMMAND);
 	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 	pci_write_config32(usb1, PCI_COMMAND, cmd);
-
-	/* USB3 Controller */
-	pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
-			   PCH_XHCI_TEMP_BAR0);
-	cmd = pci_read_config32(usb3, PCI_COMMAND);
-	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config32(usb3, PCI_COMMAND, cmd);
 }