[coreboot-gerrit] New patch to review for coreboot: 9ab6a05 AGESA: Eliminate compiler warnings in AMD F15 AGESA and CIMX wrappers

[Bruce Griffith (Bruce.Griffith@se-eng.com)]

Bruce Griffith (Bruce.Griffith at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3526

-gerrit

commit 9ab6a05d2ef4d49c08e9c201922e19d58967a626
Author: Bruce Griffith <Bruce.Griffith at se-eng.com>
Date:   Fri Jun 21 00:52:54 2013 -0600

    AGESA: Eliminate compiler warnings in AMD F15 AGESA and CIMX wrappers
    
    The change is mostly type casts to eliminate compile time warnings.
    Ultimately, this is in preparation for turning on warnings as errors
    for AMD Family 15 server parts.
    
    Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b
    Signed-off-by: Bruce Griffith <Bruce.Griffith at se-eng.com>
---
 src/northbridge/amd/agesa/family15/northbridge.c | 2 +-
 src/northbridge/amd/cimx/rd890/amd.h             | 5 +----
 src/southbridge/amd/cimx/sb700/late.c            | 2 +-
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 6134830..4d9cc3c 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -1060,7 +1060,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 				dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
 
 		for (j = 0; j <= siblings; j++ ) {
-			extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
+			// extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
 			u32 lapicid_start = 0;
 
 			/*
diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h
index 1ceff80..e7a9ca9 100644
--- a/src/northbridge/amd/cimx/rd890/amd.h
+++ b/src/northbridge/amd/cimx/rd890/amd.h
@@ -32,10 +32,7 @@
 // AGESA Types and Definitions
 //
 //
-#ifndef NULL
-  #define NULL 0
-#endif
-
+#include <stddef.h>
 
 #define LAST_ENTRY 0xFFFFFFFF
 #define IOCF8 0xCF8
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index ede9fb3..b259a7b 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -254,7 +254,7 @@ static void sb700_enable(device_t dev)
 				/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
 				/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
-				setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+				setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS));
 #elif (CONFIG_APIC_ID_OFFSET > 0)
 				/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
 				setup_ioapic(ioapic_base, 0);