[coreboot-gerrit] New patch to review for coreboot: 1b94072 beaglebone: Enable the clocks and pins for the configured UART.

Gabe Black (gabeblack@chromium.org) gerrit at coreboot.org
Sun Jun 30 08:49:24 CEST 2013


Gabe Black (gabeblack at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3573

-gerrit

commit 1b940726e0b8eff3d90e2c9a2e7724f0495cdfc3
Author: Gabe Black <gabeblack at chromium.org>
Date:   Sat Jun 29 23:20:14 2013 -0700

    beaglebone: Enable the clocks and pins for the configured UART.
    
    Set up the pinmux to enable the pins and the clocks for whichever UART is
    currently configured.
    
    Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe
    Signed-off-by: Gabe Black <gabeblack at chromium.org>
---
 src/mainboard/ti/beaglebone/bootblock.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c
index fbe73ea..6c7d132 100644
--- a/src/mainboard/ti/beaglebone/bootblock.c
+++ b/src/mainboard/ti/beaglebone/bootblock.c
@@ -21,10 +21,13 @@
 #include <types.h>
 #include <uart.h>
 #include <console/console.h>
+#include <cpu/ti/am335x/pinmux.h>
 
 void bootblock_mainboard_init(void);
 void bootblock_mainboard_init(void)
 {
+	void *uart_clock_ctrl = NULL;
+
 	/* Enable the GPIO module */
 	writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac));
 
@@ -38,6 +41,29 @@ void bootblock_mainboard_init(void)
 	clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21);
 	setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21);
 
+	/* Set up the UART we're going to use */
+	if (CONFIG_CONSOLE_SERIAL_UART0) {
+		am335x_pinmux_uart0();
+		uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4);
+	} else if (CONFIG_CONSOLE_SERIAL_UART1) {
+		am335x_pinmux_uart1();
+		uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c);
+	} else if (CONFIG_CONSOLE_SERIAL_UART2) {
+		am335x_pinmux_uart2();
+		uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70);
+	} else if (CONFIG_CONSOLE_SERIAL_UART3) {
+		am335x_pinmux_uart3();
+		uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74);
+	} else if (CONFIG_CONSOLE_SERIAL_UART4) {
+		am335x_pinmux_uart4();
+		uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78);
+	} else if (CONFIG_CONSOLE_SERIAL_UART5) {
+		am335x_pinmux_uart5();
+		uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38);
+	}
+	if (uart_clock_ctrl)
+		writel(0x2, uart_clock_ctrl);
+
 	/* Start monotonic timer */
 	//rtc_start();
 



More information about the coreboot-gerrit mailing list