[coreboot-gerrit] Patch set updated for coreboot: d5666fb libpayload: add x86 ROM variable MTRR support

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2920

-gerrit

commit d5666fb3b0ee5e8addc621019faa3a3c826898cb
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Mar 26 13:34:37 2013 -0500

    libpayload: add x86 ROM variable MTRR support
    
    On x86, coreboot may allocate a variable range MTRR for enabling caching
    of the system ROM. Add the ability to parse this structure and add the
    result to the sysinfo structure.
    
    Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 payloads/libpayload/arch/x86/coreboot.c       | 21 ++++++++-
 payloads/libpayload/configs/config.fox        | 68 +++++++++++++++++++++++++++
 payloads/libpayload/include/coreboot_tables.h | 12 +++++
 payloads/libpayload/include/sysinfo.h         |  5 ++
 4 files changed, 105 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c
index f4f9b86..03567d9 100644
--- a/payloads/libpayload/arch/x86/coreboot.c
+++ b/payloads/libpayload/arch/x86/coreboot.c
@@ -158,6 +158,12 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
+static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info)
+{
+	struct cb_x86_rom_mtrr *rom_mtrr = ptr;
+	info->x86_rom_var_mtrr_index = rom_mtrr->index;
+}
+
 static void cb_parse_string(unsigned char *ptr, char **info)
 {
 	*info = (char *)((struct cb_string *)ptr)->string;
@@ -281,6 +287,11 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_MRC_CACHE:
 			cb_parse_mrc_cache(ptr, info);
 			break;
+#if CONFIG_ARCH_X86
+		case CB_TAG_X86_ROM_MTRR:
+			cb_parse_x86_rom_var_mtrr(ptr, info);
+			break;
+#endif
 		}
 
 		ptr += rec->size;
@@ -294,7 +305,15 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	int ret;
+
+#if CONFIG_ARCH_X86
+	/* Ensure the variable range MTRR index covering the ROM is set to
+	 * an invalid value. */
+	info->x86_rom_var_mtrr_index = -1;
+#endif
+
+	ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
 
 	if (ret != 1)
 		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
diff --git a/payloads/libpayload/configs/config.fox b/payloads/libpayload/configs/config.fox
new file mode 100644
index 0000000..a5d6087
--- /dev/null
+++ b/payloads/libpayload/configs/config.fox
@@ -0,0 +1,68 @@
+#
+# Automatically generated make config: don't edit
+# libpayload version: 0.2.0
+# Tue Sep  4 17:53:34 2012
+#
+
+#
+# Generic Options
+#
+# CONFIG_EXPERIMENTAL is not set
+# CONFIG_OBSOLETE is not set
+# CONFIG_DEVELOPER is not set
+CONFIG_CHROMEOS=y
+
+#
+# Architecture Options
+#
+CONFIG_ARCH_X86=y
+# CONFIG_ARCH_POWERPC is not set
+# CONFIG_ARCH_ARMV7 is not set
+# CONFIG_MEMMAP_RAM_ONLY is not set
+# CONFIG_MULTIBOOT is not set
+
+#
+# Standard Libraries
+#
+CONFIG_LIBC=y
+# CONFIG_CURSES is not set
+# CONFIG_TINYCURSES is not set
+# CONFIG_PDCURSES is not set
+CONFIG_CBFS=y
+CONFIG_LZMA=y
+
+#
+# Console Options
+#
+CONFIG_SKIP_CONSOLE_INIT=y
+CONFIG_CBMEM_CONSOLE=y
+CONFIG_SERIAL_CONSOLE=y
+CONFIG_SERIAL_IOBASE=0x3f8
+# CONFIG_SERIAL_SET_SPEED is not set
+# CONFIG_SERIAL_ACS_FALLBACK is not set
+CONFIG_VIDEO_CONSOLE=y
+# CONFIG_VGA_VIDEO_CONSOLE is not set
+# CONFIG_GEODELX_VIDEO_CONSOLE is not set
+CONFIG_COREBOOT_VIDEO_CONSOLE=y
+CONFIG_PC_KEYBOARD=y
+CONFIG_PC_KEYBOARD_LAYOUT_US=y
+# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set
+
+#
+# Drivers
+#
+CONFIG_PCI=y
+CONFIG_NVRAM=y
+# CONFIG_RTC_PORT_EXTENDED_VIA is not set
+# CONFIG_SPEAKER is not set
+# CONFIG_STORAGE is not set
+CONFIG_USB=y
+CONFIG_USB_UHCI=y
+CONFIG_USB_OHCI=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_XHCI=y
+CONFIG_USB_HID=y
+CONFIG_USB_HUB=y
+CONFIG_USB_MSC=y
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_ARCH_SPECIFIC_OPTIONS=y
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 38bda55..02c9449 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -217,6 +217,18 @@ struct cb_vboot_handoff {
 	uint32_t vboot_handoff_size;
 };
 
+#define CB_TAG_X86_ROM_MTRR	0x0021
+struct cb_x86_rom_mtrr {
+	uint32_t tag;
+	uint32_t size;
+	/* The variable range MTRR index covering the ROM. If one wants to
+	 * enable caching the ROM, the variable MTRR needs to be set to
+	 * write-protect. To disable the caching after enabling set the
+	 * type to uncacheable. */
+	uint32_t index;
+};
+
+
 #define CB_TAG_CMOS_OPTION_TABLE 0x00c8
 struct cb_cmos_option_table {
 	u32 tag;
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index e05ef9f..fd60dc3 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -99,6 +99,11 @@ struct sysinfo_t {
 	void	*vdat_addr;
 	u32	vdat_size;
 #endif
+
+#ifdef CONFIG_ARCH_X86
+	int x86_rom_var_mtrr_index;
+#endif
+
 	void	*tstamp_table;
 	void	*cbmem_cons;
 	void	*mrc_cache;