[coreboot-gerrit] New patch to review for coreboot: ff40233 armv7: iterate thru all levels when doing dcache ops

[David Hendricks (dhendrix@chromium.org)]

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2945

-gerrit

commit ff402334d6d77559dbb450125f12d7cc77b9a683
Author: David Hendricks <dhendrix at chromium.org>
Date:   Thu Mar 28 18:26:03 2013 -0700

    armv7: iterate thru all levels when doing dcache ops
    
    This makes dcache maintenance functions operate on all levels
    of cache instead of just the current one.
    
    Change-Id: I2708fc7ba6da6740dbdfd733d937e7c943012d62
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/arch/armv7/lib/cache.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/src/arch/armv7/lib/cache.c b/src/arch/armv7/lib/cache.c
index 8709daf..da03a81 100644
--- a/src/arch/armv7/lib/cache.c
+++ b/src/arch/armv7/lib/cache.c
@@ -148,14 +148,39 @@ static void dcache_op_set_way(enum dcache_op op)
 	dsb();
 }
 
+static void dcache_foreach(enum dcache_op op)
+{
+	uint32_t clidr;
+	int level;
+
+	clidr = read_clidr();
+	for (level = 0; level < 7; level++) {
+		unsigned int ctype = (clidr >> (level * 3)) & 0x7;
+		uint32_t csselr;
+
+		switch(ctype) {
+		case 0x2:
+		case 0x3:
+		case 0x4:
+			csselr = level << 1;
+			write_csselr(csselr);
+			dcache_op_set_way(op);
+			break;
+		default:
+			/* no cache, icache only, or reserved */
+			break;
+		}
+	}
+}
+
 void dcache_clean_invalidate_all(void)
 {
-	dcache_op_set_way(OP_DCCISW);
+	dcache_foreach(OP_DCCISW);
 }
 
 void dcache_invalidate_all(void)
 {
-	dcache_op_set_way(OP_DCISW);
+	dcache_foreach(OP_DCISW);
 }
 
 static unsigned int line_bytes(void)