[coreboot-gerrit] New patch to review for coreboot: a02461d armv7: add functions for reading/writing L2CTLR

[David Hendricks (dhendrix@chromium.org)]

David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2948

-gerrit

commit a02461dd7b63936c007cf23f21fa0c0079efd784
Author: David Hendricks <dhendrix at chromium.org>
Date:   Thu Mar 28 19:04:14 2013 -0700

    armv7: add functions for reading/writing L2CTLR
    
    This adds simple accessor functions for reading/writing L2CTLR.
    
    Change-Id: I2768d00d5bb2c43e84741ccead81e529dac9254d
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/arch/armv7/include/arch/cache.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
index f074a3b..3e0ff2e 100644
--- a/src/arch/armv7/include/arch/cache.h
+++ b/src/arch/armv7/include/arch/cache.h
@@ -219,6 +219,25 @@ static inline void write_csselr(uint32_t val)
 	isb();	/* ISB to sync the change to CCSIDR */
 }
 
+/* read L2 control register (L2CTLR) */
+static inline unsigned int read_l2ctlr(void)
+{
+	unsigned int val = 0;
+	asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+	return val;
+}
+
+/* write L2 control register (L2CTLR) */
+static inline void write_l2ctlr(uint32_t val)
+{
+	/*
+	 * Note: L2CTLR can only be written when the L2 memory system
+	 * is idle, ie before the MMU is enabled.
+	 */
+	asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
+	isb();
+}
+
 /* read system control register (SCTLR) */
 static inline unsigned int read_sctlr(void)
 {