[coreboot-gerrit] Patch merged into coreboot/master: bb4e79a x86: add new mtrr implementation

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit bb4e79a332f0a4f79d402c91b61010157d8a7886
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Mar 26 14:09:47 2013 -0500

    x86: add new mtrr implementation
    
    The old MTRR code had issues using too many variable
    MTRRs depending on the physical address space layout dictated
    by the device resources. This new implementation calculates
    the default MTRR type by comparing the number of variable MTRRs
    used for each type. This avoids the need for IORESOURE_UMA_FB
    because in many of those situations setting the default type to WB
    frees up the variable MTTRs to set that space to UC.
    
    Additionally, it removes the need for IORESOURCE_IGNORE_MTRR
    becuase the new mtrr uses the memrange library which does merging
    of resources.
    
    Lastly, the sandybridge gma has its speedup optimization removed
    for the graphics memory by writing a pre-determined MTRR index.
    That will be fixed in an upcoming patch once write-combining support
    is added to the resources.
    
    Slight differences from previous MTRR code:
    - The number of reserved OS MTRRs is not a hard limit. It's now advisory
      as PAT can be used by the OS to setup the regions to the caching
      policy desired.
    - The memory types are calculated once by the first CPU to run the code.
      After that all other CPUs use that value.
    - CONFIG_CACHE_ROM support was dropped. It will be added back in its own
      change.
    
    A pathological case that was previously fixed by changing vendor code
    to adjust the IO hole location looked like the following:
    
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    
    As noted by the output below it's impossible to accomodate those
    ranges even with 10 variable MTRRS. However, because the code
    can select WB as the default MTRR type it can be done in 6 MTRRs:
    
    MTRR: default type WB/UC MTRR counts: 6/14.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2889
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Fri Mar 29 07:06:46 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Mar 29 19:53:43 2013, giving +2
See http://review.coreboot.org/2889 for details.

-gerrit