[coreboot-gerrit] Patch merged into coreboot/master: 5392424 x86: mtrr: optimize hole carving above 4GiB

gerrit at coreboot.org gerrit at coreboot.org
Fri Mar 29 20:12:21 CET 2013


the following patch was just integrated into master:
commit 53924240be1c4ebc57282d7903e82f447ba2eb6b
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Mar 29 11:48:27 2013 -0500

    x86: mtrr: optimize hole carving above 4GiB
    
    There is an optimization that can take place when hole
    carving in ranges above 4GiB. If the range is the last
    range then there is no need to carve UC holes out from
    the larger WB range.
    
    This optimization also has the same assumption of choosing
    WB as the default MTRR type: the OS needs to properly
    handle accessing realloacted MMIO resources with PAT so
    that the MTRR type can be overidden.
    
    Below are results using a combination of options. The
    board this was tested on has 10 variable MTRRs at its
    disposal. It has 4GiB of RAM.
    
    IO hole config #1: hole starts at 0xad800000
    
    No CACHE_ROM and no WRCOMB resources (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 4/6.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
    
    No CACHE_ROM and 1 WRCOMB resource (takes 6 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 6/7.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    CACHE_ROM and no WRCOMB resources (takes 7 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 11/7.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6
    MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6
    MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 6 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    CACHE_ROM and 1 WRCOMB resource (takes 8 MTRRs):
    Previously this combination was impossible without the optimization.
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 12/8.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6
    MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6
    MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 5 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 6 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 7 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    IO hole config #1: hole starts at 0x80000000
    
    No CACHE_ROM and no WRCOMB resources (takes 1 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 1/2.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0
    
    No CACHE_ROM and 1 WRCOMB resource (takes 3 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 4/3.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    CACHE_ROM and no WRCOMB resources (takes 3 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 9/3.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    CACHE_ROM and 1 WRCOMB resource (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 10/4.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 3 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    Change-Id: Ia3195af686c3f0603b21f713cfb2d9075eb02806
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2959
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Fri Mar 29 18:32:35 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Mar 29 20:12:14 2013, giving +2
See http://review.coreboot.org/2959 for details.

-gerrit



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