[coreboot-gerrit] New patch to review for coreboot: 981ac13 lynxpoint: Fix LP clock gating setup for LPC
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri Mar 29 22:10:59 CET 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2973
-gerrit
commit 981ac13690c90a209b91b8c014e091e5209c9eb7
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Fri Mar 22 11:24:45 2013 -0700
lynxpoint: Fix LP clock gating setup for LPC
This bit offset is incorrect and should only be set based
on another bit in a different register.
Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
src/southbridge/intel/lynxpoint/lpc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 079c7ed..f6c64c5 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -461,7 +461,10 @@ static void enable_lp_clock_gating(device_t dev)
RCBA32_OR(0x900, 0x0000031f);
reg32 = RCBA32(CG);
- reg32 |= (1 << 31); // LPC Dynamic
+ if (RCBA32(0x3454) & (1 << 4))
+ reg32 &= ~(1 << 29); // LPC Dynamic
+ else
+ reg32 |= (1 << 29); // LPC Dynamic
reg32 |= (1 << 30); // LP LPC
reg32 |= (1 << 28); // GPIO Dynamic
reg32 |= (1 << 27); // HPET Dynamic
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