[coreboot-gerrit] Patch set updated for coreboot: 0e845c3 Intel BD82x6x: LPC: Unify I/O APIC setup
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Fri May 3 14:27:46 CEST 2013
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3183
-gerrit
commit 0e845c38d0d9d2ae118afe61e4ca1c78af3b2a66
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Fri May 3 12:23:39 2013 +0200
Intel BD82x6x: LPC: Unify I/O APIC setup
Remove local copies of reading and writing I/O APIC registers by
using already available functions.
This change is similar to
commit db4f875a412e6c41f48a86a79b72465f6cd81635
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Jan 31 17:24:12 2012 +0200
IOAPIC: Divide setup_ioapic() in two parts.
Reviewed-on: http://review.coreboot.org/300
and
commit e614353194c712a40aa8444a530b2062876eabe3
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Feb 26 17:24:41 2013 +0200
Unify setting 82801a/b/c/d IOAPIC ID
Reviewed-on: http://review.coreboot.org/2532
and uses `io_apic_read()` and `io_apic_write()` too.
Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/southbridge/intel/bd82x6x/lpc.c | 65 +++++++++++++++++++------------------
1 file changed, 34 insertions(+), 31 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 7bcadc9..181d36c 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -39,43 +39,43 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
-static void pch_enable_apic(struct device *dev)
+/**
+ * Enable ACPI I/O range.
+ *
+ * @param dev PCI device with ACPI and PM BAR's
+ */
+static void i82801gx_enable_acpi(struct device *dev)
+{
+ /* Set ACPI base address (I/O space). */
+ /* pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); // not needed? */
+
+ /* Enable ACPI I/O range decode and ACPI power management. */
+ pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+}
+
+/**
+ * Set miscellanous static southbridge features.
+ *
+ * @param dev PCI device with I/O APIC control registers
+ */
+static void i82801gx_enable_ioapic(struct device *dev)
{
int i;
u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
- volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-
- /* Enable ACPI I/O and power management.
- * Set SCI IRQ to IRQ9
- */
- pci_write_config8(dev, ACPI_CNTL, 0x80);
- *ioapic_index = 0;
- *ioapic_data = (2 << 24);
+ set_ioapic_id(IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- *ioapic_index = 1;
- reg32 = *ioapic_data;
- *ioapic_index = 1;
- *ioapic_data = reg32;
-
- *ioapic_index = 0;
- reg32 = *ioapic_data;
- printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
- if (reg32 != (2 << 24))
- die("APIC Error\n");
-
- printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
- for (i=0; i<3; i++) {
- *ioapic_index = i;
- printk(BIOS_SPEW, " reg 0x%04x:", i);
- reg32 = *ioapic_data;
- printk(BIOS_SPEW, " 0x%08x\n", reg32);
- }
+ reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+ io_apic_write(IO_APIC_ADDR, reg32);
+
+ printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
+ for (i = 0; i < 3; i++)
+ printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
+ io_apic_read(ioapic_base, i));
- *ioapic_index = 3; /* Select Boot Configuration register. */
- *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+ io_apic_write(IO_APIC_ADDR, 0x03, /* Select Boot Configuration register. */
+ 0x01); /* Use Processor System Bus to deliver interrupts. */
}
static void pch_enable_serial_irqs(struct device *dev)
@@ -537,8 +537,11 @@ static void lpc_init(struct device *dev)
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
+ /* ACPI initialization. */
+ pch_enable_acpi(dev);
+
/* IO APIC initialization. */
- pch_enable_apic(dev);
+ pch_enable_ioapic(dev);
pch_enable_serial_irqs(dev);
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