[coreboot-gerrit] Patch merged into coreboot/master: 703aa97 x86: harden tsc udelay() function
gerrit at coreboot.org
gerrit at coreboot.org
Tue May 7 22:53:09 CEST 2013
the following patch was just integrated into master:
commit 703aa978aa6db915fbc7fa42e5ca79cf31f57505
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed May 1 15:55:14 2013 -0500
x86: harden tsc udelay() function
Since the TSC udelay() function can be used in SMM that means the
TSC can count up to whatever value. The current loop was not handling
TSC rollover properly. In most cases this should not matter as the TSC
typically starts ticking at value 0, and it would take a very long time
to roll it over. However, it is my understanding that this behavior is
not guaranteed. Theoretically the TSC could start or be be written to
with a large value that would cause the rollover.
Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: http://review.coreboot.org/3171
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Build-Tested: build bot (Jenkins) at Tue May 7 22:25:15 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Tue May 7 20:02:01 2013, giving +2
See http://review.coreboot.org/3171 for details.
-gerrit
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