[coreboot-gerrit] New patch to review for coreboot: 2020dcf slippy: Add SPD data for on-board memory

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4154

-gerrit

commit 2020dcf5c8abe91849c7179384cfbef5c3e3efdb
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu May 2 10:40:49 2013 -0700

    slippy: Add SPD data for on-board memory
    
    Change-Id: I7a617fe06d23b906f718ed30f1378f7d220b2799
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49911
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/slippy/Makefile.inc           | 21 +++++++++++++
 .../google/slippy/Micron_MT41K256M16HA.spd.hex     | 17 +++++++++++
 src/mainboard/google/slippy/romstage.c             | 34 +++++++++++++++++++++-
 3 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc
index 92256e8..1b80e6b 100644
--- a/src/mainboard/google/slippy/Makefile.inc
+++ b/src/mainboard/google/slippy/Makefile.inc
@@ -23,3 +23,24 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = Micron_MT41K256M16HA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $^; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do echo -e -n "\\x$$c"; \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab
+spd.bin-position := 0xfffec000
diff --git a/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex b/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex
new file mode 100644
index 0000000..a310e17
--- /dev/null
+++ b/src/mainboard/google/slippy/Micron_MT41K256M16HA.spd.hex
@@ -0,0 +1,17 @@
+# Micron MT41K256M16HA-125 DDR3L-1600
+92 11 0B 03 04 19 00 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 06 F2
+34 4A 54 46 32 35 36 36 20 34 48 5A 2D 31 47 36
+45 31 45 31 80 2C 00 00 00 00 00 00 00 00 01 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index e44e485..a02a84d 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -21,6 +21,8 @@
 #include <delay.h>
 #include <stdint.h>
 #include <stdlib.h>
+#include <string.h>
+#include <cbfs.h>
 #include <console/console.h>
 #include "cpu/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/haswell.h"
@@ -73,6 +75,33 @@ const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
+/* Copy SPD data for on-board memory */
+static void copy_spd(struct pei_data *peid)
+{
+	const int gpio_vector[] = {13, 9, 47, -1};
+	int spd_index = get_gpios(gpio_vector);
+	struct cbfs_file *spd_file;
+
+	printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
+	spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
+	if (!spd_file)
+		die("SPD data not found.");
+
+	if (ntohl(spd_file->len) <
+	    ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
+		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+		spd_index = 0;
+	}
+
+	if (spd_file->len < sizeof(peid->spd_data[0]))
+		die("Missing SPD data.");
+
+	memcpy(peid->spd_data[0],
+	       ((char*)CBFS_SUBHEADER(spd_file)) +
+	       spd_index * sizeof(peid->spd_data[0]),
+	       sizeof(peid->spd_data[0]));
+}
+
 /*
  * Power Sequencing for SanDisk i100/i110 SSD
  *
@@ -124,7 +153,7 @@ void mainboard_romstage_entry(unsigned long bist)
 		temp_mmio_base: 0xfed08000,
 		system_type: 5, /* ULT */
 		tseg_size: CONFIG_SMM_TSEG_SIZE,
-		spd_addresses: { 0xa2, 0x00, 0xa2, 0x00 },
+		spd_addresses: { 0xff, 0x00, 0xff, 0x00 },
 		ec_present: 1,
 		// 0 = leave channel enabled
 		// 1 = disable dimm 0 on channel
@@ -152,6 +181,9 @@ void mainboard_romstage_entry(unsigned long bist)
 		.bist = bist,
 	};
 
+	/* Prepare SPD data */
+	copy_spd(&pei_data);
+
 	/* Call into the real romstage main with this board's attributes. */
 	romstage_common(&romstage_params);