[coreboot-gerrit] Patch set updated for coreboot: c66a1e9 Add DDR refresh config to pei data structure.

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Wed Nov 20 01:50:52 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4213

-gerrit

commit c66a1e943fa38f49ec191c31c96783a27386d8c3
Author: Shawn Nematbakhsh <shawnn at google.com>
Date:   Wed May 8 11:41:04 2013 -0700

    Add DDR refresh config to pei data structure.
    
    Allow platform customized DDR config, including forcing refresh rate to
    2x.
    
    Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2
    Reviewed-on: https://gerrit.chromium.org/gerrit/50476
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn at chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn at chromium.org>
---
 src/northbridge/intel/sandybridge/pei_data.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index d317515..5e0ff0f 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -121,6 +121,14 @@ struct pei_data
 	 * 2 2N
 	 */
 	int nmode;
+	/* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
+	 * for DIMM SPD data to specify whether double-rate is required for
+	 * extended operating temperature range.
+	 * 0 Enable double rate based upon temperature thresholds
+	 * 1 Normal rate
+	 * 2 Always enable double rate
+	 */
+	int ddr_refresh_rate_config;
 } __attribute__((packed));
 
 #endif



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