[coreboot-gerrit] Patch set updated for coreboot: 9e0a26b dmp/vortex86ex: Initialize I2C controller base address/IRQ
Andrew Wu (arw@dmp.com.tw)
gerrit at coreboot.org
Mon Oct 21 15:17:26 CEST 2013
Andrew Wu (arw at dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3976
-gerrit
commit 9e0a26b1d9985011e6bcb400a801b7e533a423ff
Author: Andrew Wu <arw at dmp.com.tw>
Date: Wed Oct 16 13:08:30 2013 +0800
dmp/vortex86ex: Initialize I2C controller base address/IRQ
Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce
Signed-off-by: Andrew Wu <arw at dmp.com.tw>
---
src/mainboard/dmp/vortex86ex/Kconfig | 8 ++++++++
src/southbridge/dmp/vortex86ex/southbridge.c | 12 ++++++++++++
src/southbridge/dmp/vortex86ex/southbridge.h | 1 +
3 files changed, 21 insertions(+)
diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig
index 723a251..f4931ca 100644
--- a/src/mainboard/dmp/vortex86ex/Kconfig
+++ b/src/mainboard/dmp/vortex86ex/Kconfig
@@ -122,6 +122,14 @@ menu "On-Chip Device Power Down Control"
endmenu
+menu "On-Chip Device I/O Base Address Control"
+
+config I2C_BASE
+ hex "I2C base address"
+ default 0xfb00
+
+endmenu
+
menu "Watchdog Timer setting"
config WDT1_INITIALIZE
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index d8914c0..d431c1c 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -70,6 +70,7 @@ static const unsigned char irq_to_int_routing[16] = {
#define PIDE_IRQ 5
#define SPI1_IRQ 10
+#define I2C0_IRQ 10
#define MOTOR_IRQ 11
/* RT0-3 IRQs. */
@@ -418,6 +419,16 @@ static void ex_sb_uart_init(struct device *dev)
//pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0);
}
+static void i2c_init(struct device *dev)
+{
+ u8 mapped_irq = irq_to_int_routing[I2C0_IRQ];
+ u32 cfg = 0;
+ cfg |= 1 << 31; // UE = enabled.
+ cfg |= (mapped_irq << 16); // IIRT0.
+ cfg |= CONFIG_I2C_BASE; // UIOA.
+ pci_write_config32(dev, SB_REG_II2CCR, cfg);
+}
+
static int get_rtc_update_in_progress(void)
{
if (cmos_read(RTC_REG_A) & RTC_UIP)
@@ -566,6 +577,7 @@ static void southbridge_init(struct device *dev)
if (dev->device == 0x6011) {
ex_sb_gpio_init(dev);
ex_sb_uart_init(dev);
+ i2c_init(dev);
}
pci_routing_fixup(dev);
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h
index 0cc28fa..316d30a 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.h
+++ b/src/southbridge/dmp/vortex86ex/southbridge.h
@@ -36,6 +36,7 @@
#define SB_REG_IPFCR 0xc0
#define SB_REG_FRWPR 0xc4
#define SB_REG_STRAP 0xce
+#define SB_REG_II2CCR 0xd4
#define SB1 PCI_DEV(0, 7, 1)
#define SB1_REG_EXT_PIRQ_ROUTE2 0xb4
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