[coreboot-gerrit] New patch to review for coreboot: 7852806 Unify get_top_of_ram and get_cbmem_toc
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Sep 4 15:20:35 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3904
-gerrit
commit 7852806c410bb3605740333ef0d6598696f23925
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Sep 4 01:11:16 2013 +0300
Unify get_top_of_ram and get_cbmem_toc
Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/boot/Makefile.inc | 2 ++
src/arch/x86/boot/ramtop.c | 8 +++++++-
src/include/cbmem.h | 3 ++-
src/mainboard/emulation/qemu-i440fx/memory.c | 8 +-------
src/northbridge/amd/lx/northbridge.h | 1 -
src/northbridge/amd/lx/northbridgeinit.c | 2 +-
src/northbridge/intel/e7505/raminit.h | 1 -
src/northbridge/intel/gm45/gm45.h | 1 -
src/northbridge/intel/gm45/ram_calc.c | 2 +-
src/northbridge/intel/haswell/raminit.h | 1 -
src/northbridge/intel/i945/raminit.c | 5 -----
src/northbridge/intel/i945/raminit.h | 1 -
src/northbridge/intel/sandybridge/northbridge.c | 10 +---------
src/northbridge/intel/sandybridge/raminit.c | 5 -----
src/northbridge/intel/sandybridge/raminit.h | 1 -
src/northbridge/via/vx900/early_vx900.c | 5 -----
src/northbridge/via/vx900/early_vx900.h | 1 -
17 files changed, 15 insertions(+), 42 deletions(-)
diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc
index 6778ad8..89faabe 100644
--- a/src/arch/x86/boot/Makefile.inc
+++ b/src/arch/x86/boot/Makefile.inc
@@ -1,3 +1,5 @@
+romstage-y += ramtop.c
+
ramstage-y += boot.c
ramstage-$(CONFIG_MULTIBOOT) += multiboot.c
ramstage-y += gdt.c
diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c
index 7ac2ee2..fbd98a3 100644
--- a/src/arch/x86/boot/ramtop.c
+++ b/src/arch/x86/boot/ramtop.c
@@ -18,7 +18,13 @@
#include <console/console.h>
#include <cbmem.h>
-#if !CONFIG_DYNAMIC_CBMEM
+unsigned long __attribute__((weak)) get_top_of_ram(void)
+{
+ printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n");
+ return 0;
+}
+
+#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__)
void set_top_of_ram(uint64_t ramtop)
{
set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE);
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 46739de..6517b94 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -143,7 +143,8 @@ void set_cbmem_toc(struct cbmem_entry *);
void cbmem_init(u64 baseaddr, u64 size);
int cbmem_reinit(u64 baseaddr);
-extern struct cbmem_entry *get_cbmem_toc(void);
+unsigned long get_top_of_ram(void);
+struct cbmem_entry *get_cbmem_toc(void);
#endif /* CONFIG_DYNAMIC_CBMEM */
diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c
index 000a0f6..027deb9 100644
--- a/src/mainboard/emulation/qemu-i440fx/memory.c
+++ b/src/mainboard/emulation/qemu-i440fx/memory.c
@@ -40,18 +40,12 @@ static unsigned long qemu_get_memory_size(void)
return tomk;
}
-unsigned long get_top_of_ram(void);
unsigned long get_top_of_ram(void)
{
return qemu_get_memory_size() * 1024;
}
-#if !CONFIG_DYNAMIC_CBMEM
-struct cbmem_entry *get_cbmem_toc(void)
-{
- return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-#else
+#if CONFIG_DYNAMIC_CBMEM
void *cbmem_top(void)
{
/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
index fd62184..25075bd 100644
--- a/src/northbridge/amd/lx/northbridge.h
+++ b/src/northbridge/amd/lx/northbridge.h
@@ -28,7 +28,6 @@ int sizeram(void);
/* northbridgeinit.c */
void northbridge_init_early(void);
-uint32_t get_top_of_ram(void);
/* pll_reset.c */
unsigned int GeodeLinkSpeed(void);
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 3768777..ba9db2b 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -713,7 +713,7 @@ static void setup_lx_cache(void)
wbinvd();
}
-uint32_t get_top_of_ram(void)
+unsigned long get_top_of_ram(void)
{
struct gliutable *gl = 0;
uint32_t systop;
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h
index f9ba796..8eb4990 100644
--- a/src/northbridge/intel/e7505/raminit.h
+++ b/src/northbridge/intel/e7505/raminit.h
@@ -20,7 +20,6 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr);
void e7505_mch_done(const struct mem_controller *memctrl);
int e7505_mch_is_ready(void);
-unsigned long get_top_of_ram(void);
/* Mainboard exports this. */
int spd_read_byte(unsigned device, unsigned address);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 2dffcad..227baef 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -422,7 +422,6 @@ void gm45_late_init(stepping_t);
u32 decode_igd_memory_size(u32 gms);
u32 decode_igd_gtt_size(u32 gsm);
-u32 get_top_of_ram(void);
void init_iommu(void);
#endif
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 28e947b..5585822 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -83,7 +83,7 @@ u32 decode_igd_gtt_size(const u32 gsm)
}
}
-u32 get_top_of_ram(void)
+unsigned long get_top_of_ram(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0, 0);
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 46be570..706c286 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -23,7 +23,6 @@
#include "pei_data.h"
void sdram_initialize(struct pei_data *pei_data);
-unsigned long get_top_of_ram(void);
int fixup_haswell_errata(void);
/* save_mrc_data() must be called after cbmem has been initialized. */
void save_mrc_data(struct pei_data *pei_data);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b1a0684..b50f1d8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -28,11 +28,6 @@
#include "i945.h"
#include <cbmem.h>
-struct cbmem_entry *get_cbmem_toc(void)
-{
- return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 2d8ef9e..9eb4193 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -69,7 +69,6 @@ struct sys_info {
void receive_enable_adjust(struct sys_info *sysinfo);
void sdram_initialize(int boot_path, const u8 *sdram_addresses);
-unsigned long get_top_of_ram(void);
int fixup_i945_errata(void);
void udelay(u32 us);
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 4cd86cd..a03b8a6 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -51,21 +51,13 @@ int bridge_silicon_revision(void)
return bridge_revision_id;
}
-static unsigned long get_top_of_ram(void)
+unsigned long get_top_of_ram(void)
{
/* Base of TSEG is top of usable DRAM */
u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG);
return (unsigned long) tom;
}
-struct cbmem_entry *get_cbmem_toc(void)
-{
- static struct cbmem_entry *toc = NULL;
- if (!toc)
- toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
- return toc;
-}
-
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 3eb2fb3..3b321d7 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data)
save_mrc_data(pei_data);
}
-struct cbmem_entry *get_cbmem_toc(void)
-{
- return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-
unsigned long get_top_of_ram(void)
{
/* Base of TSEG is top of usable DRAM */
diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h
index 23bdbd9..2e9b1f3 100644
--- a/src/northbridge/intel/sandybridge/raminit.h
+++ b/src/northbridge/intel/sandybridge/raminit.h
@@ -30,7 +30,6 @@ struct sys_info {
} __attribute__ ((packed));
void sdram_initialize(struct pei_data *pei_data);
-unsigned long get_top_of_ram(void);
int fixup_sandybridge_errata(void);
#endif /* RAMINIT_H */
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index 2439c8d..2896680 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void)
return (((unsigned long)reg_tom) << 24) - (256 << 20);
}
-struct cbmem_entry *get_cbmem_toc(void)
-{
- return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
-}
-
/**
* \brief Enable accessing of PCI configuration space for all devices.
*
diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h
index dcb24b5..46e3023 100644
--- a/src/northbridge/via/vx900/early_vx900.h
+++ b/src/northbridge/via/vx900/early_vx900.h
@@ -61,7 +61,6 @@
#define RAMINIT_USE_HW_RXCR_CALIB 0
#define RAMINIT_USE_HW_MRS_SEQ 0
-unsigned long get_top_of_ram(void);
void enable_smbus(void);
void dump_spd_data(spd_raw_data spd);
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