[coreboot-gerrit] New patch to review for coreboot: fa1773b qemu: q35: fix pci bar placement

Gerd Hoffmann (kraxel@redhat.com) gerrit at coreboot.org
Tue Sep 17 11:08:10 CEST 2013


Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3927

-gerrit

commit fa1773beb5aecf08d000c6385d20bf1e72ab3557
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Tue Sep 17 10:35:43 2013 +0200

    qemu: q35: fix pci bar placement
    
    Without this coreboot may (depends on the amount of memory) place the
    pci bars below 0xb0000000, then the linux kernel goes move them around
    so they are inside the window declared in the acpi tables.
    
    This breaks vesafb as the vga framebuffer gets moved after vgabios
    initialization.  It's also not exactly nice to expect the OS fix our
    mess ;)
    
    Change-Id: If6b50ea863958eea71b567ccb7a06c6a28076111
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
 src/mainboard/emulation/qemu-i440fx/northbridge.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index a2cd37b..c878689 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -54,6 +54,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 {
 	u16 nbid   = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID);
 	int i440fx = (nbid == 0x1237);
+	int q35    = (nbid == 0x29c0);
 	struct resource *res;
 	unsigned long tomk = 0, high;
 	int idx = 10;
@@ -89,6 +90,21 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 	set_top_of_ram(tomk * 1024);
 #endif
 
+	if (q35 && ((tomk * 1024) < 0xb0000000)) {
+		/*
+		 * Reserve the region between top-of-ram and the
+		 * mmconf xbar (ar 0xb0000000), so coreboot doesn't
+		 * place pci bars there.  The region isn't declared as
+		 * pci io window in the acpi tables (\_SB.PCI0._CRS).
+		 */
+		res = new_resource(dev, idx++);
+		res->base = tomk * 1024;
+		res->size = 0xb0000000 - tomk * 1024;
+		res->limit = 0xffffffff;
+		res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+			IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
 	if (i440fx) {
 		/* Reserve space for the IOAPIC.  This should be in
 		 * the southbridge, but I couldn't tell which device



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