[coreboot-gerrit] Patch set updated for coreboot: f19e24e superio/intel/i3100: Avoid .c includes

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Sun Apr 6 12:28:45 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438

-gerrit

commit f19e24e4338414f203be9662234c59070a697001
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Mon Mar 31 21:30:11 2014 +1100

    superio/intel/i3100: Avoid .c includes
    
    Following the same reasoning as commit
    d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid
    .c includes
    
    Note that these three Intel boards are ROMCC and so we can not clean up
    the early_serial #include directives in these particular
    mainboard/romstage's. However we fix here the superio so that other
    boards that are not ROMCC do not include early_serial.c
    
    Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/intel/eagleheights/romstage.c | 1 +
 src/mainboard/intel/mtarvon/romstage.c      | 2 +-
 src/mainboard/intel/truxton/romstage.c      | 2 +-
 src/superio/intel/i3100/Makefile.inc        | 2 +-
 src/superio/intel/i3100/early_serial.c      | 5 +++--
 src/superio/intel/i3100/i3100.h             | 7 ++++++-
 6 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 3aeb71c..dbe824b 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -33,6 +33,7 @@
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "southbridge/intel/i3100/reset.c"
+#include <superio/intel/i3100/i3100.h>
 #include "superio/intel/i3100/early_serial.c"
 #include "superio/smsc/smscsuperio/early_serial.c"
 #include "northbridge/intel/i3100/i3100.h"
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 0cab9bd..7d01dd3 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -29,7 +29,7 @@
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"
-#include "superio/intel/i3100/i3100.h"
+#include <superio/intel/i3100/i3100.h>
 #include "superio/intel/i3100/early_serial.c"
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 71c5f38..fe8ab2f 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -30,9 +30,9 @@
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
-#include "superio/intel/i3100/i3100.h"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
+#include <superio/intel/i3100/i3100.h>
 #include "superio/intel/i3100/early_serial.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc
index bc3329e..2284398 100644
--- a/src/superio/intel/i3100/Makefile.inc
+++ b/src/superio/intel/i3100/Makefile.inc
@@ -18,5 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c
-
diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c
index f95cf8a..a7376b7 100644
--- a/src/superio/intel/i3100/early_serial.c
+++ b/src/superio/intel/i3100/early_serial.c
@@ -19,6 +19,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pnp.h>
 #include "i3100.h"
 
 static void pnp_enter_ext_func_mode(device_t dev)
@@ -38,14 +39,14 @@ static void pnp_exit_ext_func_mode(device_t dev)
 }
 
 /* Enable device interrupts, set UART_CLK predivide. */
-static void i3100_configure_uart_clk(device_t dev, u8 predivide)
+void i3100_configure_uart_clk(device_t dev, u8 predivide)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);
 	pnp_exit_ext_func_mode(dev);
 }
 
-static void i3100_enable_serial(device_t dev, u16 iobase)
+void i3100_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);
diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h
index 4b8bf27..41f2c21 100644
--- a/src/superio/intel/i3100/i3100.h
+++ b/src/superio/intel/i3100/i3100.h
@@ -61,4 +61,9 @@
 #define I3100_UART_CLK_PREDIVIDE_8	0x01
 #define I3100_UART_CLK_PREDIVIDE_26	0x02
 
-#endif
+// XXX: We leave these commented out until ROMCC boards are EOL'ed..
+//void i3100_configure_uart_clk(device_t dev, u8 predivide);
+
+//void i3100_enable_serial(device_t dev, u16 iobase);
+
+#endif /* SUPERIO_INTEL_I3100_I3100_H */



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