[coreboot-gerrit] Patch set updated for coreboot: 89d34b8 OxPCIe uart: Move under drivers/uart

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Mon Apr 7 05:41:38 CEST 2014


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5329

-gerrit

commit 89d34b881b3da13ccd2657f2681c9e1928da6834
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Feb 28 15:15:12 2014 +0200

    OxPCIe uart: Move under drivers/uart
    
    This driver is only a thin shell for uart8250mem and we could extend it
    with further compatible PCI IDs from other vendors/brands.
    
    Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/drivers/Kconfig                      |   1 -
 src/drivers/Makefile.inc                 |   1 -
 src/drivers/oxford/Kconfig               |   1 -
 src/drivers/oxford/Makefile.inc          |   1 -
 src/drivers/oxford/oxpcie/Kconfig        |  10 ---
 src/drivers/oxford/oxpcie/Makefile.inc   |   4 --
 src/drivers/oxford/oxpcie/oxpcie.c       |  73 --------------------
 src/drivers/oxford/oxpcie/oxpcie_early.c | 111 -------------------------------
 src/drivers/uart/Kconfig                 |  11 +++
 src/drivers/uart/Makefile.inc            |   5 ++
 src/drivers/uart/oxpcie.c                |  73 ++++++++++++++++++++
 src/drivers/uart/oxpcie_early.c          | 111 +++++++++++++++++++++++++++++++
 12 files changed, 200 insertions(+), 202 deletions(-)

diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 5267ff8..1a5f8ff 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -27,7 +27,6 @@ source src/drivers/ics/Kconfig
 source src/drivers/intel/Kconfig
 source src/drivers/ipmi/Kconfig
 source src/drivers/maxim/Kconfig
-source src/drivers/oxford/Kconfig
 source src/drivers/parade/Kconfig
 if PC80_SYSTEM
 source src/drivers/pc80/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 148e257..f11e4b8 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -25,7 +25,6 @@ subdirs-y += i2c
 subdirs-y += intel
 subdirs-y += maxim
 subdirs-y += net
-subdirs-y += oxford
 subdirs-y += parade
 subdirs-y += realtek
 subdirs-y += sil
diff --git a/src/drivers/oxford/Kconfig b/src/drivers/oxford/Kconfig
deleted file mode 100644
index cd7c27c..0000000
--- a/src/drivers/oxford/Kconfig
+++ /dev/null
@@ -1 +0,0 @@
-source src/drivers/oxford/oxpcie/Kconfig
diff --git a/src/drivers/oxford/Makefile.inc b/src/drivers/oxford/Makefile.inc
deleted file mode 100644
index 732face..0000000
--- a/src/drivers/oxford/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-subdirs-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie
diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig
deleted file mode 100644
index c2ea7b6..0000000
--- a/src/drivers/oxford/oxpcie/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-config DRIVERS_OXFORD_OXPCIE
-	bool "Oxford OXPCIe952"
-	default n
-	depends on PCI
-	select DRIVERS_UART_8250MEM
-	select EARLY_PCI_BRIDGE
-	help
-	  Support for Oxford OXPCIe952 serial port PCIe cards.
-	  Currently only devices with the vendor ID 0x1415 and device ID
-	  0xc158 or 0xc11b will work.
diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc
deleted file mode 100644
index 5e3e6e5..0000000
--- a/src/drivers/oxford/oxpcie/Makefile.inc
+++ /dev/null
@@ -1,4 +0,0 @@
-ifeq ($(CONFIG_CONSOLE_SERIAL),y)
-ramstage-y += oxpcie_early.c oxpcie.c
-romstage-y += oxpcie_early.c
-endif
diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
deleted file mode 100644
index 76119d2..0000000
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include <console/uart.h>
-#include <arch/io.h>
-
-static void oxford_oxpcie_enable(device_t dev)
-{
-	printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
-
-	struct resource *res = find_resource(dev, 0x10);
-	if (!res) {
-		printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
-		return;
-	}
-
-	printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
-			(read32(res->base) >> 8), (read32(res->base) & 0xff));
-	printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
-			(read32(res->base + 4) & 3));
-	printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
-}
-
-
-static void oxford_oxpcie_set_resources(struct device *dev)
-{
-	pci_dev_set_resources(dev);
-
-	/* Re-initialize OXPCIe base address after set_resources */
-	u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-	oxford_remap(mmio_base & ~0xf);
-}
-
-static struct device_operations oxford_oxpcie_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = oxford_oxpcie_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = oxford_oxpcie_enable,
-	.scan_bus         = 0,
-};
-
-static const struct pci_driver oxford_oxpcie_driver __pci_driver = {
-	.ops    = &oxford_oxpcie_ops,
-	.vendor = 0x1415,
-	.device = 0xc158,
-};
-
-static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = {
-	.ops    = &oxford_oxpcie_ops,
-	.vendor = 0x1415,
-	.device = 0xc11b,
-};
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
deleted file mode 100644
index b81fa89..0000000
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <arch/io.h>
-#include <arch/early_variables.h>
-#include <boot/coreboot_tables.h>
-#include <console/uart.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-
-static unsigned int oxpcie_present CAR_GLOBAL;
-static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
-static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000;
-
-int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
-{
-	pci_devfn_t device = PCI_DEV(bus, dev, 0);
-
-	u32 id = pci_read_config32(device, PCI_VENDOR_ID);
-	switch (id) {
-	case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
-		/* On this device function 0 is the parallel port, and
-		 * function 3 is the serial port. So let's go look for
-		 * the UART.
-		 */
-		device = PCI_DEV(bus, dev, 3);
-		id = pci_read_config32(device, PCI_VENDOR_ID);
-		if (id != 0xc11b1415)
-			return -1;
-		break;
-	case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */
-	case 0xc1581415: /* e.g. Startech MPEX2S952 */
-		break;
-	default:
-		/* No UART here. */
-		return -1;
-	}
-
-	/* Sanity-check, we assume fixed location. */
-	if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE)
-		return -1;
-
-	/* Setup base address on device */
-	pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
-
-	/* Enable memory on device */
-	u16 reg16 = pci_read_config16(device, PCI_COMMAND);
-	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(device, PCI_COMMAND, reg16);
-
-	car_set_var(oxpcie_present, 1);
-	return 0;
-}
-
-static int oxpcie_uart_active(void)
-{
-	return (car_get_var(oxpcie_present));
-}
-
-unsigned int uart_platform_base(int idx)
-{
-	if (idx == 0 && oxpcie_uart_active())
-		return uart0_base;
-	if (idx == 1 && oxpcie_uart_active())
-		return uart1_base;
-	return 0;
-}
-
-#ifndef __PRE_RAM__
-void oxford_remap(u32 new_base)
-{
-	uart0_base = new_base + 0x1000;
-	uart1_base = new_base + 0x2000;
-}
-
-void uart_fill_lb(void *data)
-{
-	struct lb_serial serial;
-	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
-	serial.baseaddr = uart_platform_base(0);
-	serial.baud = default_baudrate();
-	lb_add_serial(&serial, data);
-
-	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
-}
-#endif
-
-unsigned int uart_platform_refclk(void)
-{
-	return 62500000;
-}
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index 889c69a..a979437 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -21,6 +21,17 @@ config HAVE_UART_SPECIAL
 	bool
 	default n
 
+config DRIVERS_UART_OXPCIE
+	bool "Oxford OXPCIe952"
+	default n
+	depends on PCI
+	select DRIVERS_UART_8250MEM
+	select EARLY_PCI_BRIDGE
+	help
+	  Support for Oxford OXPCIe952 serial port PCIe cards.
+	  Currently only devices with the vendor ID 0x1415 and device ID
+	  0xc158 or 0xc11b will work.
+
 config DRIVERS_UART_PL011
 	bool
 	default n
diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc
index 286bff2..5164282 100644
--- a/src/drivers/uart/Makefile.inc
+++ b/src/drivers/uart/Makefile.inc
@@ -18,6 +18,11 @@ ramstage-y += uart8250mem.c
 smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c
 endif
 
+ifeq ($(CONFIG_DRIVERS_UART_OXPCIE),y)
+ramstage-y += oxpcie_early.c oxpcie.c
+romstage-y += oxpcie_early.c
+endif
+
 ifeq ($(CONFIG_DRIVERS_UART_PL011),y)
 bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c
 romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c
diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c
new file mode 100644
index 0000000..76119d2
--- /dev/null
+++ b/src/drivers/uart/oxpcie.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include <console/uart.h>
+#include <arch/io.h>
+
+static void oxford_oxpcie_enable(device_t dev)
+{
+	printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
+
+	struct resource *res = find_resource(dev, 0x10);
+	if (!res) {
+		printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
+			(read32(res->base) >> 8), (read32(res->base) & 0xff));
+	printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
+			(read32(res->base + 4) & 3));
+	printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
+}
+
+
+static void oxford_oxpcie_set_resources(struct device *dev)
+{
+	pci_dev_set_resources(dev);
+
+	/* Re-initialize OXPCIe base address after set_resources */
+	u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	oxford_remap(mmio_base & ~0xf);
+}
+
+static struct device_operations oxford_oxpcie_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = oxford_oxpcie_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = oxford_oxpcie_enable,
+	.scan_bus         = 0,
+};
+
+static const struct pci_driver oxford_oxpcie_driver __pci_driver = {
+	.ops    = &oxford_oxpcie_ops,
+	.vendor = 0x1415,
+	.device = 0xc158,
+};
+
+static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = {
+	.ops    = &oxford_oxpcie_ops,
+	.vendor = 0x1415,
+	.device = 0xc11b,
+};
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
new file mode 100644
index 0000000..b81fa89
--- /dev/null
+++ b/src/drivers/uart/oxpcie_early.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <stdint.h>
+#include <stddef.h>
+#include <arch/io.h>
+#include <arch/early_variables.h>
+#include <boot/coreboot_tables.h>
+#include <console/uart.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+
+static unsigned int oxpcie_present CAR_GLOBAL;
+static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
+static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000;
+
+int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
+{
+	pci_devfn_t device = PCI_DEV(bus, dev, 0);
+
+	u32 id = pci_read_config32(device, PCI_VENDOR_ID);
+	switch (id) {
+	case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
+		/* On this device function 0 is the parallel port, and
+		 * function 3 is the serial port. So let's go look for
+		 * the UART.
+		 */
+		device = PCI_DEV(bus, dev, 3);
+		id = pci_read_config32(device, PCI_VENDOR_ID);
+		if (id != 0xc11b1415)
+			return -1;
+		break;
+	case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */
+	case 0xc1581415: /* e.g. Startech MPEX2S952 */
+		break;
+	default:
+		/* No UART here. */
+		return -1;
+	}
+
+	/* Sanity-check, we assume fixed location. */
+	if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE)
+		return -1;
+
+	/* Setup base address on device */
+	pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
+
+	/* Enable memory on device */
+	u16 reg16 = pci_read_config16(device, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_MEMORY;
+	pci_write_config16(device, PCI_COMMAND, reg16);
+
+	car_set_var(oxpcie_present, 1);
+	return 0;
+}
+
+static int oxpcie_uart_active(void)
+{
+	return (car_get_var(oxpcie_present));
+}
+
+unsigned int uart_platform_base(int idx)
+{
+	if (idx == 0 && oxpcie_uart_active())
+		return uart0_base;
+	if (idx == 1 && oxpcie_uart_active())
+		return uart1_base;
+	return 0;
+}
+
+#ifndef __PRE_RAM__
+void oxford_remap(u32 new_base)
+{
+	uart0_base = new_base + 0x1000;
+	uart1_base = new_base + 0x2000;
+}
+
+void uart_fill_lb(void *data)
+{
+	struct lb_serial serial;
+	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial.baseaddr = uart_platform_base(0);
+	serial.baud = default_baudrate();
+	lb_add_serial(&serial, data);
+
+	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
+
+unsigned int uart_platform_refclk(void)
+{
+	return 62500000;
+}



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