[coreboot-gerrit] New patch to review for coreboot: 1dbf41a mainboard/intel: EOL old eval kit hw that uses ROMCC

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Tue Apr 8 07:30:52 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5475

-gerrit

commit 1dbf41ade9c8feac1d67c5cf26f69628089d24e4
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Tue Apr 8 15:27:40 2014 +1000

    mainboard/intel: EOL old eval kit hw that uses ROMCC
    
    These Intel boards apears to be old evaluation kits that are now EOL'ed.
    Since they use ROMCC this makes for a good case to drop them from
    bitrot.
    
    Change-Id: I085e6774171d8da6c833ad716ec8ba0fdfc63a50
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/intel/Kconfig                     |   9 -
 src/mainboard/intel/jarrell/Kconfig             |  40 ---
 src/mainboard/intel/jarrell/board_info.txt      |   3 -
 src/mainboard/intel/jarrell/cmos.layout         |  82 ------
 src/mainboard/intel/jarrell/debug.c             | 328 ------------------------
 src/mainboard/intel/jarrell/devicetree.cb       |  80 ------
 src/mainboard/intel/jarrell/irq_tables.c        |  43 ----
 src/mainboard/intel/jarrell/jarrell_fixups.c    | 117 ---------
 src/mainboard/intel/jarrell/mptable.c           | 239 -----------------
 src/mainboard/intel/jarrell/power_reset_check.c |  22 --
 src/mainboard/intel/jarrell/romstage.c          | 109 --------
 src/mainboard/intel/jarrell/watchdog.c          | 139 ----------
 src/mainboard/intel/truxton/Kconfig             |  34 ---
 src/mainboard/intel/truxton/Makefile.inc        |   1 -
 src/mainboard/intel/truxton/board_info.txt      |   2 -
 src/mainboard/intel/truxton/devicetree.cb       |  55 ----
 src/mainboard/intel/truxton/irq_tables.c        |  44 ----
 src/mainboard/intel/truxton/mptable.c           | 140 ----------
 src/mainboard/intel/truxton/romstage.c          |  98 -------
 src/mainboard/intel/xe7501devkit/Kconfig        |  34 ---
 src/mainboard/intel/xe7501devkit/acpi_tables.c  | 137 ----------
 src/mainboard/intel/xe7501devkit/board_info.txt |   1 -
 src/mainboard/intel/xe7501devkit/bus.h          |  16 --
 src/mainboard/intel/xe7501devkit/cmos.layout    |  53 ----
 src/mainboard/intel/xe7501devkit/devicetree.cb  |  73 ------
 src/mainboard/intel/xe7501devkit/dsdt.asl       |  16 --
 src/mainboard/intel/xe7501devkit/ioapic.h       |  11 -
 src/mainboard/intel/xe7501devkit/irq_tables.c   |  74 ------
 src/mainboard/intel/xe7501devkit/mptable.c      | 142 ----------
 src/mainboard/intel/xe7501devkit/romstage.c     |  75 ------
 30 files changed, 2217 deletions(-)

diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 75142e3..9cdd38f 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -13,14 +13,8 @@ config BOARD_INTEL_EAGLEHEIGHTS
 	bool "EagleHeights"
 config BOARD_INTEL_EMERALDLAKE2
 	bool "Emerald Lake 2 CRB"
-config BOARD_INTEL_JARRELL
-	bool "Jarrell (SE7520JR2)"
 config BOARD_INTEL_MTARVON
 	bool "3100 devkit (Mt. Arvon)"
-config BOARD_INTEL_TRUXTON
-	bool "EP80579 devkit (Truxton)"
-config BOARD_INTEL_XE7501DEVKIT
-	bool "XE7501devkit"
 config BOARD_INTEL_BASKING_RIDGE
 	bool "Basking Ridge CRB"
 config BOARD_INTEL_WTM2
@@ -34,10 +28,7 @@ source "src/mainboard/intel/d945gclf/Kconfig"
 source "src/mainboard/intel/eagleheights/Kconfig"
 source "src/mainboard/intel/emeraldlake2/Kconfig"
 source "src/mainboard/intel/baskingridge/Kconfig"
-source "src/mainboard/intel/jarrell/Kconfig"
 source "src/mainboard/intel/mtarvon/Kconfig"
-source "src/mainboard/intel/truxton/Kconfig"
-source "src/mainboard/intel/xe7501devkit/Kconfig"
 source "src/mainboard/intel/wtm2/Kconfig"
 
 config MAINBOARD_VENDOR
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
deleted file mode 100644
index 2a62777..0000000
--- a/src/mainboard/intel/jarrell/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-if BOARD_INTEL_JARRELL
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_X86
-	select CPU_INTEL_SOCKET_MPGA604
-	select NORTHBRIDGE_INTEL_E7520
-	select SOUTHBRIDGE_INTEL_PXHD
-	select SOUTHBRIDGE_INTEL_I82801EX
-	select SUPERIO_NSC_PC87427
-	select ROMCC
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select UDELAY_TSC
-	select USE_WATCHDOG_ON_BOOT
-	select DRIVERS_ATI_RAGEXL
-	select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
-	string
-	default intel/jarrell
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Jarrell"
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
-config DIMM_MAP_LOGICAL
-	hex
-	default 0x0124
-
-endif # BOARD_INTEL_JARRELL
diff --git a/src/mainboard/intel/jarrell/board_info.txt b/src/mainboard/intel/jarrell/board_info.txt
deleted file mode 100644
index e62a179..0000000
--- a/src/mainboard/intel/jarrell/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Board name: Jarrell (SE7520JR2)
-Category: server
-Board URL: http://www.intel.com/support/motherboards/server/se7520jr2/
diff --git a/src/mainboard/intel/jarrell/cmos.layout b/src/mainboard/intel/jarrell/cmos.layout
deleted file mode 100644
index 1f225f8..0000000
--- a/src/mainboard/intel/jarrell/cmos.layout
+++ /dev/null
@@ -1,82 +0,0 @@
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-#96         288       r       0        temporary_filler
-0          376       r       0        reserved_memory
-376          1       e       1        power_up_watchdog
-384          1       e       4        boot_option
-385          1       e       4        last_boot
-386          1       e       1        ECC_memory
-388          4       r       0        reboot_bits
-392          3       e       5        baud_rate
-395          1       e       2        hyper_threading
-397          1       e       1        pxhd_bus_speed_100
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-416          4       e       7        boot_first
-420          4       e       7        boot_second
-424          4       e       7        boot_third
-428          4       h       0        boot_index
-432          8       h       0        boot_countdown
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Network
-7     1     HDD
-7     2     Floppy
-7     8     Fallback_Network
-7     9     Fallback_HDD
-7     10    Fallback_Floppy
-#7     3     ROM
-
-checksums
-
-checksum 392 983 984
-
-
diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c
deleted file mode 100644
index 93199d7..0000000
--- a/src/mainboard/intel/jarrell/debug.c
+++ /dev/null
@@ -1,328 +0,0 @@
-#include <spd.h>
-
-static void print_reg(unsigned char index)
-{
-        unsigned char data;
-
-        outb(index, 0x2e);
-        data = inb(0x2f);
-	print_debug("0x");
-	print_debug_hex8(index);
-	print_debug(": 0x");
-	print_debug_hex8(data);
-	print_debug("\n");
-        return;
-}
-
-static void xbus_en(void)
-{
-        /* select the XBUS function in the SIO */
-        outb(0x07, 0x2e);
-        outb(0x0f, 0x2f);
-        outb(0x30, 0x2e);
-        outb(0x01, 0x2f);
-	return;
-}
-
-static void setup_func(unsigned char func)
-{
-        /* select the function in the SIO */
-        outb(0x07, 0x2e);
-        outb(func, 0x2f);
-        /* print out the regs */
-        print_reg(0x30);
-        print_reg(0x60);
-        print_reg(0x61);
-        print_reg(0x62);
-        print_reg(0x63);
-        print_reg(0x70);
-        print_reg(0x71);
-        print_reg(0x74);
-        print_reg(0x75);
-        return;
-}
-
-static void siodump(void)
-{
-        int i;
-        unsigned char data;
-
-	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
-        for (i=0x10; i<=0x2d; i++) {
-                print_reg((unsigned char)i);
-        }
-#if 0
-        print_debug("\n*** XBUS REGISTERS ***\n");
-        setup_func(0x0f);
-        for (i=0xf0; i<=0xff; i++) {
-                print_reg((unsigned char)i);
-        }
-
-        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
-        setup_func(0x03);
-        print_reg(0xf0);
-
-        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
-        setup_func(0x02);
-        print_reg(0xf0);
-
-#endif
-        print_debug("\n***  GPIO REGISTERS ***\n");
-        setup_func(0x07);
-        for (i=0xf0; i<=0xf8; i++) {
-                print_reg((unsigned char)i);
-        }
-        print_debug("\n***  GPIO VALUES ***\n");
-        data = inb(0x68a);
-	print_debug("\nGPDO 4: 0x");
-	print_debug_hex8(data);
-        data = inb(0x68b);
-	print_debug("\nGPDI 4: 0x");
-	print_debug_hex8(data);
-	print_debug("\n");
-
-#if 0
-
-        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
-        setup_func(0x0a);
-        print_reg(0xf0);
-
-        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
-        setup_func(0x09);
-        print_reg(0xf0);
-        print_reg(0xf1);
-
-        print_debug("\n***  RTC REGISTERS ***\n");
-        setup_func(0x10);
-        print_reg(0xf0);
-        print_reg(0xf1);
-        print_reg(0xf3);
-        print_reg(0xf6);
-        print_reg(0xf7);
-        print_reg(0xfe);
-        print_reg(0xff);
-
-        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
-        setup_func(0x14);
-        print_reg(0xf0);
-#endif
-        return;
-}
-
-static void print_debug_pci_dev(unsigned dev)
-{
-	print_debug("PCI: ");
-	print_debug_hex8((dev >> 16) & 0xff);
-	print_debug_char(':');
-	print_debug_hex8((dev >> 11) & 0x1f);
-	print_debug_char('.');
-	print_debug_hex8((dev >> 8) & 7);
-}
-
-static void print_pci_devices(void)
-{
-	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
-		dev <= PCI_DEV(0, 0x1f, 0x7);
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
-		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
-			continue;
-		}
-		print_debug_pci_dev(dev);
-		print_debug("\n");
-	}
-}
-
-static void dump_pci_device(unsigned dev)
-{
-	int i;
-	print_debug_pci_dev(dev);
-	print_debug("\n");
-
-	for(i = 0; i <= 255; i++) {
-		unsigned char val;
-		if ((i & 0x0f) == 0) {
-			print_debug_hex8(i);
-			print_debug_char(':');
-		}
-		val = pci_read_config8(dev, i);
-		print_debug_char(' ');
-		print_debug_hex8(val);
-		if ((i & 0x0f) == 0x0f) {
-			print_debug("\n");
-		}
-	}
-}
-
-static void dump_bar14(unsigned dev)
-{
-	int i;
-	unsigned long bar;
-
-	print_debug("BAR 14 Dump\n");
-
-	bar = pci_read_config32(dev, 0x14);
-	for(i = 0; i <= 0x300; i+=4) {
-#if 0
-		unsigned char val;
-		if ((i & 0x0f) == 0) {
-			print_debug_hex8(i);
-			print_debug_char(':');
-		}
-		val = pci_read_config8(dev, i);
-#endif
-		if((i%4)==0) {
-		print_debug("\n");
-		print_debug_hex16(i);
-		print_debug_char(' ');
-		}
-		print_debug_hex32(read32(bar + i));
-		print_debug_char(' ');
-	}
-	print_debug("\n");
-}
-
-static void dump_pci_devices(void)
-{
-	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
-		dev <= PCI_DEV(0, 0x1f, 0x7);
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
-		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
-			continue;
-		}
-		dump_pci_device(dev);
-	}
-}
-
-#if 0
-static void dump_spd_registers(const struct mem_controller *ctrl)
-{
-	int i;
-	print_debug("\n");
-	for(i = 0; i < 4; i++) {
-		unsigned device;
-		device = ctrl->channel0[i];
-		if (device) {
-			int j;
-			print_debug("dimm: ");
-			print_debug_hex8(i);
-			print_debug(".0: ");
-			print_debug_hex8(device);
-			for(j = 0; j < 256; j++) {
-				int status;
-				unsigned char byte;
-				if ((j & 0xf) == 0) {
-					print_debug("\n");
-					print_debug_hex8(j);
-					print_debug(": ");
-				}
-				status = smbus_read_byte(device, j);
-				if (status < 0) {
-					print_debug("bad device\n");
-					break;
-				}
-				byte = status & 0xff;
-				print_debug_hex8(byte);
-				print_debug_char(' ');
-			}
-			print_debug("\n");
-		}
-		device = ctrl->channel1[i];
-		if (device) {
-			int j;
-			print_debug("dimm: ");
-			print_debug_hex8(i);
-			print_debug(".1: ");
-			print_debug_hex8(device);
-			for(j = 0; j < 256; j++) {
-				int status;
-				unsigned char byte;
-				if ((j & 0xf) == 0) {
-					print_debug("\n");
-					print_debug_hex8(j);
-					print_debug(": ");
-				}
-				status = smbus_read_byte(device, j);
-				if (status < 0) {
-					print_debug("bad device\n");
-					break;
-				}
-				byte = status & 0xff;
-				print_debug_hex8(byte);
-				print_debug_char(' ');
-			}
-			print_debug("\n");
-		}
-	}
-}
-#endif
-
-void dump_spd_registers(void)
-{
-        unsigned device;
-        device = DIMM0;
-        while(device <= DIMM7) {
-                int status = 0;
-                int i;
-        	print_debug("\n");
-                print_debug("dimm ");
-		print_debug_hex8(device);
-
-                for(i = 0; (i < 256) ; i++) {
-	                unsigned char byte;
-                        if ((i % 16) == 0) {
-				print_debug("\n");
-				print_debug_hex8(i);
-				print_debug(": ");
-                        }
-			status = smbus_read_byte(device, i);
-                        if (status < 0) {
-			         print_debug("bad device: ");
-				 print_debug_hex8(-status);
-				 print_debug("\n");
-			         break;
-			}
-			print_debug_hex8(status);
-			print_debug_char(' ');
-		}
-		device++;
-		print_debug("\n");
-	}
-}
-
-void dump_ipmi_registers(void)
-{
-        unsigned device;
-        device = 0x42;
-        while(device <= 0x42) {
-                int status = 0;
-                int i;
-        	print_debug("\n");
-                print_debug("ipmi ");
-		print_debug_hex8(device);
-
-                for(i = 0; (i < 8) ; i++) {
-	                unsigned char byte;
-			status = smbus_read_byte(device, 2);
-                        if (status < 0) {
-			         print_debug("bad device: ");
-				 print_debug_hex8(-status);
-				 print_debug("\n");
-			         break;
-			}
-			print_debug_hex8(status);
-			print_debug_char(' ');
-		}
-		device++;
-		print_debug("\n");
-	}
-}
diff --git a/src/mainboard/intel/jarrell/devicetree.cb b/src/mainboard/intel/jarrell/devicetree.cb
deleted file mode 100644
index 501bc7e..0000000
--- a/src/mainboard/intel/jarrell/devicetree.cb
+++ /dev/null
@@ -1,80 +0,0 @@
-chip northbridge/intel/e7520
-	device domain 0 on
-		subsystemid 0x8086 0x1079 inherit
-		device pci 00.0 on end
-		device pci 00.1 on end
-		device pci 01.0 on end
-		device pci 02.0 on
-			chip southbridge/intel/pxhd # pxhd1
-				device pci 00.0 on end
-				device pci 00.1 on end
-				device pci 00.2 on
-					chip drivers/generic/generic
-						device pci 04.0 on end
-						device pci 04.1 on end
-					end
-				end
-				device pci 00.3 on end
-			end
-		end
-		device pci 06.0 on end
-		chip southbridge/intel/i82801ex # i82801er
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end
-			device pci 1d.3 off end
-			device pci 1d.7 on end
-			device pci 1e.0 on
-				chip drivers/ati/ragexl
-					device pci 0c.0 on end
-				end
-			end
-			device pci 1f.0 on
-				chip superio/nsc/pc87427
-					device pnp 2e.0 off end
-					device pnp 2e.2 on
-#						 io 0x60 = 0x2f8
-#						irq 0x70 = 3
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-#						 io 0x60 = 0x3f8
-#						irq 0x70 = 4
-						 io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 on
-						 io 0x60 = 0x60
-						 io 0x62 = 0x64
-						irq 0x70 = 1
-					end
-					device pnp 2e.7 off end
-					device pnp 2e.9 off end
-					device pnp 2e.a off end
-					device pnp 2e.f on end
-					device pnp 2e.10 off end
-					device pnp 2e.14 off end
-				end
-			end
-			device pci 1f.1 on end
-			device pci 1f.2 off end
-			device pci 1f.3 on end
-			device pci 1f.5 off end
-			device pci 1f.6 off end
-			register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
-			register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
-			register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
-		end
-	end
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_mPGA604 # cpu 0
-			device lapic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 # cpu 1
-			device lapic 6 on end
-		end
-	end
-end
diff --git a/src/mainboard/intel/jarrell/irq_tables.c b/src/mainboard/intel/jarrell/irq_tables.c
deleted file mode 100644
index 6e88d48..0000000
--- a/src/mainboard/intel/jarrell/irq_tables.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* PCI: Interrupt Routing Table found at 0x40114180 size = 320 */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	0x52495024, /* u32 signature */
-	0x0100,     /* u16 version   */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,        /* u16 Table size 32+(16*devices)  */
-	0x00,       /* u8 Bus 0 */
-	0xf8,       /* u8 Device 1, Function 0 */
-	0x0000,     /* u16 reserve IRQ for PCI */
-	0x8086,     /* u16 Vendor */
-	0x24d0,     /* Device ID */
-	0x00000000, /* u32 miniport_data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x38,   /*  u8 checksum - mod 256 checksum must give zero */
-	{  /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
-	    {0x00, 0x08, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	    {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	    {0x00, 0xe8, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00,  0x00},
-	    {0x02, 0x20, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	    {0x03, 0x28, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	    {0x04, 0x60, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	    {0x02, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x04,  0x00},
-	    {0x02, 0x10, {{0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x05,  0x00},
-	    {0x02, 0x18, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}}, 0x06,  0x00},
-	    {0x03, 0x08, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}}, 0x01,  0x00},
-	    {0x03, 0x10, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x61, 0xdcf8}}, 0x02,  0x00},
-	    {0x03, 0x18, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x61, 0xdcf8}}, 0x03,  0x00},
-	    {0x00, 0x10, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00,  0x00},
-	    {0x00, 0x18, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00,  0x00},
-	    {0x00, 0x20, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00,  0x00},
-	    {0x00, 0x28, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00,  0x00},
-	    {0x00, 0x30, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00,  0x00},
-	    {0x00, 0x38, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdc78}, {0x63, 0xdcf8}}, 0x00,  0x00}
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
-
diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c
deleted file mode 100644
index 9a57746..0000000
--- a/src/mainboard/intel/jarrell/jarrell_fixups.c
+++ /dev/null
@@ -1,117 +0,0 @@
-#include <arch/io.h>
-
-static void mch_reset(void)
-{
-        device_t dev;
-        unsigned long value, base;
-        dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0);
-        if (dev != PCI_DEV_INVALID) {
-                /* I/O space is always enables */
-
-                /* Set gpio base */
-                pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
-                base = ICH5_GPIOBASE;
-
-                /* Enable GPIO Bar */
-                value = pci_read_config32(dev, 0x5c);
-                value |= 0x10;
-                pci_write_config32(dev, 0x5c, value);
-
-		/* Set GPIO 19 mux to IO usage */
-		value = inl(base);
-		value |= (1 <<19);
-		outl(value, base);
-
-                /* Pull GPIO 19 low */
-                value = inl(base + 0x0c);
-                value &= ~(1 << 19);
-                outl(value, base + 0x0c);
-        }
-        return;
-}
-
-static void mainboard_set_e7520_pll(unsigned bits)
-{
-	uint16_t gpio_index;
-	uint8_t data;
-	device_t dev;
-
-	/* currently only handle the Jarrell/PC87427 case */
-	dev = PC87427_GPIO_DEV;
-
-
-	pnp_set_logical_device(dev);
-	gpio_index = pnp_read_iobase(dev, 0x60);
-
-	/* select SIO GPIO port 4, pin 2 */
-	pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x42));
-	/* set to push-pull, enable output */
-	pnp_write_config(dev, PC87427_GPCFG1, 0x03);
-
-	/* select SIO GPIO port 4, pin 4 */
-	pnp_write_config(dev, PC87427_GPSEL, ((pnp_read_config(dev, PC87427_GPSEL) & 0x88) | 0x44));
-	/* set to push-pull, enable output */
-	pnp_write_config(dev, PC87427_GPCFG1, 0x03);
-
-	/* set gpio 42,44 signal levels */
-	data = inb(gpio_index + PC87427_GPDO_4);
-	if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
-		print_debug("set_pllsel: correct settings detected!\n");
-		return; /* settings already configured */
-	} else {
-		outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
-		/* reset */
-		print_debug("set_pllsel: settings adjusted, now resetting...\n");
-		// hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
-		// mch_reset();
-		full_reset();
-	}
-	return;
-}
-
-static void mainboard_set_e7520_leds(void)
-{
-	uint8_t cnt;
-	uint8_t data;
-	device_t dev;
-
-	/* currently only handle the Jarrell/PC87427 case */
-	dev = PC87427_GPIO_DEV;
-
-	pnp_set_logical_device(dev);
-
-	/* enable */
-	outb(0x30, 0x2e);
-	outb(0x01, 0x2f);
-	outb(0x2d, 0x2e);
-	outb(0x01, 0x2f);
-
-	/* Set auto mode for dimm leds and post */
-	outb(0xf0,0x2e);
-	outb(0x70,0x2f);
-	outb(0xf4,0x2e);
-	outb(0x30,0x2f);
-	outb(0xf5,0x2e);
-	outb(0x88,0x2f);
-	outb(0xf6,0x2e);
-	outb(0x00,0x2f);
-	outb(0xf7,0x2e);
-	outb(0x90,0x2f);
-	outb(0xf8,0x2e);
-	outb(0x00,0x2f);
-
-	/* Turn the leds off */
-	outb(0x00,0x88);
-	outb(0x00,0x90);
-
-	/* Disable the ports */
-	outb(0xf5,0x2e);
-	outb(0x00,0x2f);
-	outb(0xf7,0x2e);
-	outb(0x00,0x2f);
-	outb(0xf4,0x2e);
-	outb(0x00,0x2f);
-
-	return;
-}
-
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
deleted file mode 100644
index 6662329..0000000
--- a/src/mainboard/intel/jarrell/mptable.c
+++ /dev/null
@@ -1,239 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	unsigned char bus_pxhd_1;
-	unsigned char bus_pxhd_2;
-	unsigned char bus_pxhd_3 = 0;
-	unsigned char bus_pxhd_4 = 0;
-	unsigned char bus_pxhd_x = 0;
-	unsigned char bus_ich5r_1;
-	unsigned int bus_pxhd_id;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	{
-		device_t dev;
-
-		/* ich5r */
-		dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
-		if (dev) {
-			bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		}
-		else {
-			printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n");
-
-			bus_ich5r_1 = 4;
-		}
-		/* pxhd-1 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
-		if (dev) {
-			bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
-			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
-
-			bus_pxhd_1 = 2;
-		}
-		/* pxhd-2 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
-		if (dev) {
-			bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-		}
-		else {
-			printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
-			bus_pxhd_2 = 3;
-		}
-		/* test for active riser with 2nd pxh device */
-		dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
-                if (dev) {
-			bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
-			if(bus_pxhd_id == 0x35998086) {
-				bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS);
-				/* pxhd-3 */
-				dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x0,0));
-				if (dev) {
-					bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
-					if(bus_pxhd_id == 0x03298086) {
-					    bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-					}
-				}
-				/* pxhd-4 */
-				dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2));
-				if (dev) {
-					bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID);
-                                        if(bus_pxhd_id == 0x032a8086) {
-					    bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-					}
-				}
-			}
-		}
-	}
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* IOAPIC handling */
-
-	smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
-	{
-		struct resource *res;
-		device_t dev;
-		/* pxhd apic 3 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 0x09, 0x20, res->base);
-			}
-		}
-		else {
-			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
-		}
-		/* pxhd apic 4 */
-		dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
-		if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, 0x0a, 0x20, res->base);
-			}
-		}
-		else {
-			printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
-		}
-
-		/* pxhd apic 5 */
-		if(bus_pxhd_3) { /* Active riser pxhd */
-			dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
-			if (dev) {
-				res = find_resource(dev, PCI_BASE_ADDRESS_0);
-				if (res) {
-					smp_write_ioapic(mc, 0x0b, 0x20, res->base);
-				}
-			}
-			else {
-				printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.1\n",bus_pxhd_x);
-			}
-		}
-		/* pxhd apic 6 */
-		if(bus_pxhd_4) { /* active riser pxhd */
-			dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,3));
-			if (dev) {
-				res = find_resource(dev, PCI_BASE_ADDRESS_0);
-				if (res) {
-					smp_write_ioapic(mc, 0x0c, 0x20, res->base);
-				}
-			}
-			else {
-				printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI %d:00.3\n",bus_pxhd_x);
-			}
-		}
-	}
-
-	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
-
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x0a, 0x08, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x0b, 0x08, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x0a, 0x08, 0x10);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x07, 0x08, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x0b, 0x08, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x05, 0x08, 0x17);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x0b, 0x08, 0x12);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x07, 0x08, 0x13);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x0b, 0x08, 0x11);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-		bus_isa, 0x0a, 0x08, 0x10);
-
-	/* Standard local interrupt assignments */
-	mptable_lintsrc(mc, bus_isa);
-
-	/* FIXME verify I have the irqs handled for all of the risers */
-
-	/* 2:3.0 PCI Slot 1 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_1, (3<<2)|0, 0x9, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_1, (3<<2)|1, 0x9, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_1, (3<<2)|2, 0x9, 0x5);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_1, (3<<2)|3, 0x9, 0x4);
-
-
-	/* 3:7.0 PCI Slot 2 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_2, (7<<2)|0, 0xa, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_2, (7<<2)|1, 0xa, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_2, (7<<2)|2, 0xa, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_2, (7<<2)|3, 0xa, 0x1);
-
-	/* PCI Slot 3 (if active riser) */
-	if(bus_pxhd_3) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-	                bus_pxhd_3, (1<<2)|0, 0xb, 0x0);
-	}
-
-	/* PCI Slot 4 (if active riser) */
-	if(bus_pxhd_4) {
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-	                bus_pxhd_4, (1<<2)|0, 0xc, 0x0);
-	}
-
-	/* Onboard SCSI 0 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_1, (5<<2)|0, 0x9, 0x2);
-
-	/* Onboard SCSI 1 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_1, (5<<2)|1, 0x9, 0x1);
-
-	/* Onboard NIC 0 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_2, (4<<2)|0, 0xa, 0x6);
-
-	/* Onboard NIC 1 */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		bus_pxhd_2, (4<<2)|1, 0xa, 0x7);
-
-	/* Onboard VGA */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-		 bus_ich5r_1, (12<<2)|0, 0x8, 0x11);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
-
diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c
deleted file mode 100644
index 0ac526f..0000000
--- a/src/mainboard/intel/jarrell/power_reset_check.c
+++ /dev/null
@@ -1,22 +0,0 @@
-void full_reset(void)
-{
-	/* Enable power on after power fail... */
-	unsigned byte;
-	byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	byte &= 0xfe;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
-
-	outb(0x0e, 0xcf9);
-}
-
-static void power_down_reset_check(void)
-{
-	uint8_t cmos;
-
-	cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
-	print_debug("Boot byte = ");
-	print_debug_hex8(cmos);
-	print_debug("\n");
-
-	if((cmos>2)&&(cmos&1))  full_reset();
-}
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
deleted file mode 100644
index bddb34a..0000000
--- a/src/mainboard/intel/jarrell/romstage.c
+++ /dev/null
@@ -1,109 +0,0 @@
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include "southbridge/intel/i82801ex/early_smbus.c"
-#include "northbridge/intel/e7520/raminit.h"
-#include "superio/nsc/pc87427/pc87427.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "watchdog.c"
-#include "southbridge/intel/i82801ex/reset.c"
-#include "power_reset_check.c"
-#include "jarrell_fixups.c"
-#include "superio/nsc/pc87427/early_init.c"
-#include "northbridge/intel/e7520/memory_initialized.c"
-#include "cpu/x86/bist.h"
-#include <spd.h>
-
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
-#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
-#define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
-
-#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
-#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/e7520/raminit.c"
-#include "lib/generic_sdram.c"
-#include "debug.c"
-#include "arch/x86/lib/stages.c"
-
-static void main(unsigned long bist)
-{
-	static const struct mem_controller mch[] = {
-		{
-			.node_id = 0,
-			.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
-			.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
-		}
-	};
-
-	if (bist == 0) {
-		/* Skip this if there was a built in self test failure */
-		early_mtrr_init();
-		if (memory_initialized())
-			skip_romstage();
-	}
-
-	/* Setup the console */
-	pc87427_disable_dev(CONSOLE_SERIAL_DEV);
-	pc87427_disable_dev(HIDDEN_SERIAL_DEV);
-	pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
-        /* Enable Serial 2 lines instead of GPIO */
-        outb(0x2c, 0x2e);
-        outb((inb(0x2f) & (~1<<1)), 0x2f);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
-
-	pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
-	xbus_cfg(PC87427_XBUS_DEV);
-
-	/* MOVE ME TO A BETTER LOCATION !!! */
-	/* config LPC decode for flash memory access */
-        device_t dev;
-        dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-        if (dev == PCI_DEV_INVALID)
-                die("Missing ich5?");
-        pci_write_config32(dev, 0xe8, 0x00000000);
-        pci_write_config8(dev, 0xf0, 0x00);
-
-#if 0
-	print_pci_devices();
-#endif
-	enable_smbus();
-#if 0
-//	dump_spd_registers(&cpu[0]);
-	int i;
-	for(i = 0; i < 1; i++)
-		dump_spd_registers();
-#endif
-	disable_watchdogs();
-	power_down_reset_check();
-//	dump_ipmi_registers();
-	mainboard_set_e7520_leds();
-	sdram_initialize(ARRAY_SIZE(mch), mch);
-	ich5_watchdog_on();
-#if 0
-	dump_pci_devices();
-	dump_pci_device(PCI_DEV(0, 0x00, 0));
-	dump_bar14(PCI_DEV(0, 0x00, 0));
-#endif
-	/* NOTE: ROMCC dies with an internal compiler error if the
-	 * following line is removed.
-	 */
-	print_debug("SDRAM is up.\n");
-}
diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c
deleted file mode 100644
index 7f7a039..0000000
--- a/src/mainboard/intel/jarrell/watchdog.c
+++ /dev/null
@@ -1,139 +0,0 @@
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-
-#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
-#define NSC_WDBASE 0x600
-#define ICH5_WDBASE 0x400
-#define ICH5_GPIOBASE 0x500
-
-static void disable_sio_watchdog(device_t dev)
-{
-	/* FIXME move me somewhere more appropriate */
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 1);
-	pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
-	/* disable the sio watchdog */
-	outb(0, NSC_WDBASE + 0);
-	pnp_set_enable(dev, 0);
-}
-
-static void disable_ich5_watchdog(void)
-{
-	/* FIXME move me somewhere more appropriate */
-	device_t dev;
-	unsigned long value, base;
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("Missing ich5?");
-	}
-	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
-
-	/* Set and enable acpibase */
-	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
-	pci_write_config8(dev, 0x44, 0x10);
-	base = ICH5_WDBASE + 0x60;
-
-	/* Set bit 11 in TCO1_CNT */
-	value = inw(base + 0x08);
-	value |= 1 << 11;
-	outw(value, base + 0x08);
-
-	/* Clear TCO timeout status */
-	outw(0x0008, base + 0x04);
-	outw(0x0002, base + 0x06);
-}
-
-static void disable_jarell_frb3(void)
-{
-	device_t dev;
-	unsigned long value, base;
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("Missing ich5?");
-	}
-	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 0);
-	pci_write_config16(dev, 0x04, value);
-
-	/* Set gpio base */
-	pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
-	base = ICH5_GPIOBASE;
-
-	/* Enable GPIO Bar */
-	value = pci_read_config32(dev, 0x5c);
-	value |= 0x10;
-	pci_write_config32(dev, 0x5c, value);
-
-	/* Configure GPIO 48 and 40 as GPIO */
-	value = inl(base + 0x30);
-	value |= (1 << 16) | ( 1 << 8);
-	outl(value, base + 0x30);
-
-	/* Configure GPIO 48 as Output */
-	value = inl(base + 0x34);
-	value &= ~(1 << 16);
-	outl(value, base + 0x34);
-
-	/* Toggle GPIO 48 high to low */
-	value = inl(base + 0x38);
-	value |= (1 << 16);
-	outl(value, base + 0x38);
-	value &= ~(1 << 16);
-	outl(value, base + 0x38);
-
-}
-
-static void disable_watchdogs(void)
-{
-	disable_sio_watchdog(NSC_WD_DEV);
-	disable_ich5_watchdog();
-	disable_jarell_frb3();
-	print_debug("Watchdogs disabled\n");
-}
-
-static void ich5_watchdog_on(void)
-{
-	device_t dev;
-	unsigned long value, base;
-	unsigned char byte;
-
-	/* check cmos options */
-	byte = cmos_read(RTC_BOOT_BYTE-1);
-	if(!(byte & 1)) return; /* no boot watchdog */
-	byte = cmos_read(RTC_BOOT_BYTE);
-	if(!(byte & 2)) return; /* fallback so ignore */
-
-	dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
-	if (dev == PCI_DEV_INVALID) {
-		die("Missing ich5?");
-	}
-	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
-
-	/* Set and enable acpibase */
-	pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
-	pci_write_config8(dev, 0x44, 0x10);
-	base = ICH5_WDBASE + 0x60;
-
-	/* Clear TCO timeout status */
-	outw(0x0008, base + 0x04);
-	outw(0x0002, base + 0x06);
-
-	/* set the time value 1 cnt = .6 sec */
-	outw(0x0010, base + 0x01);
-	/* reload the timer with the value */
-	outw(0x0001, base + 0x00);
-
-	/* clear bit 11 in TCO1_CNT to start watchdog */
-	value = inw(base + 0x08);
-	value &= ~(1 << 11);
-	outw(value, base + 0x08);
-
-	print_debug("Watchdog ICH5 enabled\n");
-}
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
deleted file mode 100644
index 5f7de08..0000000
--- a/src/mainboard/intel/truxton/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-if BOARD_INTEL_TRUXTON
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_X86
-	select CPU_INTEL_EP80579
-	select NORTHBRIDGE_INTEL_I3100
-	select SOUTHBRIDGE_INTEL_I3100
-	select SUPERIO_INTEL_I3100
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select ROMCC
-	select HAVE_HARD_RESET
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
-	string
-	default intel/truxton
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Truxton"
-
-config IRQ_SLOT_COUNT
-	int
-	default 1
-
-config MAX_CPUS
-	int
-	default 4
-
-endif # BOARD_INTEL_TRUXTON
diff --git a/src/mainboard/intel/truxton/Makefile.inc b/src/mainboard/intel/truxton/Makefile.inc
deleted file mode 100644
index 6ef4fc9..0000000
--- a/src/mainboard/intel/truxton/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
diff --git a/src/mainboard/intel/truxton/board_info.txt b/src/mainboard/intel/truxton/board_info.txt
deleted file mode 100644
index 7fb5aac..0000000
--- a/src/mainboard/intel/truxton/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Board name: EP80579 devkit (Truxton)
-Category: eval
diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb
deleted file mode 100644
index 05fb05e..0000000
--- a/src/mainboard/intel/truxton/devicetree.cb
+++ /dev/null
@@ -1,55 +0,0 @@
-chip northbridge/intel/i3100
-        device domain 0 on
-                subsystemid 0x8086 0x2680 inherit
-                device pci 00.0 on end # IMCH
-                device pci 00.1 on end # IMCH error status
-                device pci 01.0 on end # IMCH EDMA engine
-                device pci 02.0 on end # PCIe port A/A0
-                device pci 03.0 on end # PCIe port A1
-                device pci 04.0 on end # ?
-                device pci 08.0 off end # must be off to boot
-                device pci 0d.0 off end # must be off to boot
-                device pci 0d.1 off end # must be off to boot
-                chip southbridge/intel/i3100
-                        # PIRQ line -> legacy IRQ mappings
-                        register "pirq_a_d" = "0x0b070a05"
-                        register "pirq_e_h" = "0x0a808080"
-
-                        device pci 1d.0 on end  # USB (UHCI)
-                        device pci 1d.7 on end  # USB (EHCI)
-                        device pci 1f.0 on      # LPC bridge
-                                chip superio/intel/i3100
-                                        device pnp 4e.4 on # Com1
-                                                 io 0x60 = 0x3f8
-                                                irq 0x70 = 4
-                                        end
-                                        device pnp 4e.5 on # Com2
-                                                 io 0x60 = 0x2f8
-                                                irq 0x70 = 3
-                                        end
-				end
-				chip superio/smsc/smscsuperio
-					device pnp 2e.0 off end
-					device pnp 2e.3 off end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.7 on # PS/2 keyboard / mouse
-            					io 0x60 = 0x60
-            					io 0x62 = 0x64
-            					irq 0x70 = 1	# PS/2 keyboard interrupt
-            					irq 0x72 = 12	# PS/2 mouse interrupt
-					end
-					device pnp 2e.a off end
-                                end
-                        end
-                        device pci 1f.2 on end  # SATA
-                        device pci 1f.3 on end  # SMBus
-                        device pci 1f.4 on end  # ?
-                end
-        end
-        device cpu_cluster 0 on
-                chip cpu/intel/ep80579
-                        device lapic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c
deleted file mode 100644
index 9c5ca41..0000000
--- a/src/mainboard/intel/truxton/irq_tables.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE, /* u32 signature */
-	PIRQ_VERSION,   /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices)  */
-	0x00,       /* u8 Bus 0 */
-	(0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */
-	0x0000,     /* u16 reserve IRQ for PCI */
-	0x8086,     /* u16 Vendor */
-	0x5031,     /* Device ID */
-	0x00000000, /* u32 miniport_data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x5e,   /*  u8 checksum - mod 256 checksum must give zero */
-	{  /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  */
-	    {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00,  0x00},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
-
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
deleted file mode 100644
index 1c4b602..0000000
--- a/src/mainboard/intel/truxton/mptable.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-	u8 bus_pea0 = 0;
-	u8 bus_pea1 = 0;
-	u8 bus_aioc;
-	device_t dev;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	/* AIOC bridge */
-	dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
-	if (dev) {
-		bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
-		bus_aioc = 0;
-	}
-	/* PCIe A0 */
-	dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
-	if (dev) {
-		bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
-		bus_pea0 = 0;
-	}
-	/* PCIe A1 */
-	dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
-	if (dev) {
-		bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-	else {
-		printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
-		bus_pea1 = 0;
-	}
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* IOAPIC handling */
-	smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
-
-	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
-
-	/* Standard local interrupt assignments */
-	mptable_lintsrc(mc, bus_isa);
-
-	/* IMCH/IICH PCI devices */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
-
-	if (bus_pea0) {
-		/* PCIe slot 0 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|0, 0x8, 0x10);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|1, 0x8, 0x11);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|2, 0x8, 0x12);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea0, (0<<2)|3, 0x8, 0x13);
-	}
-
-	if (bus_pea1) {
-		/* PCIe slots 1-4 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|0, 0x8, 0x10);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|1, 0x8, 0x11);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|2, 0x8, 0x12);
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_pea1, (0<<2)|3, 0x8, 0x13);
-	}
-
-	if (bus_aioc) {
-		/* AIOC PCI devices */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-				 bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
-	}
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
-
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
deleted file mode 100644
index 71c5f38..0000000
--- a/src/mainboard/intel/truxton/romstage.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include "drivers/pc80/udelay_io.c"
-#include <console/console.h>
-#include "southbridge/intel/i3100/early_smbus.c"
-#include "southbridge/intel/i3100/early_lpc.c"
-#include "northbridge/intel/i3100/raminit_ep80579.h"
-#include "superio/intel/i3100/i3100.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/intel/i3100/early_serial.c"
-#include "cpu/x86/bist.h"
-#include <spd.h>
-
-#define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
-
-static inline int spd_read_byte(u16 device, u8 address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i3100/raminit_ep80579.c"
-#include "lib/generic_sdram.c"
-#include "../../intel/jarrell/debug.c"
-#include "arch/x86/lib/stages.c"
-
-#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
-
-static void main(unsigned long bist)
-{
-	msr_t msr;
-	u16 perf;
-	static const struct mem_controller mch[] = {
-		{
-			.node_id = 0,
-			.f0 = PCI_DEV(0, 0x00, 0),
-			.channel0 = { DIMM2, DIMM3 },
-		}
-	};
-
-	if (bist == 0) {
-		/* Skip this if there was a built in self test failure */
-		early_mtrr_init();
-		if (memory_initialized())
-			skip_romstage();
-	}
-
-	/* Set up the console */
-	i3100_enable_superio();
-	i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
-
-	console_init();
-
-	/* Prevent the TCO timer from rebooting us */
-	i3100_halt_tco_timer();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-#ifdef TRUXTON_DEBUG
-	print_pci_devices();
-#endif
-	enable_smbus();
-	dump_spd_registers();
-
-	sdram_initialize(ARRAY_SIZE(mch), mch);
-	dump_pci_devices();
-	dump_pci_device(PCI_DEV(0, 0x00, 0));
-#ifdef TRUXTON_DEBUG
-	dump_bar14(PCI_DEV(0, 0x00, 0));
-#endif
-}
diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig
deleted file mode 100644
index 276b1f7..0000000
--- a/src/mainboard/intel/xe7501devkit/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-if BOARD_INTEL_XE7501DEVKIT
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_X86
-	select CPU_INTEL_SOCKET_MPGA604
-	select NORTHBRIDGE_INTEL_E7501
-	select SOUTHBRIDGE_INTEL_I82870
-	select SOUTHBRIDGE_INTEL_I82801CX
-	select SUPERIO_SMSC_LPC47B272
-	select ROMCC
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select UDELAY_TSC
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-
-config MAINBOARD_DIR
-	string
-	default intel/xe7501devkit
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "XE7501devkit"
-
-config IRQ_SLOT_COUNT
-	int
-	default 12
-
-config MAX_CPUS
-	int
-	default 2
-
-endif # BOARD_INTEL_XE7501DEVKIT
diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c
deleted file mode 100644
index b3c20ba..0000000
--- a/src/mainboard/intel/xe7501devkit/acpi_tables.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Ported to Intel XE7501DEVKIT from Agami Aruma
- * written by Stefan Reinauer <stepan at openbios.org>
- *  (C) 2005 Stefan Reinauer
- *  (C) 2005 Digital Design Corporation
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <assert.h>
-#include "bus.h"
-#include "ioapic.h"
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
-	/* Just a dummy */
-	return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
-	// Not implemented
-	return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
-	// Not implemented
-	return current;
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	unsigned int irq_start = 0;
-	device_t dev = 0;
-    struct resource* res = NULL;
-
-
-	// SJM: Hard-code CPU LAPIC entries for now
-	//		Use SourcePoint numbering of processors
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
-
-
-	// Southbridge IOAPIC
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, IO_APIC_ADDR, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-	// P64H2#2 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-	// P64H2#2 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-
-	// P64H2#1 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-	// P64H2#1 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
-	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-	// Map ISA IRQ 0 to IRQ 2
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
-
-	// IRQ9 differs from ISA standard - ours is active high, level-triggered
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
-
-	return current;
-}
-
-
-unsigned long write_acpi_tables(unsigned long start)
-{
-	unsigned long current;
-	acpi_rsdp_t *rsdp;
-	acpi_rsdt_t *rsdt;
-	acpi_madt_t *madt;
-
-	/* Align ACPI tables to 16byte */
-	start   = ALIGN(start, 16);
-	current = start;
-
-	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-	/* We need at least an RSDP and an RSDT Table */
-	rsdp = (acpi_rsdp_t *) current;
-	current += sizeof(acpi_rsdp_t);
-	rsdt = (acpi_rsdt_t *) current;
-	current += sizeof(acpi_rsdt_t);
-
-	/* clear all table memory */
-	memset((void *)start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, NULL);
-	acpi_write_rsdt(rsdt);
-
-	/*
-	 * We explicitly add these tables later on:
-	 */
-	/* QNX wants an MADT */
-	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
-
-	madt = (acpi_madt_t *) current;
-	acpi_create_madt(madt);
-	current+=madt->header.length;
-	acpi_add_table(rsdp,madt);
-
-	printk(BIOS_INFO, "ACPI: done.\n");
-	return current;
-}
-
diff --git a/src/mainboard/intel/xe7501devkit/board_info.txt b/src/mainboard/intel/xe7501devkit/board_info.txt
deleted file mode 100644
index b351b8e..0000000
--- a/src/mainboard/intel/xe7501devkit/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/intel/xe7501devkit/bus.h b/src/mainboard/intel/xe7501devkit/bus.h
deleted file mode 100644
index 286120a..0000000
--- a/src/mainboard/intel/xe7501devkit/bus.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef XE7501DEVKIT_BUS_H_INCLUDED
-#define XE7501DEVKIT_BUS_H_INCLUDED
-
-// These were determined by seeing how coreboot enumerates the various
-// PCI (and PCI-like) buses on the board.
-
-#define PCI_BUS_CHIPSET		0
-#define PCI_BUS_E7501_HI_B	1		// P64H2#2
-#define PCI_BUS_P64H2_2_B	2		// P64H2#2 bus B
-#define PCI_BUS_P64H2_2_A	3		// P64H2#2 bus A
-#define PCI_BUS_E7501_HI_D	4		// P64H2#1
-#define PCI_BUS_P64H2_1_B	5		// P64H2#1 bus B
-#define PCI_BUS_P64H2_1_A	6		// P64H2#1 bus A
-#define PCI_BUS_ICH3		7		// ICH3-S
-
-#endif	// XE7501DEVKIT_BUS_H_INCLUDED
diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout
deleted file mode 100644
index 322f1c9..0000000
--- a/src/mainboard/intel/xe7501devkit/cmos.layout
+++ /dev/null
@@ -1,53 +0,0 @@
-entries
-
-#start-bit length  config config-ID    name
-0           512      r       0        reserved_memory1	# We know nothing about the factory BIOS
-512         512      r       0        reserved_memory2	# More factory BIOS
-
-# Work in progress.
-# This is where we would put the LB RTC_BOOT_BYTE options once the code
-# supports finding them there.
-#1024         1       e       4        boot_option
-#1025         1       e       4        last_boot
-#1026         1       e       1        ECC_memory
-#1028         4       r       0        reboot_bits
-
-# Options used by XE7501DevKit
-#1032         3       e       5        baud_rate
-#1035         1       e       2        hyper_threading
-#1036         1       e       1        power_on_after_fail
-#1037         1       e       1        nmi
-
-#1040         4       e       6        debug_level
-
-#1048        16       h       0        check_sum
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-
-checksums
-
-# Checksum FROM bit-location TO bit-location STORE AT bit-location
-checksum 1024 1047 1048
-
diff --git a/src/mainboard/intel/xe7501devkit/devicetree.cb b/src/mainboard/intel/xe7501devkit/devicetree.cb
deleted file mode 100644
index 215ed97..0000000
--- a/src/mainboard/intel/xe7501devkit/devicetree.cb
+++ /dev/null
@@ -1,73 +0,0 @@
-chip northbridge/intel/e7501
-	device domain 0 on
-		subsystemid 0x8086 0x2480 inherit
-		device pci 0.0 on end # Chipset host controller
-		device pci 0.1 on end # Host RASUM controller
-		device pci 2.0 on # Hub interface B
-			chip southbridge/intel/i82870 # P64H2
-				device pci 1c.0 on end # IOAPIC - bus B
-				device pci 1d.0 on end # Hub to PCI-B bridge
-				device pci 1e.0 on end # IOAPIC - bus A
-				device pci 1f.0 on end # Hub to PCI-A bridge
-			end
-		end
-		device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
-		device pci 4.0 on # Hub interface D
-			chip southbridge/intel/i82870 # P64H2
-				device pci 1c.0 on end # IOAPIC - bus B
-				device pci 1d.0 on end # Hub to PCI-B bridge
-				device pci 1e.0 on end # IOAPIC - bus A
-				device pci 1f.0 on end # Hub to PCI-A bridge
-			end
-		end
-		device pci 6.0 on end # E7501 Power management registers? (undocumented)
-		chip southbridge/intel/i82801cx
-			device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
-			device pci 1d.1 off end # USB (not populated)
-			device pci 1d.2 off end # USB (not populated)
-			device pci 1e.0 on # Hub to PCI bridge
-				device pci 0.0 on end
-			end
-			device pci 1f.0 on # LPC bridge
-				chip superio/smsc/lpc47b272
-					device pnp 2e.0 off # Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.3 off # Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.4 on # Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.5 off # Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.7 on # Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1 # Keyboard interrupt
-						irq 0x72 = 12 # Mouse interrupt
-					end
-					device pnp 2e.a off end # ACPI
-				end
-			end
-			device pci 1f.1 on end # IDE
-			device pci 1f.3 on end # SMBus
-			device pci 1f.5 off end # AC97 Audio
-			device pci 1f.6 off end # AC97 Modem
-		end # SB
-	end # PCI domain
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_mPGA604
-			device lapic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604
-			device lapic 6 on end
-		end
-	end
-end
diff --git a/src/mainboard/intel/xe7501devkit/dsdt.asl b/src/mainboard/intel/xe7501devkit/dsdt.asl
deleted file mode 100644
index 87dd574..0000000
--- a/src/mainboard/intel/xe7501devkit/dsdt.asl
+++ /dev/null
@@ -1,16 +0,0 @@
-/* This is a dummy dsdt. Normal ACPI requires a DSDT, but in this case, ACPI
-   is just a workaround for QNX. It would be nice to eventually have a real
-   dsdt here.
-   Note: It will not be hooked up at runtime. It won't even get linked.
-   But we still need this file. */
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0
-	"COREv2",	// OEM id
-	"COREBOOT",	// OEM table id
-	0x20090419	// OEM revision
-)
-{
-}
diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h
deleted file mode 100644
index 9ac2aee..0000000
--- a/src/mainboard/intel/xe7501devkit/ioapic.h
+++ /dev/null
@@ -1,11 +0,0 @@
-// IOAPIC addresses determined by coreboot enumeration.
-// Someday add functions to get APIC IDs and versions from the chips themselves.
-
-#define IOAPIC_ICH3				2
-#define IOAPIC_P64H2_2_BUS_B	3	// IOAPIC 3 at 01:1c.0  MBAR = fe300000 DataAddr = fe300010
-#define IOAPIC_P64H2_2_BUS_A	4	// IOAPIC 4 at 01:1e.0  MBAR = fe301000 DataAddr = fe301010
-#define IOAPIC_P64H2_1_BUS_B	5	// IOAPIC 5 at 04:1c.0  MBAR = fe500000 DataAddr = fe500010
-#define IOAPIC_P64H2_1_BUS_A	8	// IOAPIC 8 at 04:1e.0  MBAR = fe501000 DataAddr = fe501010
-
-#define P64H2_IOAPIC_VERSION	0x20
-#define INTEL_IOAPIC_NUM_INTERRUPTS 24		// Both ICH-3 and P64-H2
diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c
deleted file mode 100644
index 7af7a9f..0000000
--- a/src/mainboard/intel/xe7501devkit/irq_tables.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Run checkpir to verify any changes to this table...
-   Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx
-*/
-
-#include <arch/pirq_routing.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include "bus.h"
-
-#define UNUSED_INTERRUPT {0, 0}
-#define PIRQ_A 0x60
-#define PIRQ_B 0x61
-#define PIRQ_C 0x62
-#define PIRQ_D 0x63
-#define PIRQ_E 0x68
-#define PIRQ_F 0x69
-#define PIRQ_G 0x6A
-#define PIRQ_H 0x6B
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,
-	PIRQ_VERSION,
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,		// Size of this struct in bytes
-	0,			 							// PCI bus number on which the interrupt router resides
-	PCI_DEVFN(31, 0),   					// PCI device/function number of the interrupt router
-	0,		 								// PCI-exclusive IRQ bitmap
-	PCI_VENDOR_ID_INTEL,					// Vendor ID of compatible PCI interrupt router
-	PCI_DEVICE_ID_INTEL_82801CA_LPC,		// Device ID of compatible PCI interrupt router
-	0,		 								// Additional miniport information
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 	// Reserved, must be zero
-	0xB1,      								// Checksum of the entire structure (causes 8-bit sum == 0)
-	{
-		// NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
-		//		 This was determined from linux-2.6.11/arch/x86/pci/irq.c
-		// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
-		// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
-		// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
-
-		//											INTA#			   INTB#		     INTC#		      INTD#
-	//  bus,				device #  		   {link  , bitmap}, {link  , bitmap}, {link  , bitmap}, {link  , bitmap},  slot, rfu
-
-		{PCI_BUS_CHIPSET,	PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// IDE / SMBus
-		{PCI_BUS_CHIPSET,	PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT},   0, 0},	// USB 1.1
-
-		// P64H2#2 Bus A
-		{PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// SCSI
-			// NOTE: Hotplug disabled on this bus
-
-		// P64H2#2 Bus B
-		{PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  23, 0},	// Slot 2A (J23)
-		{PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  24, 0},	// Slot 2B (J24)
-		{PCI_BUS_P64H2_2_B, PCI_DEVFN(3, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  25, 0},	// Slot 2C (J25)
-		{PCI_BUS_P64H2_2_B, PCI_DEVFN(4, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  12, 0},	// Slot 2D (J12)
-			// NOTE: Hotplug disabled on this bus
-
-		// P64H2#1 Bus A
-		{PCI_BUS_P64H2_1_A, PCI_DEVFN(1, 0),  {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}},  20, 0},	// Slot 1A (J20)
-			// NOTE: Hotplug disabled on this bus
-
-		// P64H2#1 Bus B
-		{PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0),  {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// GB Ethernet
-		{PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0),  {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}},  21, 0},	// Slot 1B (J21)
-			// NOTE: Hotplug disabled on this bus
-
-		// ICH-3 PCI bus
-		{PCI_BUS_ICH3,		PCI_DEVFN(0, 0),  {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// Video
-		{PCI_BUS_ICH3,		PCI_DEVFN(2, 0),  {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}},  11, 0},	// Debug slot (J11)
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
deleted file mode 100644
index cc7eda5..0000000
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ /dev/null
@@ -1,142 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <assert.h>
-#include "bus.h"
-#include "ioapic.h"
-
-// Generate MP-table IRQ numbers for PCI devices.
-#define INT_A	0
-#define INT_B	1
-#define INT_C	2
-#define INT_D	3
-#define PCI_IRQ(dev, intLine)	(((dev)<<2) | intLine)
-
-static int bus_isa;
-
-static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
-{
-	device_t dev;
-	struct resource *res;
-
-	// TODO: Gack. This is REALLY ugly.
-
-	// Southbridge IOAPIC
-	smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, IO_APIC_ADDR);	// APIC ID, Version, Address
-
-	// P64H2#2 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
-
-	// P64H2#2 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
-
-
-	// P64H2#1 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
-
-	// P64H2#1 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
-	if (!dev)
-		BUG();
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
-}
-
-static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
-{
-	// Chipset PCI bus
-	//					 Type		Trigger | Polarity							Bus ID				IRQ					APIC ID					PIN#
-	mptable_lintsrc(mc, PCI_BUS_CHIPSET);
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_CHIPSET, 	PCI_IRQ(29, INT_A), IOAPIC_ICH3, 			16);	// USB 1.1 Controller #1
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_CHIPSET,	PCI_IRQ(31, INT_B),	IOAPIC_ICH3,			17);	// SMBus
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_CHIPSET, 	PCI_IRQ(29, INT_C), IOAPIC_ICH3, 			18);	// USB 1.1 Controller #3
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_CHIPSET, 	PCI_IRQ(31, INT_C), IOAPIC_ICH3, 			18);	// IDE
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_CHIPSET, 	PCI_IRQ(29, INT_D), IOAPIC_ICH3, 			19);	// USB 1.1 Controller #2
-
-	// P64H2#2 Bus B
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(1, INT_A), 	IOAPIC_P64H2_2_BUS_B,    0);	// Slot 2A (J23)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(1, INT_B), 	IOAPIC_P64H2_2_BUS_B,    1);	// Slot 2A (J23)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(1, INT_C), 	IOAPIC_P64H2_2_BUS_B,    2);	// Slot 2A (J23)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(1, INT_D), 	IOAPIC_P64H2_2_BUS_B,    3);	// Slot 2A (J23)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(2, INT_A), 	IOAPIC_P64H2_2_BUS_B,    4);	// Slot 2B (J24)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(2, INT_B), 	IOAPIC_P64H2_2_BUS_B,    5);	// Slot 2B (J24)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(2, INT_C), 	IOAPIC_P64H2_2_BUS_B,    6);	// Slot 2B (J24)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(2, INT_D), 	IOAPIC_P64H2_2_BUS_B,    7);	// Slot 2B (J24)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(3, INT_A), 	IOAPIC_P64H2_2_BUS_B,    8);	// Slot 2C (J25)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(3, INT_B), 	IOAPIC_P64H2_2_BUS_B,    9);	// Slot 2C (J25)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(3, INT_C), 	IOAPIC_P64H2_2_BUS_B,   10);	// Slot 2C (J25)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(3, INT_D), 	IOAPIC_P64H2_2_BUS_B,   11);	// Slot 2C (J25)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_A), 	IOAPIC_P64H2_2_BUS_B,   12);	// Slot 2D (J12)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_B), 	IOAPIC_P64H2_2_BUS_B,   13);	// Slot 2D (J12)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_C), 	IOAPIC_P64H2_2_BUS_B,   14);	// Slot 2D (J12)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_D), 	IOAPIC_P64H2_2_BUS_B,   15);	// Slot 2D (J12)
-
-	// P64H2#2 Bus A
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_P64H2_2_A, 	PCI_IRQ(1, INT_A),	IOAPIC_P64H2_2_BUS_A,	 0);	// SCSI
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_P64H2_2_A, 	PCI_IRQ(1, INT_B),	IOAPIC_P64H2_2_BUS_A,	 1);	// SCSI
-
-	// P64H2#1 Bus B
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(1, INT_A), 	IOAPIC_P64H2_1_BUS_B,    0);	// GB Ethernet
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(2, INT_A), 	IOAPIC_P64H2_1_BUS_B,    4);	// Slot 1B (J21)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(2, INT_B), 	IOAPIC_P64H2_1_BUS_B,    5);	// Slot 1B (J21)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(2, INT_C), 	IOAPIC_P64H2_1_BUS_B,    6);	// Slot 1B (J21)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(2, INT_D), 	IOAPIC_P64H2_1_BUS_B,    7);	// Slot 1B (J21)
-
-	// P64H2#1 Bus A
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_A, 	PCI_IRQ(1, INT_A), 	IOAPIC_P64H2_1_BUS_A,    0);	// Slot 1A (J20)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_A, 	PCI_IRQ(1, INT_B), 	IOAPIC_P64H2_1_BUS_A,    1);	// Slot 1A (J20)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_A, 	PCI_IRQ(1, INT_C), 	IOAPIC_P64H2_1_BUS_A,    2);	// Slot 1A (J20)
-	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_A, 	PCI_IRQ(1, INT_D), 	IOAPIC_P64H2_1_BUS_A,    3);	// Slot 1A (J20)
-
-	// ICH-3
-
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(0, INT_A),	IOAPIC_ICH3,			16);	// Video
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_A),	IOAPIC_ICH3,			18);	// Debug slot (J11)
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_B),	IOAPIC_ICH3,			19);	// Debug slot (J11)
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_C),	IOAPIC_ICH3,			16);	// Debug slot (J11)
-	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_D),	IOAPIC_ICH3,			17);	// Debug slot (J11)
-
-	// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
-
-	mptable_add_isa_interrupts(mc, bus_isa, IOAPIC_ICH3, 0);
-}
-
-static void *smp_write_config_table(void* v)
-{
-	struct mp_config_table *mc;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-	xe7501devkit_register_ioapics(mc);
-	xe7501devkit_register_interrupts(mc);
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
deleted file mode 100644
index 342e6f1..0000000
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ /dev/null
@@ -1,75 +0,0 @@
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include "southbridge/intel/i82801cx/early_smbus.c"
-#include "northbridge/intel/e7501/raminit.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/debug.c"
-#include "superio/smsc/lpc47b272/early_serial.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
-
-static void hard_reset(void)
-{
-        outb(0x0e, 0x0cf9);
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/e7501/raminit.c"
-#include "northbridge/intel/e7501/reset_test.c"
-#include "lib/generic_sdram.c"
-
-// This function MUST appear last (ROMCC limitation)
-static void main(unsigned long bist)
-{
-	static const struct mem_controller memctrl[] = {
-		{
-			.d0 = PCI_DEV(0, 0, 0),
-			.d0f1 = PCI_DEV(0, 0, 1),
-			.channel0 = { DIMM0, DIMM1, DIMM2, 0 },
-			.channel1 = { DIMM4, DIMM5, DIMM6, 0 },
-		},
-	};
-
-	if (bist == 0) {
-		// Skip this if there was a built in self test failure
-		early_mtrr_init();
-		enable_lapic();
-	}
-
-	// Get the serial port running and print a welcome banner
-	lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	// Halt if there was a built in self test failure
-	report_bist_failure(bist);
-
-	// print_pci_devices();
-
-	// If this is a warm boot, some initialization can be skipped
-
-	if (!bios_reset_detected())
-	{
-		enable_smbus();
-		// dump_spd_registers(&memctrl[0]);
-		// dump_smbus_registers();
-		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-	}
-
-	// NOTE: ROMCC dies with an internal compiler error
-	//		 if the following line is removed.
-	print_debug("SDRAM is up.\n");
-}



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