[coreboot-gerrit] Patch set updated for coreboot: 6017160 superio/ite/it8712f: Avoid .c includes
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Tue Apr 8 14:03:09 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5476
-gerrit
commit 6017160df546a740316566faf51be7cd3093da92
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Apr 8 17:26:11 2014 +1000
superio/ite/it8712f: Avoid .c includes
NOTFORMERGE
Following the same reasoning as commit
d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid
.c includes
Clean up the early_serial #include directives in mainboard/romstage code.
This however requires a major re-write of superio/ite/it8712f.
Change-Id: I502d59671fa2888a43eb473af618ea46ad237aa7
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/amd/dbm690t/romstage.c | 2 +-
src/mainboard/amd/pistachio/romstage.c | 2 +-
src/mainboard/asus/a8n_e/romstage.c | 2 +-
src/mainboard/asus/f2a85-m/romstage.c | 2 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 2 +-
src/mainboard/asus/m2v/romstage.c | 26 +++----
src/mainboard/asus/m4a78-em/romstage.c | 2 +-
src/mainboard/asus/m4a785-m/romstage.c | 2 +-
src/mainboard/ecs/p6iwp-fe/romstage.c | 2 +-
src/mainboard/lippert/hurricane-lx/romstage.c | 2 +-
src/mainboard/lippert/literunner-lx/romstage.c | 2 +-
src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +-
src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +-
src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +-
src/mainboard/technexion/tim5690/romstage.c | 2 +-
src/mainboard/technexion/tim8690/romstage.c | 2 +-
src/superio/ite/it8712f/Makefile.inc | 2 +-
src/superio/ite/it8712f/chip.h | 2 +-
src/superio/ite/it8712f/early_serial.c | 91 ++++++++++++-------------
src/superio/ite/it8712f/it8712f.h | 9 +--
20 files changed, 78 insertions(+), 82 deletions(-)
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 74b6d1b..8f07d4e 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -35,7 +35,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <spd.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 2971072..9953fff 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -30,7 +30,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <spd.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 29f425a..6d3565b 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -33,7 +33,7 @@
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index bc7546c..a7b08cf 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -38,7 +38,7 @@
/* TODO: remove .c includes */
#include <drivers/pc80/i8254.c>
#include <drivers/pc80/i8259.c>
-#include <superio/ite/it8712f/early_serial.c>
+#include <superio/ite/it8712f/it8712f.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void disable_cache_as_ram(void);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index ef0ce87..7e189b5 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 1ca145d..b7ca810 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus);
#include "lib/delay.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "southbridge/via/vt8237r/early_smbus.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -46,6 +46,7 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
#define IT8712F_GPIO_BASE 0x0a20
@@ -163,15 +164,16 @@ static void m2v_it8712f_gpio_init(void)
* 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
* 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
*/
- it8712f_enter_conf();
- giv = gpio_init_data;
- while (giv->addr) {
- printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
- giv->addr, giv->val);
- it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
- giv++;
- }
- it8712f_exit_conf();
+ // FIXME: fix this as a follow up..
+// it8712f_enter_conf();
+// giv = gpio_init_data;
+// while (giv->addr) {
+// printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
+// giv->addr, giv->val);
+// it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
+// giv++;
+// }
+// it8712f_exit_conf();
printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
/*
@@ -225,9 +227,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
int needs_reset = 0;
struct sys_info *sysinfo = &sysinfo_car;
- it8712f_24mhz_clkin();
+ it8712f_24mhz_clkin(CLKIN_DEV);
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog();
+ it8712f_kill_watchdog(WATCHDOG_DEV);
console_init();
enable_rom_decode();
m2v_bus_init();
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 18c6f18..7d4bed0 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -41,7 +41,7 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 660ab0f..75bff90 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -41,7 +41,7 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c
index 1ebdedd..b7819bf 100644
--- a/src/mainboard/ecs/p6iwp-fe/romstage.c
+++ b/src/mainboard/ecs/p6iwp-fe/romstage.c
@@ -30,7 +30,7 @@
#include "northbridge/intel/i82810/raminit.h"
#include "drivers/pc80/udelay_io.c"
#include "cpu/x86/bist.h"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include <lib.h>
void main(unsigned long bist)
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 95ea27d..e87b326 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -35,7 +35,7 @@
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum. */
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 6edcf37..b54e0d5 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -35,7 +35,7 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 68dcfc0..9ec77d0 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -35,7 +35,7 @@
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
int spd_read_byte(unsigned int device, unsigned int address)
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 59bd618..1e75e53 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -35,7 +35,7 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 6d36524..4091de8 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -43,7 +43,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 42c2599..a179513 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -37,7 +37,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 22a1212..4af88fa 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -37,7 +37,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc
index 3c8a512..ce75645 100644
--- a/src/superio/ite/it8712f/Makefile.inc
+++ b/src/superio/ite/it8712f/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c
-
diff --git a/src/superio/ite/it8712f/chip.h b/src/superio/ite/it8712f/chip.h
index 1f159cd..0354a8d 100644
--- a/src/superio/ite/it8712f/chip.h
+++ b/src/superio/ite/it8712f/chip.h
@@ -29,4 +29,4 @@ struct superio_ite_it8712f_config {
struct pc_keyboard keyboard;
};
-#endif
+#endif /* SUPERIO_ITE_IT8712F_CHIP_H */
diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c
index 51564fc..cc9e2a3 100644
--- a/src/superio/ite/it8712f/early_serial.c
+++ b/src/superio/ite/it8712f/early_serial.c
@@ -19,13 +19,9 @@
*/
#include <arch/io.h>
+#include <device/pnp.h>
#include "it8712f.h"
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
/* Global configuration registers. */
#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
@@ -35,17 +31,9 @@
#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */
#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
-static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
-{
- outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8712f_enter_conf(void)
+static void pnp_enter_conf_state(device_t dev)
{
- u16 port = 0x2e; /* TODO: Don't hardcode! */
+ u16 port = dev >> 8;
outb(0x87, port);
outb(0x01, port);
@@ -53,17 +41,24 @@ static void it8712f_enter_conf(void)
outb((port == 0x4e) ? 0xaa : 0x55, port);
}
-static void it8712f_exit_conf(void)
+static void pnp_exit_conf_state(device_t dev)
{
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_CC, 0x02);
}
/* Select 24MHz CLKIN (48MHz is the default). */
-void it8712f_24mhz_clkin(void)
+/*
+ * in romstage.c
+ * #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+ * and pass: CLKIN_DEV
+ */
+void it8712f_24mhz_clkin(device_t dev)
{
- it8712f_enter_conf();
- it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
- it8712f_exit_conf();
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_CLOCKSEL, 0x01);
+ pnp_exit_conf_state(dev);
}
/*
@@ -75,43 +70,41 @@ void it8712f_24mhz_clkin(void)
* 0: 3VSBSW# will be always inactive.
* 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
*/
-void it8712f_enable_3vsbsw(void)
+/*
+ * in romstage.c
+ * #define 3VSBSW_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+ * and pass: 3VSBSW_DEV
+ */
+void it8712f_enable_3vsbsw(device_t dev)
{
- it8712f_enter_conf();
- it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
- it8712f_exit_conf();
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_MFC, 0x80);
+ pnp_exit_conf_state(dev);
}
-void it8712f_kill_watchdog(void)
+/*
+ * in romstage.c
+ * #define WDT_DEV PNP_DEV(0x2e, IT8712F_GPIO)
+ * and pass: WTD_DEV
+ */
+void it8712f_kill_watchdog(device_t dev)
{
- it8712f_enter_conf();
- it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
- it8712f_exit_conf();
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
+ pnp_exit_conf_state(dev);
}
/* Enable the serial port(s). */
void it8712f_enable_serial(device_t dev, u16 iobase)
{
- /* (1) Enter the configuration state (MB PnP mode). */
- it8712f_enter_conf();
-
- /* (2) Modify the data of configuration registers. */
-
- /*
- * Select the chip to configure (if there's more than one).
- * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- * If this register is not written, both chips are configured.
- */
-
- /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
-
- /* Enable serial port(s). */
- it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
+ pnp_enter_conf_state(dev);
- /* Clear software suspend mode (clear bit 0). TODO: Needed? */
- /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
- /* (3) Exit the configuration state (MB PnP mode). */
- it8712f_exit_conf();
+ pnp_exit_conf_state(dev);
}
diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h
index 5ec6188..06d409d 100644
--- a/src/superio/ite/it8712f/it8712f.h
+++ b/src/superio/ite/it8712f/it8712f.h
@@ -35,8 +35,9 @@
#define IT8712F_GAME 0x09 /* GAME port */
#define IT8712F_IR 0x0a /* Consumer IR */
-void it8712f_kill_watchdog(void);
+void it8712f_kill_watchdog(device_t);
void it8712f_enable_serial(device_t dev, u16 iobase);
-void it8712f_24mhz_clkin(void);
-void it8712f_enable_3vsbsw(void);
-#endif
+void it8712f_24mhz_clkin(device_t);
+void it8712f_enable_3vsbsw(device_t);
+
+#endif /* SUPERIO_ITE_IT8712F_IT8712F_H */
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