[coreboot-gerrit] New patch to review for coreboot: 3a345be inteltool: Add partial support for H87/C220 chipsets
Roland A. Lugasi (gaugedev@gmail.com)
gerrit at coreboot.org
Wed Apr 9 00:44:32 CEST 2014
Roland A. Lugasi (gaugedev at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5479
-gerrit
commit 3a345be23154ed465a774b4e3f6e494d11fbad2e
Author: Roland A. Lugasi <gaugedev at gmail.com>
Date: Wed Apr 9 01:42:20 2014 +0300
inteltool: Add partial support for H87/C220 chipsets
inteltool now can dump GPIO, RCBA and PMBASE info from H87 chipsets
Change-Id: I28386dddfb59c83c108aced9a12c6095deafcade
Signed-off-by: Roland A. Lugasi <gaugedev at gmail.com>
---
util/inteltool/gpio.c | 8 ++++++++
util/inteltool/inteltool.c | 2 ++
util/inteltool/inteltool.h | 2 ++
util/inteltool/powermgt.c | 5 +++++
util/inteltool/rootcmplx.c | 6 ++++++
5 files changed, 23 insertions(+)
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 42e7272..e49494c 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -459,6 +459,14 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
gpio_defaults = pp_pch_mobile_defaults;
defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);
break;
+ case PCI_DEVICE_ID_INTEL_C220:
+ case PCI_DEVICE_ID_INTEL_H87:
+ gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+ gpio_registers = pch_gpio_registers;
+ size = ARRAY_SIZE(pch_gpio_registers);
+ gpio_defaults = pp_pch_desktop_defaults;
+ defaults_size = ARRAY_SIZE(pp_pch_desktop_defaults);
+ break;
case PCI_DEVICE_ID_INTEL_ICH10R:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich10_gpio_registers;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 219d84e..bbf3092 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -150,6 +150,8 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H87, "H87" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C220, "C220" },
{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
};
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 88008e4..5183fe0 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -108,6 +108,8 @@
#define PCI_DEVICE_ID_INTEL_HM75 0x1e5d
#define PCI_DEVICE_ID_INTEL_HM70 0x1e5e
#define PCI_DEVICE_ID_INTEL_NM70 0x1e5f
+#define PCI_DEVICE_ID_INTEL_H87 0x8c4a
+#define PCI_DEVICE_ID_INTEL_C220 0x8c58
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index 3bc4efc..200353a 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -689,6 +689,11 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
pm_registers = pch_pm_registers;
size = ARRAY_SIZE(pch_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_H87:
+ pmbase = pci_read_word(sb, 0x40) & 0xff80;
+ pm_registers = pch_pm_registers;
+ size = ARRAY_SIZE(pch_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH10R:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = ich10_pm_registers;
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index f1e902d..850f7c3 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -86,6 +86,8 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_B75:
case PCI_DEVICE_ID_INTEL_H77:
case PCI_DEVICE_ID_INTEL_C216:
+ rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
+ break;
case PCI_DEVICE_ID_INTEL_QM77:
case PCI_DEVICE_ID_INTEL_QS77:
case PCI_DEVICE_ID_INTEL_HM77:
@@ -95,6 +97,10 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_HM70:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break;
+ case PCI_DEVICE_ID_INTEL_H87:
+ case PCI_DEVICE_ID_INTEL_C220:
+ rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
+ break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
case PCI_DEVICE_ID_INTEL_ICH2:
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