[coreboot-gerrit] Patch set updated for coreboot: 535fb52 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Thu Apr 10 17:42:13 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5481

-gerrit

commit 535fb52e5172003cada5baa404bf4807081057f9
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Thu Apr 10 19:12:28 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
    
    Keep under 80 colums and Doxygen'ify inline documentation somewhat.
    Strip some whitespace bulk while here.
    
    Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c   |  34 +++--
 src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h   |   2 +-
 src/mainboard/jetway/nf81-t56n-lf/Makefile.inc     |   2 -
 .../jetway/nf81-t56n-lf/PlatformGnbPcie.c          | 170 +++++++++++++--------
 .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h   |  88 ++++++-----
 src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c    |  10 +-
 src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c   |  29 ----
 src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h   |  47 ++----
 src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c   |  57 +++----
 src/mainboard/jetway/nf81-t56n-lf/irq_tables.c     |  24 ++-
 src/mainboard/jetway/nf81-t56n-lf/mainboard.c      |   4 +-
 src/mainboard/jetway/nf81-t56n-lf/mptable.c        |  13 +-
 src/mainboard/jetway/nf81-t56n-lf/romstage.c       |   2 +-
 13 files changed, 241 insertions(+), 241 deletions(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 1d2aef0..e86b813 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -400,13 +400,13 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 	ResetType = Data;
 	StdHeader = ConfigPtr;
 
-	//
-	// Perform the RESET based upon the ResetType. In case of
-	// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
-	// AmdResetManager. During the critical condition, where reset is required
-	// immediately, the reset will be invoked directly by writing 0x04 to port
-	// 0xCF9 (Reset Port).
-	//
+	/**
+	* Perform the RESET based upon the ResetType. In case of
+	* WARM_RESET_WHENEVER and COLD_RESET_WHENEVER, the request will go to
+	* AmdResetManager. During the critical condition, where reset is required
+	* immediately, the reset will be invoked directly by writing 0x04 to port
+	* 0xCF9 (Reset Port).
+	*/
 	switch (ResetType) {
 	case WARM_RESET_WHENEVER:
 	case COLD_RESET_WHENEVER:
@@ -442,31 +442,35 @@ AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 	return AGESA_UNSUPPORTED;
 }
-/*	Call the host environment interface to provide a user hook opportunity. */
+
+/* Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 	return AGESA_SUCCESS;
 }
-/*	Call the host environment interface to provide a user hook opportunity. */
+
+/* Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
-	// Make sure the right speed settings are selected.
+	/* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
+	 * Make sure the right speed settings are selected.
+	 */
 	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
 	return AGESA_SUCCESS;
 }
 
-/*	Call the host environment interface to provide a user hook opportunity. */
+/* Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 	return AGESA_SUCCESS;
 }
 
-/*	Call the host environment interface to provide a user hook opportunity. */
+/* Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 	return AGESA_SUCCESS;
 }
+
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
@@ -481,7 +485,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 
 	FcnData = Data;
 	ResetInfo = ConfigPtr;
-	// Get SB800 MMIO Base (AcpiMmioAddr)
+	/* Get SB800 MMIO Base (AcpiMmioAddr) */
 	WriteIo8(0xCD6, 0x27);
 	Data8 = ReadIo8(0xCD7);
 	Data16=Data8<<8;
@@ -493,7 +497,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 	switch (ResetInfo->ResetId)
 	{
-	case 46:	// GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
+	case 46:	/* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
index c4f4f70..98cff3b 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
@@ -70,4 +70,4 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 
-#endif //_BIOS_CALLOUT_H_
+#endif /* _BIOS_CALLOUT_H_ */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
index e1f18a9..0630008 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
+++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
@@ -33,5 +33,3 @@ ramstage-y += buildOpts.c
 ramstage-y += agesawrapper.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
-
-
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
index d7413cd..f60bc8f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,22 +25,6 @@
 
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *	OemCustomizeInitEarly
- *
- *	Description:
- *	This stub function will call the host environment through the binary block
- *	interface (call-out port) to provide a user hook opportunity
- *
- *	Parameters:
- *	@param[in]		**PeiServices
- *	@param[in]		*InitEarly
- *
- *	@retval		 VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
 VOID
 OemCustomizeInitEarly (
 	IN	OUT AMD_EARLY_PARAMS	*InitEarly
@@ -52,52 +37,95 @@ OemCustomizeInitEarly (
 
 	ALLOCATE_HEAP_PARAMS AllocHeapParams;
 
+/**
+ * @brief Initialize Port descriptors
+ */
 PCIe_PORT_DESCRIPTOR PortList [] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+		/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
 		{
-			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT,
+										GNB_GPP_PORT4_CHANNEL_TYPE,
+										4,
+										GNB_GPP_PORT4_HOTPLUG_SUPPORT,
+										GNB_GPP_PORT4_SPEED_MODE,
+										GNB_GPP_PORT4_SPEED_MODE,
+										GNB_GPP_PORT4_LINK_ASPM,
+										46)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+		/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
 		{
-			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT,
+										GNB_GPP_PORT5_CHANNEL_TYPE,
+										5,
+										GNB_GPP_PORT5_HOTPLUG_SUPPORT,
+										GNB_GPP_PORT5_SPEED_MODE,
+										GNB_GPP_PORT5_SPEED_MODE,
+										GNB_GPP_PORT5_LINK_ASPM,
+										46)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+		/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
 		{
-			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT,
+										GNB_GPP_PORT6_CHANNEL_TYPE,
+										6,
+										GNB_GPP_PORT6_HOTPLUG_SUPPORT,
+										GNB_GPP_PORT6_SPEED_MODE,
+										GNB_GPP_PORT6_SPEED_MODE,
+										GNB_GPP_PORT6_LINK_ASPM,
+										46)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+		/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
 		{
 			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT,
+										GNB_GPP_PORT7_CHANNEL_TYPE,
+										7,
+										GNB_GPP_PORT7_HOTPLUG_SUPPORT,
+										GNB_GPP_PORT7_SPEED_MODE,
+										GNB_GPP_PORT7_SPEED_MODE,
+										GNB_GPP_PORT7_LINK_ASPM,
+										0)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+		/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
 		{
-			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			/* Descriptor flags. IMPORTANT! Terminate last element of array */
+			DESCRIPTOR_TERMINATE_LIST,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT,
+										GNB_GPP_PORT8_CHANNEL_TYPE,
+										8,
+										GNB_GPP_PORT8_HOTPLUG_SUPPORT,
+										GNB_GPP_PORT8_SPEED_MODE,
+										GNB_GPP_PORT8_SPEED_MODE,
+										GNB_GPP_PORT8_LINK_ASPM,
+										0)
 		}
 };
 
+/**
+ * @brief Initialize Ddi descriptors
+ */
 PCIe_DDI_DESCRIPTOR DdiList [] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+		/* (DDI interface Lanes 8:11, DdA, ...) */
 		{
-			0,	 //Descriptor flags
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+			/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */
 			{ConnectorTypeLvds, Aux1, Hdp1}
 		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+		/* (DDI interface Lanes 12:15, DdB, ...) */
 		{
-			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			/* Descriptor flags. IMPORTANT! Terminate last element of array */
+			DESCRIPTOR_TERMINATE_LIST,
 			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-			//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+			/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */
 			{ConnectorTypeDP, Aux2, Hdp2}
 		}
 };
@@ -109,53 +137,61 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 		&DdiList[0]
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
+	/**
+	 * @brief GNB PCIe topology Porting
+	 *
+	 * Allocate buffer for
+	 * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	 */
+	AllocHeapParams.RequestedBufferSize = \
+		sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
 
 	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	if ( Status!= AGESA_SUCCESS) {
-	// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	ASSERT(FALSE);
-	return;
+
+	/**
+	 * Could not allocate buffer for
+	 * PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	 */
+	if (Status!= AGESA_SUCCESS) {
+		ASSERT(FALSE);
+		return;
 	}
 
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+	BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
 	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+	BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
 	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+	BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
-	LibAmdMemFill (BrazosPcieComplexListPtr,
-					 0,
-					 sizeof(Brazos),
-					 &InitEarly->StdHeader);
+	LibAmdMemFill(BrazosPcieComplexListPtr,
+				 0,
+				 sizeof(Brazos),
+				 &InitEarly->StdHeader);
 
-	LibAmdMemFill (BrazosPciePortPtr,
-					 0,
-					 sizeof(PortList),
-					 &InitEarly->StdHeader);
+	LibAmdMemFill(BrazosPciePortPtr,
+				 0,
+				 sizeof(PortList),
+				 &InitEarly->StdHeader);
 
-	LibAmdMemFill (BrazosPcieDdiPtr,
-					 0,
-					 sizeof(DdiList),
-					 &InitEarly->StdHeader);
+	LibAmdMemFill(BrazosPcieDdiPtr,
+				 0,
+				 sizeof(DdiList),
+				 &InitEarly->StdHeader);
 
-	LibAmdMemCopy	(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader);
-	LibAmdMemCopy	(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
-	LibAmdMemCopy	(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
+	LibAmdMemCopy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader);
+	LibAmdMemCopy(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
+	LibAmdMemCopy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
 
 
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+	((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \
+		(PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr;
+	((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = \
+		(PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr;
 
 	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
+	InitEarly->GnbConfig.PsppPolicy = 0;
 }
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
index 47ed1a5..b620d20 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,49 +24,64 @@
 #include <vendorcode/amd/agesa/f14/AGESA.h>
 #include <vendorcode/amd/agesa/f14/Lib/amdlib.h>
 
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/**
+ * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)
+ *
+ * GNB_GPP_PORT?_PORT_PRESENT
+ *  0:Disable 1:Enable
+ *
+ * GNB_GPP_PORT?_SPEED_MODE
+ *  0:Auto 1:GEN1 2:GEN2
+ *
+ * GNB_GPP_PORT?_LINK_ASPM
+ *  0:Disable 1:L0s 2:L1 3:L0s+L1
+ *
+ * GNB_GPP_PORT?_CHANNEL_TYPE -
+ *  0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ *  3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+ *
+ * GNB_GPP_PORT?_HOTPLUG_SUPPORT
+ *  0:Disable 1:Basic 3:Enhanced
+ */
+
+/* GNB GPP 4 */
+#define GNB_GPP_PORT4_PORT_PRESENT		1
+#define GNB_GPP_PORT4_SPEED_MODE		2
+#define GNB_GPP_PORT4_LINK_ASPM			3
+#define GNB_GPP_PORT4_CHANNEL_TYPE		4
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 5 */
+#define GNB_GPP_PORT5_PORT_PRESENT		1
+#define GNB_GPP_PORT5_SPEED_MODE		2
+#define GNB_GPP_PORT5_LINK_ASPM			3
+#define GNB_GPP_PORT5_CHANNEL_TYPE		4
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 6 */
+#define GNB_GPP_PORT6_PORT_PRESENT		1
+#define GNB_GPP_PORT6_SPEED_MODE		2
+#define GNB_GPP_PORT6_LINK_ASPM			3
+#define GNB_GPP_PORT6_CHANNEL_TYPE		4
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT		0	//0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 7 */
+#define GNB_GPP_PORT7_PORT_PRESENT		0
+#define GNB_GPP_PORT7_SPEED_MODE		2
+#define GNB_GPP_PORT7_LINK_ASPM			3
+#define GNB_GPP_PORT7_CHANNEL_TYPE		4
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 8 */
+#define GNB_GPP_PORT8_PORT_PRESENT		1
+#define GNB_GPP_PORT8_SPEED_MODE		2
+#define GNB_GPP_PORT8_LINK_ASPM			3
+#define GNB_GPP_PORT8_CHANNEL_TYPE		4
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT	0
 
 VOID
 OemCustomizeInitEarly (
 	IN	OUT AMD_EARLY_PARAMS	*InitEarly
 	);
 
-#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
+#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
index e7772aa..934ea38 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
@@ -31,7 +31,6 @@
 #define DUMP_ACPI_TABLES 0
 
 #if DUMP_ACPI_TABLES == 1
-
 static void dump_mem(u32 start, u32 end)
 {
 
@@ -45,7 +44,7 @@ static void dump_mem(u32 start, u32 end)
 	}
 	print_debug("\n");
 }
-#endif
+#endif /* DUMP_ACPI_TABLES */
 
 extern const unsigned char AmlCode[];
 
@@ -60,6 +59,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta
 	lens += acpigen_write_name_dword("TOM1", msr.lo);
 	msr = rdmsr(TOP_MEM2);
 	/*
+	 * FIXME: remove this work-around and url.. WinXP is EOL'ed any way.
 	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
 	 * here.
 	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
@@ -124,7 +124,7 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest)
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-	// Not implemented
+	/* Not implemented */
 	return current;
 }
 
@@ -180,7 +180,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	memcpy(dsdt, &AmlCode, dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
-	/* FACS */ // it needs 64 bit alignment
+	/* FACS - it needs 64 bit alignment */
 	current = ALIGN(current, 8);
 	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
 	facs = (acpi_facs_t *) current;
@@ -313,7 +313,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	printk(BIOS_DEBUG, "hest\n");
 	dump_mem(hest, ((void *)hest) + hest->header.length);
-#endif
+#endif /* DUMP_ACPI_TABLES */
 
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
index 1627f25..4a5d9c1 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
@@ -17,11 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/*-----------------------------------------------------------------------------
- *						M O D U L E S		U S E D
- *-----------------------------------------------------------------------------
- */
-
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "PlatformGnbPcieComplex.h"
@@ -41,11 +36,6 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*------------------------------------------------------------------------------
- *					D E F I N I T I O N S		A N D		M A C R O S
- *------------------------------------------------------------------------------
- */
-
 #define MMCONF_ENABLE 1
 
 /* ACPI table pointers returned by AmdInitLate */
@@ -58,25 +48,6 @@ VOID *AcpiWheaMce	= NULL;
 VOID *AcpiWheaCmc	= NULL;
 VOID *AcpiAlib		= NULL;
 
-/*------------------------------------------------------------------------------
- *				T Y P E D E F S		 A N D		 S T R U C T U R E S
- *------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
- *------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- *						E X P O R T E D		F U N C T I O N S
- *------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- *						L O C A L		F U N C T I O N S
- *------------------------------------------------------------------------------
- */
 uint32_t agesawrapper_amdinitcpuio(void)
 {
 	pci_devfn_t dev;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
index 6af5e5f..ee31fcf 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
@@ -17,11 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *						 M O D U L E S		U S E D
- *----------------------------------------------------------------------------------------
- */
-
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
@@ -29,50 +24,28 @@
 #include <vendorcode/amd/agesa/f14/AGESA.h>
 
 
-/*----------------------------------------------------------------------------------------
- *					 D E F I N I T I O N S		A N D		M A C R O S
- *----------------------------------------------------------------------------------------
+/**
+ * Define AMD Ontario APU SSID/SVID
  */
-/* Define AMD Ontario APPU SSID/SVID */
 #define AMD_APU_SVID		0x1022
 #define AMD_APU_SSID		0x1234
 #define PCIE_BASE_ADDRESS	 CONFIG_MMCONF_BASE_ADDRESS
 
 enum {
-	PICK_DMI,		/* DMI Interface */
-	PICK_PSTATE,	/* Acpi Pstate SSDT Table */
-	PICK_SRAT,		/* SRAT Table */
-	PICK_SLIT,		/* SLIT Table */
-	PICK_WHEA_MCE,	/* WHEA MCE table */
-	PICK_WHEA_CMC,	/* WHEA CMV table */
-	PICK_ALIB,		/* SACPI SSDT table with ALIB implementation */
+	PICK_DMI,		/**< DMI Interface */
+	PICK_PSTATE,	/**< Acpi Pstate SSDT Table */
+	PICK_SRAT,		/**< SRAT Table */
+	PICK_SLIT,		/**< SLIT Table */
+	PICK_WHEA_MCE,	/**< WHEA MCE table */
+	PICK_WHEA_CMC,	/**< WHEA CMV table */
+	PICK_ALIB,		/**< SACPI SSDT table with ALIB implementation */
 };
 
-/*----------------------------------------------------------------------------------------
- *					T Y P E D E F S		 A N D		 S T R U C T U	R E S
- *----------------------------------------------------------------------------------------
- */
-
 typedef struct {
 	UINT32 CalloutName;
 	AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
 } BIOS_CALLOUT_STRUCT;
 
-/*----------------------------------------------------------------------------------------
- *		P R O T O T Y P E S		 O F		 L O C A L		 F U	N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *						E X P O R T E D		F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------
- *						L O C A L		F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
 UINT32 agesawrapper_amdinitenv (void);
@@ -92,4 +65,4 @@ void *agesawrapper_getlateinitptr (int pick);
 
 UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader);
 
-#endif
+#endif /* _AGESAWRAPPER_H_ */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index 1491f29..9d84d09 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -30,18 +30,19 @@
 #include <southbridge/amd/cimx/sb800/sb_cimx.h>
 
 
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
+/**
+ * Global variables for mainboard layouts. These are shared by irqtable,
+ * mptable and acpi_tables where busnum is default.
+ */
 u8 bus_isa;
 u8 bus_sb800[6];
 u32 apicid_sb800;
 
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
+/**
+ * Here you only need to set value in pci1234 for HT-IO that could be
+ * installed or not. You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
 u32 pci1234x[] = {
 	0x0000ff0,
 };
@@ -53,7 +54,7 @@ static u32 get_bus_conf_done = 0;
 
 #if CONFIG_HAVE_ACPI_RESUME
 extern u8 acpi_slp_type;
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
 
 void get_bus_conf(void)
 {
@@ -63,26 +64,29 @@ void get_bus_conf(void)
 	device_t dev;
 	int i, j;
 
+	/* Be sure func is called exactly once */
 	if (get_bus_conf_done == 1)
-		return;	 /* do it only once */
+		return;
 
 	get_bus_conf_done = 1;
 
-/*
- * This is the call to AmdInitLate.	It is really in the wrong place, conceptually,
- * but functionally within the coreboot model, this is the best place to make the
- * call.	The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are
- * written into RAM.	The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "main".	There is no platform
- * specific entry point between the S3 resume decision point and the call to
- * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions.	The first of ose would seem to be the right
- * place, but other table write functions, e.g. the PIRQ table write function, are
- * called before the ACPI tables are written.	This routine is called at the beginning
- * of each of the write functions called prior to the ACPI write functions, so this
- * becomes the best place for this call.
+/**
+ * This is the call to AmdInitLate. It is really in the wrong place,
+ * conceptually, but functionally within the coreboot model, this is the best
+ * place to make the call. The logically correct place to call AmdInitLate is
+ * after PCI scan is done, after the decision about S3 resume is made, and
+ * before the system tables are written into RAM. The routine that is
+ * responsible for writing the tables is "write_tables", called near the end of
+ * "main". There is no platform specific entry point between the S3 resume
+ * decision point and the call to "write_tables", and the next platform
+ * specific entry points are the calls to the ACPI table write functions. The
+ * first of ose would seem to be the right place, but other table write
+ * functions, e.g. the PIRQ table write function, are called before the ACPI
+ * tables are written. This routine is called at the beginning of each of the
+ * write functions called prior to the ACPI write functions, so this becomes
+ * the best place for this call.
  */
+
 #if CONFIG_HAVE_ACPI_RESUME
 	if (acpi_slp_type != 3) {
 		status = agesawrapper_amdinitlate();
@@ -96,7 +100,8 @@ void get_bus_conf(void)
 	status = agesawrapper_amdinitlate();
 	if(status)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+
 	sbdn_sb800 = 0;
 
 	memset(bus_sb800, 0, sizeof(bus_sb800));
@@ -142,5 +147,5 @@ void get_bus_conf(void)
 
 #if CONFIG_AMD_SB_CIMX
 	sb_Late_Post();
-#endif
+#endif /* CONFIG_AMD_SB_CIMX */
 }
diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
index b77c375..40fb58f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
@@ -26,9 +26,9 @@
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
+			u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			u8 slot, u8 rfu)
 {
 	pirq_info->bus = bus;
 	pirq_info->devfn = devfn;
@@ -58,15 +58,17 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	u8 sum = 0;
 	int i;
 
+	/* Find all Bus num and APIC's that are share with
+	 * mptable.c and acpi_tables.c
+	 */
+	get_bus_conf();
 
-	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
 
-
-	/* Align the table to be 16 byte aligned. */
+	/* Align table on 16Byte boundary. */
 	addr += 15;
 	addr &= ~15;
 
-	/* This table must be betweeen 0xf0000 & 0x100000 */
+	/* This table must be between 0xf0000 & 0x100000 */
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
@@ -90,19 +92,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq_info = (void *)(&pirq->checksum + 1);
 	slot_num = 0;
 
-
-	/* pci bridge */
+	/* PCI Bridge */
 	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
 			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
 			0);
 	pirq_info++;
 
-
-
 	slot_num++;
 
-
-
 	pirq->size = 32 + 16 * slot_num;
 
 	for (i = 0; i < pirq->size; i++)
@@ -117,5 +114,4 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
-
 }
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index d5f2d03..1d82cb9 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -64,7 +64,7 @@ static void mainboard_enable(device_t dev)
  */
 #if CONFIG_HAVE_ACPI_RESUME
 	acpi_slp_type = acpi_get_sleep_type();
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
 
 	/* enable GPP CLK0 thru CLK3 (interleaved) */
 	/* disable GPP CLK4 thru SLT_GFX_CLK */
@@ -75,7 +75,7 @@ static void mainboard_enable(device_t dev)
 	*(misc_mem_clk_cntrl + 3) = 0x00;
 	*(misc_mem_clk_cntrl + 4) = 0x00;
 
-	/*
+	/**
 	 * Initialize ASF registers to an arbitrary address because someone
 	 * long ago set things up this way inside the SPD read code.  The
 	 * SPD read code has been made generic and moved out of the board
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index d7fe6a0..7a08726 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
 	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
-	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
 	PCI_INT(0x0, 0x14, 0x0, 0x10);
 	/* Southbridge HD Audio: */
 	PCI_INT(0x0, 0x14, 0x2, 0x12);
@@ -107,10 +106,10 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
 	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
 
-	/* sata */
+	/* SATA */
 	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-	/* on board NIC & Slot PCIE.	*/
+	/* On-board NIC & Slot PCIE. */
 
 	/* PCI slots */
 	/* PCI_SLOT 0. */
@@ -119,7 +118,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
 	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
 
-	/* PCI_SLOT 1. */
+	/* On-board Realtek NIC 1. */
 	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
 	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
 	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
@@ -135,7 +134,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
 	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
 
-	/* PCIe PortA */
+	/* On-board Realtek NIC 2. (PCIe PortA) */
 	PCI_INT(0x0, 0x15, 0x0, 0x10);
 	/* PCIe PortB */
 	PCI_INT(0x0, 0x15, 0x1, 0x11);
@@ -144,7 +143,9 @@ static void *smp_write_config_table(void *v)
 	/* PCIe PortD */
 	PCI_INT(0x0, 0x15, 0x3, 0x13);
 
-	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
+	/* Local Ints:
+	 * Type | Polarity | Trigger | Bus ID | IRQ | APIC ID PIN#
+	 */
 	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 846d5c7..3406edf 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
 	}
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
 
 	/* Initialize i8259 pic */
 	post_code(0x43);



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