[coreboot-gerrit] New patch to review for coreboot: abe920c jetway/nf81-t56n-lf: Move pc80 driver from rom to ram stage

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Tue Apr 15 12:47:54 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5509

-gerrit

commit abe920cd3b6a790162f5c65d13e891fc891c6fcb
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Tue Apr 15 20:45:13 2014 +1000

    jetway/nf81-t56n-lf: Move pc80 driver from rom to ram stage
    
    NOTFORMERGE
    
    Avoid #including .c files from pc80 driver by migrating i825{4,9} init's
    from romstage to ramstage.
    
    Change-Id: I4cd87317fb44cd2bda09f3df1c0635cdc87943e2
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 11 +++++++++++
 src/mainboard/jetway/nf81-t56n-lf/romstage.c  | 13 ++-----------
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index b3c9e3d..7904a01 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -31,6 +31,9 @@
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 #include <southbridge/amd/sb800/sb800.h>
 
+#include <pc80/i8254.h>
+#include <pc80/i8259.h>
+
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
 
@@ -58,6 +61,14 @@ static void mainboard_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
+	/* Initialize i8259 pic */
+	post_code(0x43);
+	setup_i8259 ();
+
+	/* Initialize i8254 timers */
+	post_code(0x44);
+	setup_i8254 ();
+
 /*
  * The mainboard is the first place that we get control in ramstage. Check
  * for S3 resume and call the approriate AGESA/CIMx resume functions.
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 3406edf..7ee20c3 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -42,9 +42,8 @@
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 #include "superio/fintek/f71869ad/f71869ad.h"
 
-/* FIXME: should not include .c files */
-#include "drivers/pc80/i8254.c"
-#include "drivers/pc80/i8259.c"
+#include <pc80/i8254.h>
+#include <pc80/i8259.h>
 
 void disable_cache_as_ram(void); /* cache_as_ram.inc */
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
@@ -175,14 +174,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 #endif /* CONFIG_HAVE_ACPI_RESUME */
 
-	/* Initialize i8259 pic */
-	post_code(0x43);
-	setup_i8259 ();
-
-	/* Initialize i8254 timers */
-	post_code(0x44);
-	setup_i8254 ();
-
 	post_code(0x50);
 	copy_and_run();
 	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");



More information about the coreboot-gerrit mailing list