[coreboot-gerrit] Patch set updated for coreboot: 36497a8 hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18

Alexandru Gagniuc (mr.nuke.me@gmail.com) gerrit at coreboot.org
Sun Apr 20 22:00:39 CEST 2014


Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5556

-gerrit

commit 36497a8aaf3b1767dddb74a1eda86026ee5be96d
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Sat Apr 19 16:22:53 2014 -0500

    hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
    
    The PCIE PME pin from the APU is connected to GEVENT8, but the
    northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
    accordingly.
    
    Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 10 ++++------
 src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c  |  1 +
 src/mainboard/hp/pavilion_m6_1035dx/mainboard.h  |  2 ++
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
index 93c46ae..3bf0721 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
+++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
@@ -65,12 +65,10 @@ Scope(\_GPE) {	/* Start Scope GPE */
 
 	/*  GPIO0 or GEvent8 event  */
 	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Store("PCI bridge wake event", Debug)
+		/* Notify PCI bridges of wake event */
+		Notify(\_SB.PCI0.PBR4, 0x02)
+		Notify(\_SB.PCI0.PBR5, 0x02)
 	}
 
 	/*  Azalia SCI event  */
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 8b48476..df0f8fd 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -386,6 +386,7 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = {
 SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
 	{GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
 	{GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE},
+	{GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE},
 	{SCI_MAP_OHCI_12_0, PME_GPE},
 	{SCI_MAP_OHCI_13_0, PME_GPE},
 	{SCI_MAP_XHCI_10_0, PME_GPE},
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h
index 8e51a77..95febb7 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h
@@ -12,6 +12,7 @@
 #define EC_SCI_GEVENT		3
 #define EC_LID_GEVENT		22
 #define EC_SMI_GEVENT		23
+#define PCIE_GEVENT		8
 
 /* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but
  * we make the distinction between GEVENT pin and SCI.
@@ -19,5 +20,6 @@
 #define EC_SCI_GPE 		EC_SCI_GEVENT
 #define EC_LID_GPE		EC_LID_GEVENT
 #define PME_GPE			0x0b
+#define PCIE_GPE		0x18
 
 #endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H   */



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