[coreboot-gerrit] New patch to review for coreboot: 549f69b superio/ite/it8721f: Rewrite sio from hardcoded base addr
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Mon Apr 21 09:13:15 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5560
-gerrit
commit 549f69b223440660415cbbda931762e2bb2da399
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Mon Apr 21 17:10:00 2014 +1000
superio/ite/it8721f: Rewrite sio from hardcoded base addr
I'll wait for Pauls insight
Change-Id: I52211cfb833af53efd8e00fd2a634808c0a92915
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/asus/m5a88-v/romstage.c | 2 +-
src/superio/ite/it8721f/Makefile.inc | 2 +-
src/superio/ite/it8721f/early_serial.c | 53 ++++++++++------------------------
src/superio/ite/it8721f/it8721f.h | 11 +++----
4 files changed, 21 insertions(+), 47 deletions(-)
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index db8b7b5..94a1e4e 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -41,7 +41,7 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/ite/it8721f/early_serial.c"
+#include <superio/ite/it8721f/it8721f.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc
index 712d020..ef616f4 100644
--- a/src/superio/ite/it8721f/Makefile.inc
+++ b/src/superio/ite/it8721f/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_ITE_IT8721F) += early_serial.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c
-
diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c
index 20e19b6..a820e79 100644
--- a/src/superio/ite/it8721f/early_serial.c
+++ b/src/superio/ite/it8721f/early_serial.c
@@ -20,30 +20,24 @@
*/
#include <arch/io.h>
+#include <device/pnp.h>
#include "it8721f.h"
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
/* Global configuration registers. */
#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-static void it8721f_sio_write(u8 ldn, u8 index, u8 value)
+static void it8721f_sio_write(device_t dev, u8 index, u8 value)
{
- outb(IT8721F_CONFIG_REG_LDN, SIO_BASE);
- outb(ldn, SIO_DATA);
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
+ pnp_set_logical_device(dev);
+ pnp_write_config(dev, index, value);
}
-static void it8721f_enter_conf(void)
+static void it8721f_enter_conf(device_t dev)
{
- u16 port = 0x2e; /* TODO: Don't hardcode! */
+ u16 port = dev >> 8;
outb(0x87, port);
outb(0x01, port);
@@ -54,40 +48,23 @@ static void it8721f_enter_conf(void)
static void it8721f_exit_conf(void)
{
it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CC, 0x02);
+ it8721f_sio_write(dev, IT8728F_CONFIG_REG_CC, 0x02);
}
/* Select 24MHz CLKIN (48MHz default). */
-void it8721f_24mhz_clkin(void)
+void it8721f_24mhz_clkin(device_t dev)
{
- it8721f_enter_conf();
- it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CLOCKSEL, 0x1);
- it8721f_exit_conf();
+ it8721f_reg_write(dev, IT8728F_CONFIG_REG_CLOCKSEL, 0x1);
}
/* Enable the serial port(s). */
void it8721f_enable_serial(device_t dev, u16 iobase)
{
- /* (1) Enter the configuration state (MB PnP mode). */
- it8721f_enter_conf();
-
- /* (2) Modify the data of configuration registers. */
-
- /*
- * Select the chip to configure (if there's more than one).
- * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- * If this register is not written, both chips are configured.
- */
-
- /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
-
- /* Enable serial port(s). */
- it8721f_sio_write(IT8721F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8721f_sio_write(IT8721F_SP2, 0x30, 0x1); /* Serial port 2 */
-
- /* Clear software suspend mode (clear bit 0). TODO: Needed? */
- /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
-
- /* (3) Exit the configuration state (MB PnP mode). */
- it8721f_exit_conf();
+ it8721f_enter_conf(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ it8721f_exit_conf(dev);
}
diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h
index 25300e6..1706449 100644
--- a/src/superio/ite/it8721f/it8721f.h
+++ b/src/superio/ite/it8721f/it8721f.h
@@ -19,8 +19,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SUPERIO_ITE_IT8721F_IT8721F_H
-#define SUPERIO_ITE_IT8721F_IT8721F_H
+#ifndef SUPERIO_ITE_IT8721F_H
+#define SUPERIO_ITE_IT8721F_H
#define IT8721F_FDC 0x00 /* Floppy */
#define IT8721F_SP1 0x01 /* Com1 */
@@ -32,10 +32,7 @@
#define IT8721F_GPIO 0x07 /* GPIO */
#define IT8721F_IR 0x0a /* Consumer IR */
-#if defined(__PRE_RAM__)
-void it8721f_24mhz_clkin(void);
-void it8721f_disable_reboot(void);
+void it8721f_24mhz_clkin(device_t dev);
void it8721f_enable_serial(device_t dev, u16 iobase);
-#endif
-#endif
+#endif /* SUPERIO_ITE_IT8721F_H */
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