[coreboot-gerrit] Patch set updated for coreboot: 780f431 superio/winbond/w83627ehg: Convert romstage to generic component

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Sun Apr 27 15:48:49 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5589

-gerrit

commit 780f431ab134ef5b3480260bb5bdaf691551b5ea
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sun Apr 27 23:28:31 2014 +1000

    superio/winbond/w83627ehg: Convert romstage to generic component
    
    Convert the serial init to the generic romstage component and
    corresponding boards using this sio.
    
    Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/asus/a8v-e_deluxe/romstage.c   |  3 ++-
 src/mainboard/asus/a8v-e_se/romstage.c       |  3 ++-
 src/mainboard/ibase/mb899/romstage.c         |  1 +
 src/mainboard/iei/pm-lx-800-r11/romstage.c   |  3 ++-
 src/mainboard/msi/ms7260/romstage.c          |  3 ++-
 src/mainboard/msi/ms9282/romstage.c          |  3 ++-
 src/mainboard/msi/ms9652_fam10/romstage.c    |  3 ++-
 src/superio/winbond/common/winbond.h         | 29 ++++++++++++++++++++++++++++
 src/superio/winbond/common/winbound.h        | 29 ----------------------------
 src/superio/winbond/w83627ehg/early_serial.c | 10 ----------
 src/superio/winbond/w83627ehg/w83627ehg.h    |  7 +++----
 11 files changed, 45 insertions(+), 49 deletions(-)

diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index efc4ac7..6a90fc1 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
@@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	struct sys_info *sysinfo = &sysinfo_car;
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 19f5686..0ea9aa6 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
@@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	struct sys_info *sysinfo = &sysinfo_car;
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 64df82e..d50f8c6 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -27,6 +27,7 @@
 #include <cpu/x86/lapic.h>
 #include <lib.h>
 #include <cbmem.h>
+#include <superio/winbond/common/winbond.h>
 #include "superio/winbond/w83627ehg/w83627ehg.h"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c
index f996301..bf34e9a 100644
--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c
+++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c
@@ -32,6 +32,7 @@
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <southbridge/amd/cs5536/early_smbus.c>
 #include <southbridge/amd/cs5536/early_setup.c>
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include <northbridge/amd/lx/raminit.h>
 
@@ -63,7 +64,7 @@ void main(unsigned long bist)
 
 	cs5536_early_setup();
 
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	report_bist_failure(bist);
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 68feb3b..3c5331f 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -37,6 +37,7 @@
 #include <spd.h>
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
@@ -122,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pnp_enter_ext_func_mode(SERIAL_DEV);
 	/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
 	pnp_write_config(SERIAL_DEV, 0x24, 0);
-	w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbound_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
 	setup_mb_resource_map();
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 19592f3..513ac77 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -37,6 +37,7 @@
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "cpu/x86/bist.h"
 #include <spd.h>
@@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }
 
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index ad7dcde..44bfea5 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -39,6 +39,7 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdfam10/reset_test.c"
+#include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -126,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h
new file mode 100644
index 0000000..71def7f
--- /dev/null
+++ b/src/superio/winbond/common/winbond.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_WINBOUND_COMMON_ROMSTAGE_H
+#define SUPERIO_WINBOUND_COMMON_ROMSTAGE_H
+
+#include <arch/io.h>
+#include <stdint.h>
+
+void winbound_enable_serial(device_t dev, u16 iobase);
+
+#endif /* SUPERIO_WINBOUND_COMMON_ROMSTAGE_H */
diff --git a/src/superio/winbond/common/winbound.h b/src/superio/winbond/common/winbound.h
deleted file mode 100644
index 71def7f..0000000
--- a/src/superio/winbond/common/winbound.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef SUPERIO_WINBOUND_COMMON_ROMSTAGE_H
-#define SUPERIO_WINBOUND_COMMON_ROMSTAGE_H
-
-#include <arch/io.h>
-#include <stdint.h>
-
-void winbound_enable_serial(device_t dev, u16 iobase);
-
-#endif /* SUPERIO_WINBOUND_COMMON_ROMSTAGE_H */
diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c
index 84eb127..346d6cf 100644
--- a/src/superio/winbond/w83627ehg/early_serial.c
+++ b/src/superio/winbond/w83627ehg/early_serial.c
@@ -35,13 +35,3 @@ void pnp_exit_ext_func_mode(device_t dev)
 	u16 port = dev >> 8;
 	outb(0xaa, port);
 }
-
-void w83627ehg_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h
index e574cf3..02041fc 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg.h
+++ b/src/superio/winbond/w83627ehg/w83627ehg.h
@@ -19,8 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H
-#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H
+#ifndef SUPERIO_WINBOND_W83627EHG_H
+#define SUPERIO_WINBOND_W83627EHG_H
 
 #define W83627EHG_FDC              0   /* Floppy */
 #define W83627EHG_PP               1   /* Parallel port */
@@ -57,10 +57,9 @@
 #if defined(__PRE_RAM__)
 void w83627ehg_enable_dev(device_t dev, u16 iobase);
 void w83627ehg_disable_dev(device_t dev);
-void w83627ehg_enable_serial(device_t dev, u16 iobase);
 #endif
 
 void pnp_enter_ext_func_mode(device_t dev);
 void pnp_exit_ext_func_mode(device_t dev);
 
-#endif /* SUPERIO_WINBOND_W83627EHG_W83627EHG_H */
+#endif /* SUPERIO_WINBOND_W83627EHG_H */



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