[coreboot-gerrit] Patch set updated for coreboot: a782af1 mainboard/*: Avoid including early_serial.c from w83627hf

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Tue Apr 29 04:27:28 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5597

-gerrit

commit a782af1599b62d7547975f67a7b5a3f6112707ce
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Mon Apr 28 18:07:33 2014 +1000

    mainboard/*: Avoid including early_serial.c from w83627hf
    
    Following the reasoning of:
    dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c
    
    Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/a-trend/atc-6240/romstage.c            | 5 +++--
 src/mainboard/amd/db800/romstage.c                   | 5 +++--
 src/mainboard/amd/rumba/Kconfig                      | 1 +
 src/mainboard/amd/rumba/romstage.c                   | 5 +++--
 src/mainboard/amd/serengeti_cheetah/romstage.c       | 7 ++++---
 src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 5 +++--
 src/mainboard/asus/dsbf/romstage.c                   | 5 +++--
 src/mainboard/digitallogic/adl855pc/romstage.c       | 7 ++++---
 src/mainboard/digitallogic/msm800sev/romstage.c      | 5 +++--
 src/mainboard/hp/dl145_g1/romstage.c                 | 5 +++--
 src/mainboard/iei/pcisa-lx-800-r10/romstage.c        | 5 +++--
 src/mainboard/iwill/dk8_htx/romstage.c               | 7 ++++---
 src/mainboard/iwill/dk8s2/romstage.c                 | 7 ++++---
 src/mainboard/iwill/dk8x/romstage.c                  | 7 ++++---
 src/mainboard/lippert/frontrunner/Kconfig            | 1 +
 src/mainboard/lippert/frontrunner/romstage.c         | 5 +++--
 src/mainboard/newisys/khepri/romstage.c              | 7 ++++---
 src/mainboard/supermicro/x7db8/romstage.c            | 8 +++++---
 src/mainboard/tyan/s2735/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s2850/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s2875/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s2880/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s2881/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s2882/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s2885/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s2891/romstage.c                  | 5 +++--
 src/mainboard/tyan/s2892/romstage.c                  | 5 +++--
 src/mainboard/tyan/s2912/romstage.c                  | 6 +++---
 src/mainboard/tyan/s2912_fam10/romstage.c            | 6 +++---
 src/mainboard/tyan/s4880/romstage.c                  | 7 ++++---
 src/mainboard/tyan/s4882/romstage.c                  | 7 ++++---
 31 files changed, 106 insertions(+), 76 deletions(-)

diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c
index 9e4b35b..41d5d2a 100644
--- a/src/mainboard/a-trend/atc-6240/romstage.c
+++ b/src/mainboard/a-trend/atc-6240/romstage.c
@@ -30,7 +30,8 @@
 #include "drivers/pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/bist.h"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
@@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 
 void main(unsigned long bist)
 {
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	report_bist_failure(bist);
 
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 93fc0e5..564380e 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -32,7 +32,8 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/lx/raminit.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -63,7 +64,7 @@ void main(unsigned long bist)
 	/* Note: must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig
index d600a58..1d60d0c 100644
--- a/src/mainboard/amd/rumba/Kconfig
+++ b/src/mainboard/amd/rumba/Kconfig
@@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
+	select SUPERIO_WINBOND_W83627HF
 	select UDELAY_TSC
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index cec7c36..c5a3fc3 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -4,7 +4,8 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>
@@ -38,7 +39,7 @@ void main(unsigned long bist)
 
 	SystemPreInit();
 
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	cs5536_early_setup();
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index b103389..14320a5 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -15,7 +15,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include <cpu/amd/mtrr.h>
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
@@ -113,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index bb7d5d3..09b86bb 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -44,7 +44,8 @@
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdfam10/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
@@ -204,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x32);
 
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c
index f4e65cb..e013371 100644
--- a/src/mainboard/asus/dsbf/romstage.c
+++ b/src/mainboard/asus/dsbf/romstage.c
@@ -29,7 +29,8 @@
 #include <lib.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-#include <superio/winbond/w83627hf/early_serial.c>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include <northbridge/intel/i5000/raminit.h>
 #include "northbridge/intel/i3100/i3100.h"
 #include "southbridge/intel/i3100/i3100.h"
@@ -116,7 +117,7 @@ void main(unsigned long bist)
 
 	i5000_lpc_config();
 
-	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
+	winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
 
 	console_init();
 
diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index 7eefedd..5935af2 100644
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -11,7 +11,8 @@
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "northbridge/intel/i855/raminit.h"
 #include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include <spd.h>
 
@@ -34,8 +35,8 @@ void main(unsigned long bist)
 #endif
 	}
 
-        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index b96f8ae..986e918 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -13,7 +13,8 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/lx/raminit.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -46,7 +47,7 @@ void main(unsigned long bist)
 	 * for cs5536
 	 */
 	cs5536_disable_internal_uart();
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index a5df58d..2b42e73 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -17,7 +17,8 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
@@ -113,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
 
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 1cbe32d..a75691c 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -32,7 +32,8 @@
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
 #include "southbridge/amd/cs5536/early_setup.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/lx/raminit.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -63,7 +64,7 @@ void main(unsigned long bist)
 	/* Note: must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for CS5536.
 	 */
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 070fb07..a429568 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -13,7 +13,8 @@
 #include "cpu/x86/bist.h"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
@@ -82,8 +83,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 7c8d4a5..d2371b5 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -13,7 +13,8 @@
 #include "cpu/x86/bist.h"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
@@ -83,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index b5a1d71..50869f7 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -13,7 +13,8 @@
 #include "cpu/x86/bist.h"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
@@ -83,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig
index ba1d5f1..422cded 100644
--- a/src/mainboard/lippert/frontrunner/Kconfig
+++ b/src/mainboard/lippert/frontrunner/Kconfig
@@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select CPU_AMD_GEODE_GX2
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5535
+	select SUPERIO_WINBOND_W83627HF
 	select HAVE_DEBUG_SMBUS
 	select UDELAY_TSC
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index bdbf059..92a3a99 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -5,7 +5,8 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>
@@ -80,7 +81,7 @@ void main(unsigned long bist)
 	SystemPreInit();
 	msr_init();
 
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	cs5535_early_setup();
diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index 652104a..b34882e 100644
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -20,7 +20,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -82,8 +83,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
                 bsp_apicid = init_cpus(cpu_init_detectedx);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
index bc54ed7..791028e 100644
--- a/src/mainboard/supermicro/x7db8/romstage.c
+++ b/src/mainboard/supermicro/x7db8/romstage.c
@@ -29,7 +29,8 @@
 #include <lib.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-#include <superio/winbond/w83627hf/early_serial.c>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include <northbridge/intel/i5000/raminit.h>
 #include "northbridge/intel/i3100/i3100.h"
 #include "southbridge/intel/i3100/i3100.h"
@@ -43,6 +44,8 @@
 #define RCBA_GCS   0x3410 /* 32 bit */
 #define RCBA_FD    0x3418 /* 32 bit */
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static void early_config(void)
 {
 	u32 gcs, rpc, fd;
@@ -115,8 +118,7 @@ void main(unsigned long bist)
 
 	i5000_lpc_config();
 
-	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);
-
+	winbond_enable_serial(SERIAL_DEV, 0x3f8);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index 4e71559..600d806 100644
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -11,7 +11,8 @@
 #include "southbridge/intel/i82801ex/early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "northbridge/intel/e7501/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -47,8 +48,8 @@ void main(unsigned long bist)
 	if (bist == 0)
 		enable_lapic();
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 301f81c..952b19d 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -15,7 +15,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -75,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	post_code(0x32);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 7c9f93a..8f87257 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -15,7 +15,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		init_cpus(cpu_init_detectedx);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index 13cc01e..873652b 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -15,7 +15,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		init_cpus(cpu_init_detectedx);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index dad2b6b..c020f3e 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -14,7 +14,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -73,8 +74,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	post_code(0x32);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index 13cc01e..873652b 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -15,7 +15,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		init_cpus(cpu_init_detectedx);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index a2dc990..df602ea 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -14,7 +14,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -71,8 +72,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
                 bsp_apicid = init_cpus(cpu_init_detectedx);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index aa0385b..e97b026 100644
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -16,7 +16,8 @@
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
@@ -94,7 +95,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	post_code(0x32);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index 5d6ff2a..57da072 100644
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -16,7 +16,8 @@
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
@@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //	post_code(0x32);
 
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index e4a1c65..55cb95e 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -36,8 +36,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	setup_mb_resource_map();
 
 	console_init();
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 9c86157..6dae693 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -39,8 +39,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdfam10/debug.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x32);
 
-	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 
 	/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 2b6470c..543fcf0 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -14,7 +14,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -131,8 +132,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
 		init_cpus(cpu_init_detectedx);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index 60dbdf8..b4100fb 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -13,7 +13,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
@@ -110,8 +111,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         if (bist == 0)
                 bsp_apicid = init_cpus(cpu_init_detectedx);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);



More information about the coreboot-gerrit mailing list