[coreboot-gerrit] New patch to review for coreboot: bb5ea7b mainboard/*: Use generic winbond romstage in place of w83627thg
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Tue Apr 29 06:06:27 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5603
-gerrit
commit bb5ea7bbc710ddfd0537f9632de1dd386b57b917
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Apr 29 13:59:54 2014 +1000
mainboard/*: Use generic winbond romstage in place of w83627thg
Use the generic implementation of winbond in place of the model specific
w83627thg_enable_serial() as so that it maybe removed later.
Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/lanner/em8510/romstage.c | 5 +++--
src/mainboard/msi/ms7135/romstage.c | 3 ++-
src/mainboard/winent/mb6047/romstage.c | 3 ++-
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index 335f9ec..4ae5c12 100644
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -34,6 +34,7 @@
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "northbridge/intel/i855/raminit.h"
#include "northbridge/intel/i855/debug.c"
+#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include "cpu/x86/bist.h"
@@ -56,8 +57,8 @@ void main(unsigned long bist)
#endif
}
- w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index ccb420a..15c02f5 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -31,6 +31,7 @@
#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
@@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c
index 07f235c..a725beb 100644
--- a/src/mainboard/winent/mb6047/romstage.c
+++ b/src/mainboard/winent/mb6047/romstage.c
@@ -16,6 +16,7 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
+#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -84,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// post_code(0x32);
- w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
More information about the coreboot-gerrit
mailing list