[coreboot-gerrit] Patch set updated for coreboot: ec126ff mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Wed Apr 30 20:04:11 CEST 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5610

-gerrit

commit ec126ff728720d212605120cbe5f6c1f2b60dc65
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Tue Apr 29 17:49:35 2014 +1000

    mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
    
    Provide local superio pnp_ programming entry/exit functions as to avoid
    making superio implementation global symbols. Although this is not the
    proper/final solution, it does mitigate possibly symbol collisions and
    allow for continued superio refactorisation.
    
    Change-Id: I5d3421ff9a12413da1e570c09d507206f3f09641
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/supermicro/h8qme_fam10/romstage.c | 22 ++++++++++++++++++----
 src/superio/winbond/w83627hf/Makefile.inc       |  2 +-
 src/superio/winbond/w83627hf/w83627hf.h         |  2 +-
 3 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index cca464c..9898a25 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -39,8 +39,8 @@
 #include "lib/delay.c"
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdfam10/debug.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -114,6 +114,20 @@ static const u8 spd_addr[] = {
 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
 
+/* TODO: superio code should really not be in mainboard */
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0x87, port);
+	outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0xaa, port);
+}
+
 static void write_GPIO(void)
 {
 	pnp_enter_ext_func_mode(GPIO1_DEV);
@@ -172,8 +186,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
   post_code(0x32);
 
- 	w83627hf_set_clksel_48(DUMMY_DEV);
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83627hf_set_clksel_48(DUMMY_DEV);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
 	console_init();
 	write_GPIO();
diff --git a/src/superio/winbond/w83627hf/Makefile.inc b/src/superio/winbond/w83627hf/Makefile.inc
index be5ec48..f942ccb 100644
--- a/src/superio/winbond/w83627hf/Makefile.inc
+++ b/src/superio/winbond/w83627hf/Makefile.inc
@@ -20,5 +20,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.c
-
diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h
index 468cb55..2ad1061 100644
--- a/src/superio/winbond/w83627hf/w83627hf.h
+++ b/src/superio/winbond/w83627hf/w83627hf.h
@@ -113,7 +113,7 @@
 #define W83627HF_XSCNF		0x15
 #define W83627HF_XWBCNF		0x16
 
-#if defined(__PRE_RAM__)
+#ifndef __ROMCC__
 void w83627hf_disable_dev(device_t dev);
 void w83627hf_enable_dev(device_t dev, u16 iobase);
 void w83627hf_enable_serial(device_t dev, u16 iobase);



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