[coreboot-gerrit] New patch to review for coreboot: 0152603 intel 'i440bx.h' & 'i440lx.h': Add missing header guards

HAOUAS Elyes (ehaouas@noos.fr) gerrit at coreboot.org
Fri Aug 1 14:23:37 CEST 2014


HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6450

-gerrit

commit 0152603927be43045a5c08156db2c2a37280098f
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Fri Aug 1 14:22:26 2014 +0200

    intel 'i440bx.h' & 'i440lx.h': Add missing header guards
    
    Change-Id: I1ebec4e76505529d514853174e2c00088a2106b4
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/northbridge/intel/i440bx/i440bx.h | 5 +++++
 src/northbridge/intel/i440lx/i440lx.h | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h
index 149517a..ae4b753 100644
--- a/src/northbridge/intel/i440bx/i440bx.h
+++ b/src/northbridge/intel/i440bx/i440bx.h
@@ -33,6 +33,9 @@
  * Reserved or Intel Reserved and should not be touched.
  */
 
+#ifndef I440BX_H
+#define I440BX_H
+
 #define NBXCFG  0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */
 #define DRAMC   0x57 /* DRAM Control (00S0_0000b). */
 #define DRAMT   0x58 /* DRAM Timing (0x03). */
@@ -86,3 +89,5 @@
 #define DWTC    0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */
 #define DRTC    0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
 #define BUFFC   0xf0 /* Buffer Control Register (0x0000). */
+
+#endif /* I440BX_H */
diff --git a/src/northbridge/intel/i440lx/i440lx.h b/src/northbridge/intel/i440lx/i440lx.h
index 47d5b52..76abb47 100644
--- a/src/northbridge/intel/i440lx/i440lx.h
+++ b/src/northbridge/intel/i440lx/i440lx.h
@@ -35,6 +35,10 @@
  *
  * Reserved or Intel Reserved and should not be touched.
  */
+
+#ifndef I440LX_H
+#define I440LX_H
+
 #define APBASE	0x34 /* Aperture Base Address (0x00000008) */
 #define PACCFG	0x50 /* 440LX PAC Configuration Register (0s00_s000_0000_0s00b) */
 #define DBC	0x53 /* DRAM Row Type Register (0x83) */
@@ -70,3 +74,5 @@
 #define PAM4    0x5d
 #define PAM5    0x5e
 #define PAM6    0x5f
+
+#endif /* I440LX_H */



More information about the coreboot-gerrit mailing list