[coreboot-gerrit] Patch set updated for coreboot: a7285b1 reg_scripts: move them to soc/intel/baytrail
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Mon Aug 4 20:55:01 CEST 2014
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6298
-gerrit
commit a7285b1a1b6b4fd0f6cb8d963cc4667b072b2f28
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Wed Jul 16 19:39:02 2014 +0200
reg_scripts: move them to soc/intel/baytrail
The baytrail code is the only user of this API, and with
its #if CONFIG_$CONCRETE_HARDWARE blocks, it was a bit
of a sore spot in src/lib.
Change-Id: I10f5f74188aa83f2e747503b5cd4b28dba5f4012
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/Kconfig | 7 -
src/include/reg_script.h | 339 ----------------------
src/lib/Makefile.inc | 2 -
src/lib/reg_script.c | 551 ------------------------------------
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/reg_script.c | 538 +++++++++++++++++++++++++++++++++++
src/soc/intel/baytrail/reg_script.h | 339 ++++++++++++++++++++++
src/soc/intel/fsp_baytrail/Kconfig | 1 -
8 files changed, 878 insertions(+), 900 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index af82353..ecc2757 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1102,13 +1102,6 @@ config POWER_BUTTON_IS_OPTIONAL
help
Internal option that controls ENABLE_POWER_BUTTON visibility.
-config REG_SCRIPT
- bool
- default y if ARCH_X86
- default n
- help
- Internal option that controls whether we compile in register scripts.
-
# Maximum reboot count
# TODO: Improve description.
config MAX_REBOOT_CNT
diff --git a/src/include/reg_script.h b/src/include/reg_script.h
deleted file mode 100644
index 72e1e96..0000000
--- a/src/include/reg_script.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef REG_SCRIPT_H
-#define REG_SCRIPT_H
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/resource.h>
-
-/*
- * The reg script library is a way to provide data-driven I/O accesses for
- * initializing devices. It currently supports PCI, legacy I/O,
- * memory-mapped I/O, and IOSF accesses.
- *
- * In order to simplify things for the developer the following features
- * are employed:
- * - Chaining of tables that allow runtime tables to chain to compile-time
- * tables.
- * - Notion of current device (device_t) being worked on. This allows for
- * PCI config, io, and mmio on a particular device's resources.
- *
- * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
- * and pop of the context. A chained reg_script inherits the previous
- * context (such as current device), but it does not impact the previous
- * context in any way.
- */
-
-enum {
- REG_SCRIPT_COMMAND_READ,
- REG_SCRIPT_COMMAND_WRITE,
- REG_SCRIPT_COMMAND_RMW,
- REG_SCRIPT_COMMAND_POLL,
- REG_SCRIPT_COMMAND_SET_DEV,
- REG_SCRIPT_COMMAND_NEXT,
- REG_SCRIPT_COMMAND_END,
-};
-
-enum {
- REG_SCRIPT_TYPE_PCI,
- REG_SCRIPT_TYPE_IO,
- REG_SCRIPT_TYPE_MMIO,
- REG_SCRIPT_TYPE_RES,
- REG_SCRIPT_TYPE_IOSF,
- REG_SCRIPT_TYPE_MSR,
-};
-
-enum {
- REG_SCRIPT_SIZE_8,
- REG_SCRIPT_SIZE_16,
- REG_SCRIPT_SIZE_32,
- REG_SCRIPT_SIZE_64,
-};
-
-struct reg_script {
- uint32_t command;
- uint32_t type;
- uint32_t size;
- uint32_t reg;
- uint64_t mask;
- uint64_t value;
- uint32_t timeout;
- union {
- uint32_t id;
- const struct reg_script *next;
- device_t dev;
- unsigned int res_index;
- };
-};
-
-/* Internal helper Macros. */
-
-#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
- mask_, value_, timeout_, id_) \
- { .command = cmd_, \
- .type = type_, \
- .size = size_, \
- .reg = reg_, \
- .mask = mask_, \
- .value = value_, \
- .timeout = timeout_, \
- .id = id_, \
- }
-
-#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
- mask_, value_, timeout_) \
- { .command = cmd_, \
- .type = type_, \
- .size = size_, \
- .reg = reg_, \
- .mask = mask_, \
- .value = value_, \
- .timeout = timeout_, \
- .res_index = res_index_, \
- }
-
-/*
- * PCI
- */
-
-#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
- _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
- REG_SCRIPT_TYPE_PCI, \
- REG_SCRIPT_SIZE_##bits_, \
- reg_, mask_, value_, timeout_, 0)
-#define REG_PCI_READ8(reg_) \
- REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
-#define REG_PCI_READ16(reg_) \
- REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
-#define REG_PCI_READ32(reg_) \
- REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
-#define REG_PCI_WRITE8(reg_, value_) \
- REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
-#define REG_PCI_WRITE16(reg_, value_) \
- REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
-#define REG_PCI_WRITE32(reg_, value_) \
- REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
-#define REG_PCI_RMW8(reg_, mask_, value_) \
- REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
-#define REG_PCI_RMW16(reg_, mask_, value_) \
- REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
-#define REG_PCI_RMW32(reg_, mask_, value_) \
- REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
-#define REG_PCI_OR8(reg_, value_) \
- REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
-#define REG_PCI_OR16(reg_, value_) \
- REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
-#define REG_PCI_OR32(reg_, value_) \
- REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
-#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
-#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
-#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
-
-/*
- * Legacy IO
- */
-
-#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
- _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
- REG_SCRIPT_TYPE_IO, \
- REG_SCRIPT_SIZE_##bits_, \
- reg_, mask_, value_, timeout_, 0)
-#define REG_IO_READ8(reg_) \
- REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
-#define REG_IO_READ16(reg_) \
- REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
-#define REG_IO_READ32(reg_) \
- REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
-#define REG_IO_WRITE8(reg_, value_) \
- REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
-#define REG_IO_WRITE16(reg_, value_) \
- REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
-#define REG_IO_WRITE32(reg_, value_) \
- REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
-#define REG_IO_RMW8(reg_, mask_, value_) \
- REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
-#define REG_IO_RMW16(reg_, mask_, value_) \
- REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
-#define REG_IO_RMW32(reg_, mask_, value_) \
- REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
-#define REG_IO_OR8(reg_, value_) \
- REG_SCRIPT_IO_RMW8(_reg, 0xff, value)
-#define REG_IO_OR16(reg_, value_) \
- REG_SCRIPT_IO_RMW16(_reg, 0xffff, value)
-#define REG_IO_OR32(reg_, value_) \
- REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value)
-#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
-#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
-#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
-
-/*
- * Memory Mapped IO
- */
-
-#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
- _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
- REG_SCRIPT_TYPE_MMIO, \
- REG_SCRIPT_SIZE_##bits_, \
- reg_, mask_, value_, timeout_, 0)
-#define REG_MMIO_READ8(reg_) \
- REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
-#define REG_MMIO_READ16(reg_) \
- REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
-#define REG_MMIO_READ32(reg_) \
- REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
-#define REG_MMIO_WRITE8(reg_, value_) \
- REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
-#define REG_MMIO_WRITE16(reg_, value_) \
- REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
-#define REG_MMIO_WRITE32(reg_, value_) \
- REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
-#define REG_MMIO_RMW8(reg_, mask_, value_) \
- REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
-#define REG_MMIO_RMW16(reg_, mask_, value_) \
- REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
-#define REG_MMIO_RMW32(reg_, mask_, value_) \
- REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
-#define REG_MMIO_OR8(reg_, value_) \
- REG_MMIO_RMW8(reg_, 0xff, value_)
-#define REG_MMIO_OR16(reg_, value_) \
- REG_MMIO_RMW16(reg_, 0xffff, value_)
-#define REG_MMIO_OR32(reg_, value_) \
- REG_MMIO_RMW32(reg_, 0xffffffff, value_)
-#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
-#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
-#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
-
-/*
- * Access through a device's resource such as a Base Address Register (BAR)
- */
-
-#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
- _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \
- REG_SCRIPT_TYPE_RES, bar_, \
- REG_SCRIPT_SIZE_##bits_, \
- reg_, mask_, value_, timeout_)
-#define REG_RES_READ8(bar_, reg_) \
- REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
-#define REG_RES_READ16(bar_, reg_) \
- REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
-#define REG_RES_READ32(bar_, reg_) \
- REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
-#define REG_RES_WRITE8(bar_, reg_, value_) \
- REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
-#define REG_RES_WRITE16(bar_, reg_, value_) \
- REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
-#define REG_RES_WRITE32(bar_, reg_, value_) \
- REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
-#define REG_RES_RMW8(bar_, reg_, mask_, value_) \
- REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
-#define REG_RES_RMW16(bar_, reg_, mask_, value_) \
- REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
-#define REG_RES_RMW32(bar_, reg_, mask_, value_) \
- REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
-#define REG_RES_OR8(bar_, reg_, value_) \
- REG_RES_RMW8(bar_, reg_, 0xff, value_)
-#define REG_RES_OR16(bar_, reg_, value_) \
- REG_RES_RMW16(bar_, reg_, 0xffff, value_)
-#define REG_RES_OR32(bar_, reg_, value_) \
- REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
-#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
- REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
-#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
- REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
-#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
- REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
-
-/*
- * IO Sideband Function
- */
-
-#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
- _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
- REG_SCRIPT_TYPE_IOSF, \
- REG_SCRIPT_SIZE_32, \
- reg_, mask_, value_, timeout_, unit_)
-#define REG_IOSF_READ(unit_, reg_) \
- REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
-#define REG_IOSF_WRITE(unit_, reg_, value_) \
- REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
-#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
- REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
-#define REG_IOSF_OR(unit_, reg_, value_) \
- REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
-#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
- REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
-
-/*
- * CPU Model Specific Register
- */
-
-#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \
- _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
- REG_SCRIPT_TYPE_MSR, \
- REG_SCRIPT_SIZE_64, \
- reg_, mask_, value_, timeout_, 0)
-#define REG_MSR_READ(reg_) \
- REG_SCRIPT_MSR(READ, reg_, 0, 0, 0)
-#define REG_MSR_WRITE(reg_, value_) \
- REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0)
-#define REG_MSR_RMW(reg_, mask_, value_) \
- REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0)
-#define REG_MSR_OR(reg_, value_) \
- REG_MSR_RMW(reg_, -1ULL, value_)
-#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \
- REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_)
-
-/*
- * Chain to another table.
- */
-#define REG_SCRIPT_NEXT(next_) \
- { .command = REG_SCRIPT_COMMAND_NEXT, \
- .next = next_, \
- }
-
-/*
- * Set current device
- */
-#define REG_SCRIPT_SET_DEV(dev_) \
- { .command = REG_SCRIPT_COMMAND_SET_DEV, \
- .dev = dev_, \
- }
-
-/*
- * Last script entry. All tables need to end with REG_SCRIPT_END.
- */
-#define REG_SCRIPT_END \
- _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
-
-void reg_script_run(const struct reg_script *script);
-void reg_script_run_on_dev(device_t dev, const struct reg_script *step);
-
-#endif /* REG_SCRIPT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 5298bbe..9da90d1 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -83,8 +83,6 @@ ramstage-y += cbmem_info.c
ramstage-y += hexdump.c
romstage-y += hexdump.c
-ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
-
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c
smm-y += cbfs.c memcmp.c
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
deleted file mode 100644
index 647723b..0000000
--- a/src/lib/reg_script.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/device.h>
-#include <device/resource.h>
-#include <device/pci.h>
-#include <stdint.h>
-#include <reg_script.h>
-
-#if CONFIG_ARCH_X86
-#include <cpu/x86/msr.h>
-#endif
-
-#if CONFIG_SOC_INTEL_BAYTRAIL
-#include <baytrail/iosf.h>
-#endif
-
-#define POLL_DELAY 100 /* 100us */
-#if defined(__PRE_RAM__)
-#define EMPTY_DEV 0
-#else
-#define EMPTY_DEV NULL
-#endif
-
-struct reg_script_context {
- device_t dev;
- struct resource *res;
- const struct reg_script *step;
-};
-
-static inline void reg_script_set_dev(struct reg_script_context *ctx,
- device_t dev)
-{
- ctx->dev = dev;
- ctx->res = NULL;
-}
-
-static inline void reg_script_set_step(struct reg_script_context *ctx,
- const struct reg_script *step)
-{
- ctx->step = step;
-}
-
-static inline const struct reg_script *
-reg_script_get_step(struct reg_script_context *ctx)
-{
- return ctx->step;
-}
-
-static struct resource *reg_script_get_resource(struct reg_script_context *ctx)
-{
-#if defined(__PRE_RAM__)
- return NULL;
-#else
- struct resource *res;
- const struct reg_script *step = reg_script_get_step(ctx);
-
- res = ctx->res;
-
- if (res != NULL && res->index == step->res_index)
- return res;
-
- res = find_resource(ctx->dev, step->res_index);
- ctx->res = res;
- return res;
-#endif
-}
-
-static uint32_t reg_script_read_pci(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->size) {
- case REG_SCRIPT_SIZE_8:
- return pci_read_config8(ctx->dev, step->reg);
- case REG_SCRIPT_SIZE_16:
- return pci_read_config16(ctx->dev, step->reg);
- case REG_SCRIPT_SIZE_32:
- return pci_read_config32(ctx->dev, step->reg);
- }
- return 0;
-}
-
-static void reg_script_write_pci(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->size) {
- case REG_SCRIPT_SIZE_8:
- pci_write_config8(ctx->dev, step->reg, step->value);
- break;
- case REG_SCRIPT_SIZE_16:
- pci_write_config16(ctx->dev, step->reg, step->value);
- break;
- case REG_SCRIPT_SIZE_32:
- pci_write_config32(ctx->dev, step->reg, step->value);
- break;
- }
-}
-
-static uint32_t reg_script_read_io(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->size) {
- case REG_SCRIPT_SIZE_8:
- return inb(step->reg);
- case REG_SCRIPT_SIZE_16:
- return inw(step->reg);
- case REG_SCRIPT_SIZE_32:
- return inl(step->reg);
- }
- return 0;
-}
-
-static void reg_script_write_io(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->size) {
- case REG_SCRIPT_SIZE_8:
- outb(step->value, step->reg);
- break;
- case REG_SCRIPT_SIZE_16:
- outw(step->value, step->reg);
- break;
- case REG_SCRIPT_SIZE_32:
- outl(step->value, step->reg);
- break;
- }
-}
-
-static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->size) {
- case REG_SCRIPT_SIZE_8:
- return read8(step->reg);
- case REG_SCRIPT_SIZE_16:
- return read16(step->reg);
- case REG_SCRIPT_SIZE_32:
- return read32(step->reg);
- }
- return 0;
-}
-
-static void reg_script_write_mmio(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->size) {
- case REG_SCRIPT_SIZE_8:
- write8(step->reg, step->value);
- break;
- case REG_SCRIPT_SIZE_16:
- write16(step->reg, step->value);
- break;
- case REG_SCRIPT_SIZE_32:
- write32(step->reg, step->value);
- break;
- }
-}
-
-static uint32_t reg_script_read_res(struct reg_script_context *ctx)
-{
- struct resource *res;
- uint32_t val = 0;
- const struct reg_script *step = reg_script_get_step(ctx);
-
- res = reg_script_get_resource(ctx);
-
- if (res == NULL)
- return val;
-
- if (res->flags & IORESOURCE_IO) {
- const struct reg_script io_step = {
- .size = step->size,
- .reg = res->base + step->reg,
- };
- reg_script_set_step(ctx, &io_step);
- val = reg_script_read_io(ctx);
- }
- else if (res->flags & IORESOURCE_MEM) {
- const struct reg_script mmio_step = {
- .size = step->size,
- .reg = res->base + step->reg,
- };
- reg_script_set_step(ctx, &mmio_step);
- val = reg_script_read_mmio(ctx);
- }
- reg_script_set_step(ctx, step);
- return val;
-}
-
-static void reg_script_write_res(struct reg_script_context *ctx)
-{
- struct resource *res;
- const struct reg_script *step = reg_script_get_step(ctx);
-
- res = reg_script_get_resource(ctx);
-
- if (res == NULL)
- return;
-
- if (res->flags & IORESOURCE_IO) {
- const struct reg_script io_step = {
- .size = step->size,
- .reg = res->base + step->reg,
- .value = step->value,
- };
- reg_script_set_step(ctx, &io_step);
- reg_script_write_io(ctx);
- }
- else if (res->flags & IORESOURCE_MEM) {
- const struct reg_script mmio_step = {
- .size = step->size,
- .reg = res->base + step->reg,
- .value = step->value,
- };
- reg_script_set_step(ctx, &mmio_step);
- reg_script_write_mmio(ctx);
- }
- reg_script_set_step(ctx, step);
-}
-
-static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
-{
-#if CONFIG_SOC_INTEL_BAYTRAIL
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->id) {
- case IOSF_PORT_AUNIT:
- return iosf_aunit_read(step->reg);
- case IOSF_PORT_CPU_BUS:
- return iosf_cpu_bus_read(step->reg);
- case IOSF_PORT_BUNIT:
- return iosf_bunit_read(step->reg);
- case IOSF_PORT_DUNIT_CH0:
- return iosf_dunit_ch0_read(step->reg);
- case IOSF_PORT_PMC:
- return iosf_punit_read(step->reg);
- case IOSF_PORT_USBPHY:
- return iosf_usbphy_read(step->reg);
- case IOSF_PORT_SEC:
- return iosf_sec_read(step->reg);
- case IOSF_PORT_0x45:
- return iosf_port45_read(step->reg);
- case IOSF_PORT_0x46:
- return iosf_port46_read(step->reg);
- case IOSF_PORT_0x47:
- return iosf_port47_read(step->reg);
- case IOSF_PORT_SCORE:
- return iosf_score_read(step->reg);
- case IOSF_PORT_0x55:
- return iosf_port55_read(step->reg);
- case IOSF_PORT_0x58:
- return iosf_port58_read(step->reg);
- case IOSF_PORT_0x59:
- return iosf_port59_read(step->reg);
- case IOSF_PORT_0x5a:
- return iosf_port5a_read(step->reg);
- case IOSF_PORT_USHPHY:
- return iosf_ushphy_read(step->reg);
- case IOSF_PORT_SCC:
- return iosf_scc_read(step->reg);
- case IOSF_PORT_LPSS:
- return iosf_lpss_read(step->reg);
- case IOSF_PORT_0xa2:
- return iosf_porta2_read(step->reg);
- case IOSF_PORT_CCU:
- return iosf_ccu_read(step->reg);
- case IOSF_PORT_SSUS:
- return iosf_ssus_read(step->reg);
- default:
- printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n",
- step->id);
- break;
- }
-#endif
- return 0;
-}
-
-static void reg_script_write_iosf(struct reg_script_context *ctx)
-{
-#if CONFIG_SOC_INTEL_BAYTRAIL
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->id) {
- case IOSF_PORT_AUNIT:
- iosf_aunit_write(step->reg, step->value);
- break;
- case IOSF_PORT_CPU_BUS:
- iosf_cpu_bus_write(step->reg, step->value);
- break;
- case IOSF_PORT_BUNIT:
- iosf_bunit_write(step->reg, step->value);
- break;
- case IOSF_PORT_DUNIT_CH0:
- iosf_dunit_write(step->reg, step->value);
- break;
- case IOSF_PORT_PMC:
- iosf_punit_write(step->reg, step->value);
- break;
- case IOSF_PORT_USBPHY:
- iosf_usbphy_write(step->reg, step->value);
- break;
- case IOSF_PORT_SEC:
- iosf_sec_write(step->reg, step->value);
- break;
- case IOSF_PORT_0x45:
- iosf_port45_write(step->reg, step->value);
- break;
- case IOSF_PORT_0x46:
- iosf_port46_write(step->reg, step->value);
- break;
- case IOSF_PORT_0x47:
- iosf_port47_write(step->reg, step->value);
- break;
- case IOSF_PORT_SCORE:
- iosf_score_write(step->reg, step->value);
- break;
- case IOSF_PORT_0x55:
- iosf_port55_write(step->reg, step->value);
- break;
- case IOSF_PORT_0x58:
- iosf_port58_write(step->reg, step->value);
- break;
- case IOSF_PORT_0x59:
- iosf_port59_write(step->reg, step->value);
- break;
- case IOSF_PORT_0x5a:
- iosf_port5a_write(step->reg, step->value);
- break;
- case IOSF_PORT_USHPHY:
- iosf_ushphy_write(step->reg, step->value);
- break;
- case IOSF_PORT_SCC:
- iosf_scc_write(step->reg, step->value);
- break;
- case IOSF_PORT_LPSS:
- iosf_lpss_write(step->reg, step->value);
- break;
- case IOSF_PORT_0xa2:
- iosf_porta2_write(step->reg, step->value);
- break;
- case IOSF_PORT_CCU:
- iosf_ccu_write(step->reg, step->value);
- break;
- case IOSF_PORT_SSUS:
- iosf_ssus_write(step->reg, step->value);
- break;
- default:
- printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n",
- step->id);
- break;
- }
-#endif
-}
-
-static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
-{
-#if CONFIG_ARCH_X86
- const struct reg_script *step = reg_script_get_step(ctx);
- msr_t msr = rdmsr(step->reg);
- uint64_t value = msr.hi;
- value = msr.hi;
- value <<= 32;
- value |= msr.lo;
- return value;
-#endif
-}
-
-static void reg_script_write_msr(struct reg_script_context *ctx)
-{
-#if CONFIG_ARCH_X86
- const struct reg_script *step = reg_script_get_step(ctx);
- msr_t msr;
- msr.hi = step->value >> 32;
- msr.lo = step->value & 0xffffffff;
- wrmsr(step->reg, msr);
-#endif
-}
-
-static uint64_t reg_script_read(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->type) {
- case REG_SCRIPT_TYPE_PCI:
- return reg_script_read_pci(ctx);
- case REG_SCRIPT_TYPE_IO:
- return reg_script_read_io(ctx);
- case REG_SCRIPT_TYPE_MMIO:
- return reg_script_read_mmio(ctx);
- case REG_SCRIPT_TYPE_RES:
- return reg_script_read_res(ctx);
- case REG_SCRIPT_TYPE_IOSF:
- return reg_script_read_iosf(ctx);
- case REG_SCRIPT_TYPE_MSR:
- return reg_script_read_msr(ctx);
- }
- return 0;
-}
-
-static void reg_script_write(struct reg_script_context *ctx)
-{
- const struct reg_script *step = reg_script_get_step(ctx);
-
- switch (step->type) {
- case REG_SCRIPT_TYPE_PCI:
- reg_script_write_pci(ctx);
- break;
- case REG_SCRIPT_TYPE_IO:
- reg_script_write_io(ctx);
- break;
- case REG_SCRIPT_TYPE_MMIO:
- reg_script_write_mmio(ctx);
- break;
- case REG_SCRIPT_TYPE_RES:
- reg_script_write_res(ctx);
- break;
- case REG_SCRIPT_TYPE_IOSF:
- reg_script_write_iosf(ctx);
- break;
- case REG_SCRIPT_TYPE_MSR:
- reg_script_write_msr(ctx);
- break;
- }
-}
-
-static void reg_script_rmw(struct reg_script_context *ctx)
-{
- uint64_t value;
- const struct reg_script *step = reg_script_get_step(ctx);
- struct reg_script write_step = *step;
-
- value = reg_script_read(ctx);
- value &= step->mask;
- value |= step->value;
- write_step.value = value;
- reg_script_set_step(ctx, &write_step);
- reg_script_write(ctx);
- reg_script_set_step(ctx, step);
-}
-
-/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT
- * as recursive call with a new context that has the same dev and resource
- * as the previous one. That will run to completion and then move on to the
- * next step of the previous context. */
-static void reg_script_run_next(struct reg_script_context *ctx,
- const struct reg_script *step);
-
-
-static void reg_script_run_step(struct reg_script_context *ctx,
- const struct reg_script *step)
-{
- uint64_t value = 0, try;
-
- switch (step->command) {
- case REG_SCRIPT_COMMAND_READ:
- (void)reg_script_read(ctx);
- break;
- case REG_SCRIPT_COMMAND_WRITE:
- reg_script_write(ctx);
- break;
- case REG_SCRIPT_COMMAND_RMW:
- reg_script_rmw(ctx);
- break;
- case REG_SCRIPT_COMMAND_POLL:
- for (try = 0; try < step->timeout; try += POLL_DELAY) {
- value = reg_script_read(ctx) & step->mask;
- if (value == step->value)
- break;
- udelay(POLL_DELAY);
- }
- if (try >= step->timeout)
- printk(BIOS_WARNING, "%s: POLL timeout waiting for "
- "0x%x to be 0x%lx, got 0x%lx\n", __func__,
- step->reg, (unsigned long)step->value,
- (unsigned long)value);
- break;
- case REG_SCRIPT_COMMAND_SET_DEV:
- reg_script_set_dev(ctx, step->dev);
- break;
- case REG_SCRIPT_COMMAND_NEXT:
- reg_script_run_next(ctx, step->next);
- break;
- default:
- printk(BIOS_WARNING, "Invalid command: %08x\n",
- step->command);
- break;
- }
-}
-
-static void reg_script_run_with_context(struct reg_script_context *ctx)
-{
- while (1) {
- const struct reg_script *step = reg_script_get_step(ctx);
-
- if (step->command == REG_SCRIPT_COMMAND_END)
- break;
-
- reg_script_run_step(ctx, step);
- reg_script_set_step(ctx, step + 1);
- }
-}
-
-static void reg_script_run_next(struct reg_script_context *prev_ctx,
- const struct reg_script *step)
-{
- struct reg_script_context ctx;
-
- /* Use prev context as a basis but start at a new step. */
- ctx = *prev_ctx;
- reg_script_set_step(&ctx, step);
- reg_script_run_with_context(&ctx);
-}
-
-void reg_script_run_on_dev(device_t dev, const struct reg_script *step)
-{
- struct reg_script_context ctx;
-
- reg_script_set_dev(&ctx, dev);
- reg_script_set_step(&ctx, step);
- reg_script_run_with_context(&ctx);
-}
-
-void reg_script_run(const struct reg_script *step)
-{
- reg_script_run_on_dev(EMPTY_DEV, step);
-}
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index d4f653e..886caf4 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -49,6 +49,7 @@ ramstage-y += perf_power.c
ramstage-y += stage_cache.c
romstage-y += stage_cache.c
ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += reg_script.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/reg_script.c b/src/soc/intel/baytrail/reg_script.c
new file mode 100644
index 0000000..78749fd
--- /dev/null
+++ b/src/soc/intel/baytrail/reg_script.c
@@ -0,0 +1,538 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/resource.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <reg_script.h>
+
+#include <cpu/x86/msr.h>
+#include <baytrail/iosf.h>
+
+#define POLL_DELAY 100 /* 100us */
+#if defined(__PRE_RAM__)
+#define EMPTY_DEV 0
+#else
+#define EMPTY_DEV NULL
+#endif
+
+struct reg_script_context {
+ device_t dev;
+ struct resource *res;
+ const struct reg_script *step;
+};
+
+static inline void reg_script_set_dev(struct reg_script_context *ctx,
+ device_t dev)
+{
+ ctx->dev = dev;
+ ctx->res = NULL;
+}
+
+static inline void reg_script_set_step(struct reg_script_context *ctx,
+ const struct reg_script *step)
+{
+ ctx->step = step;
+}
+
+static inline const struct reg_script *
+reg_script_get_step(struct reg_script_context *ctx)
+{
+ return ctx->step;
+}
+
+static struct resource *reg_script_get_resource(struct reg_script_context *ctx)
+{
+#if defined(__PRE_RAM__)
+ return NULL;
+#else
+ struct resource *res;
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ res = ctx->res;
+
+ if (res != NULL && res->index == step->res_index)
+ return res;
+
+ res = find_resource(ctx->dev, step->res_index);
+ ctx->res = res;
+ return res;
+#endif
+}
+
+static uint32_t reg_script_read_pci(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->size) {
+ case REG_SCRIPT_SIZE_8:
+ return pci_read_config8(ctx->dev, step->reg);
+ case REG_SCRIPT_SIZE_16:
+ return pci_read_config16(ctx->dev, step->reg);
+ case REG_SCRIPT_SIZE_32:
+ return pci_read_config32(ctx->dev, step->reg);
+ }
+ return 0;
+}
+
+static void reg_script_write_pci(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->size) {
+ case REG_SCRIPT_SIZE_8:
+ pci_write_config8(ctx->dev, step->reg, step->value);
+ break;
+ case REG_SCRIPT_SIZE_16:
+ pci_write_config16(ctx->dev, step->reg, step->value);
+ break;
+ case REG_SCRIPT_SIZE_32:
+ pci_write_config32(ctx->dev, step->reg, step->value);
+ break;
+ }
+}
+
+static uint32_t reg_script_read_io(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->size) {
+ case REG_SCRIPT_SIZE_8:
+ return inb(step->reg);
+ case REG_SCRIPT_SIZE_16:
+ return inw(step->reg);
+ case REG_SCRIPT_SIZE_32:
+ return inl(step->reg);
+ }
+ return 0;
+}
+
+static void reg_script_write_io(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->size) {
+ case REG_SCRIPT_SIZE_8:
+ outb(step->value, step->reg);
+ break;
+ case REG_SCRIPT_SIZE_16:
+ outw(step->value, step->reg);
+ break;
+ case REG_SCRIPT_SIZE_32:
+ outl(step->value, step->reg);
+ break;
+ }
+}
+
+static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->size) {
+ case REG_SCRIPT_SIZE_8:
+ return read8(step->reg);
+ case REG_SCRIPT_SIZE_16:
+ return read16(step->reg);
+ case REG_SCRIPT_SIZE_32:
+ return read32(step->reg);
+ }
+ return 0;
+}
+
+static void reg_script_write_mmio(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->size) {
+ case REG_SCRIPT_SIZE_8:
+ write8(step->reg, step->value);
+ break;
+ case REG_SCRIPT_SIZE_16:
+ write16(step->reg, step->value);
+ break;
+ case REG_SCRIPT_SIZE_32:
+ write32(step->reg, step->value);
+ break;
+ }
+}
+
+static uint32_t reg_script_read_res(struct reg_script_context *ctx)
+{
+ struct resource *res;
+ uint32_t val = 0;
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ res = reg_script_get_resource(ctx);
+
+ if (res == NULL)
+ return val;
+
+ if (res->flags & IORESOURCE_IO) {
+ const struct reg_script io_step = {
+ .size = step->size,
+ .reg = res->base + step->reg,
+ };
+ reg_script_set_step(ctx, &io_step);
+ val = reg_script_read_io(ctx);
+ }
+ else if (res->flags & IORESOURCE_MEM) {
+ const struct reg_script mmio_step = {
+ .size = step->size,
+ .reg = res->base + step->reg,
+ };
+ reg_script_set_step(ctx, &mmio_step);
+ val = reg_script_read_mmio(ctx);
+ }
+ reg_script_set_step(ctx, step);
+ return val;
+}
+
+static void reg_script_write_res(struct reg_script_context *ctx)
+{
+ struct resource *res;
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ res = reg_script_get_resource(ctx);
+
+ if (res == NULL)
+ return;
+
+ if (res->flags & IORESOURCE_IO) {
+ const struct reg_script io_step = {
+ .size = step->size,
+ .reg = res->base + step->reg,
+ .value = step->value,
+ };
+ reg_script_set_step(ctx, &io_step);
+ reg_script_write_io(ctx);
+ }
+ else if (res->flags & IORESOURCE_MEM) {
+ const struct reg_script mmio_step = {
+ .size = step->size,
+ .reg = res->base + step->reg,
+ .value = step->value,
+ };
+ reg_script_set_step(ctx, &mmio_step);
+ reg_script_write_mmio(ctx);
+ }
+ reg_script_set_step(ctx, step);
+}
+
+static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->id) {
+ case IOSF_PORT_AUNIT:
+ return iosf_aunit_read(step->reg);
+ case IOSF_PORT_CPU_BUS:
+ return iosf_cpu_bus_read(step->reg);
+ case IOSF_PORT_BUNIT:
+ return iosf_bunit_read(step->reg);
+ case IOSF_PORT_DUNIT_CH0:
+ return iosf_dunit_ch0_read(step->reg);
+ case IOSF_PORT_PMC:
+ return iosf_punit_read(step->reg);
+ case IOSF_PORT_USBPHY:
+ return iosf_usbphy_read(step->reg);
+ case IOSF_PORT_SEC:
+ return iosf_sec_read(step->reg);
+ case IOSF_PORT_0x45:
+ return iosf_port45_read(step->reg);
+ case IOSF_PORT_0x46:
+ return iosf_port46_read(step->reg);
+ case IOSF_PORT_0x47:
+ return iosf_port47_read(step->reg);
+ case IOSF_PORT_SCORE:
+ return iosf_score_read(step->reg);
+ case IOSF_PORT_0x55:
+ return iosf_port55_read(step->reg);
+ case IOSF_PORT_0x58:
+ return iosf_port58_read(step->reg);
+ case IOSF_PORT_0x59:
+ return iosf_port59_read(step->reg);
+ case IOSF_PORT_0x5a:
+ return iosf_port5a_read(step->reg);
+ case IOSF_PORT_USHPHY:
+ return iosf_ushphy_read(step->reg);
+ case IOSF_PORT_SCC:
+ return iosf_scc_read(step->reg);
+ case IOSF_PORT_LPSS:
+ return iosf_lpss_read(step->reg);
+ case IOSF_PORT_0xa2:
+ return iosf_porta2_read(step->reg);
+ case IOSF_PORT_CCU:
+ return iosf_ccu_read(step->reg);
+ case IOSF_PORT_SSUS:
+ return iosf_ssus_read(step->reg);
+ default:
+ printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n",
+ step->id);
+ break;
+ }
+ return 0;
+}
+
+static void reg_script_write_iosf(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->id) {
+ case IOSF_PORT_AUNIT:
+ iosf_aunit_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_CPU_BUS:
+ iosf_cpu_bus_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_BUNIT:
+ iosf_bunit_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_DUNIT_CH0:
+ iosf_dunit_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_PMC:
+ iosf_punit_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_USBPHY:
+ iosf_usbphy_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_SEC:
+ iosf_sec_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0x45:
+ iosf_port45_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0x46:
+ iosf_port46_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0x47:
+ iosf_port47_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_SCORE:
+ iosf_score_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0x55:
+ iosf_port55_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0x58:
+ iosf_port58_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0x59:
+ iosf_port59_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0x5a:
+ iosf_port5a_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_USHPHY:
+ iosf_ushphy_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_SCC:
+ iosf_scc_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_LPSS:
+ iosf_lpss_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_0xa2:
+ iosf_porta2_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_CCU:
+ iosf_ccu_write(step->reg, step->value);
+ break;
+ case IOSF_PORT_SSUS:
+ iosf_ssus_write(step->reg, step->value);
+ break;
+ default:
+ printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n",
+ step->id);
+ break;
+ }
+}
+
+static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+ msr_t msr = rdmsr(step->reg);
+ uint64_t value = msr.hi;
+ value = msr.hi;
+ value <<= 32;
+ value |= msr.lo;
+ return value;
+}
+
+static void reg_script_write_msr(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+ msr_t msr;
+ msr.hi = step->value >> 32;
+ msr.lo = step->value & 0xffffffff;
+ wrmsr(step->reg, msr);
+}
+
+static uint64_t reg_script_read(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->type) {
+ case REG_SCRIPT_TYPE_PCI:
+ return reg_script_read_pci(ctx);
+ case REG_SCRIPT_TYPE_IO:
+ return reg_script_read_io(ctx);
+ case REG_SCRIPT_TYPE_MMIO:
+ return reg_script_read_mmio(ctx);
+ case REG_SCRIPT_TYPE_RES:
+ return reg_script_read_res(ctx);
+ case REG_SCRIPT_TYPE_IOSF:
+ return reg_script_read_iosf(ctx);
+ case REG_SCRIPT_TYPE_MSR:
+ return reg_script_read_msr(ctx);
+ }
+ return 0;
+}
+
+static void reg_script_write(struct reg_script_context *ctx)
+{
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ switch (step->type) {
+ case REG_SCRIPT_TYPE_PCI:
+ reg_script_write_pci(ctx);
+ break;
+ case REG_SCRIPT_TYPE_IO:
+ reg_script_write_io(ctx);
+ break;
+ case REG_SCRIPT_TYPE_MMIO:
+ reg_script_write_mmio(ctx);
+ break;
+ case REG_SCRIPT_TYPE_RES:
+ reg_script_write_res(ctx);
+ break;
+ case REG_SCRIPT_TYPE_IOSF:
+ reg_script_write_iosf(ctx);
+ break;
+ case REG_SCRIPT_TYPE_MSR:
+ reg_script_write_msr(ctx);
+ break;
+ }
+}
+
+static void reg_script_rmw(struct reg_script_context *ctx)
+{
+ uint64_t value;
+ const struct reg_script *step = reg_script_get_step(ctx);
+ struct reg_script write_step = *step;
+
+ value = reg_script_read(ctx);
+ value &= step->mask;
+ value |= step->value;
+ write_step.value = value;
+ reg_script_set_step(ctx, &write_step);
+ reg_script_write(ctx);
+ reg_script_set_step(ctx, step);
+}
+
+/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT
+ * as recursive call with a new context that has the same dev and resource
+ * as the previous one. That will run to completion and then move on to the
+ * next step of the previous context. */
+static void reg_script_run_next(struct reg_script_context *ctx,
+ const struct reg_script *step);
+
+
+static void reg_script_run_step(struct reg_script_context *ctx,
+ const struct reg_script *step)
+{
+ uint64_t value = 0, try;
+
+ switch (step->command) {
+ case REG_SCRIPT_COMMAND_READ:
+ (void)reg_script_read(ctx);
+ break;
+ case REG_SCRIPT_COMMAND_WRITE:
+ reg_script_write(ctx);
+ break;
+ case REG_SCRIPT_COMMAND_RMW:
+ reg_script_rmw(ctx);
+ break;
+ case REG_SCRIPT_COMMAND_POLL:
+ for (try = 0; try < step->timeout; try += POLL_DELAY) {
+ value = reg_script_read(ctx) & step->mask;
+ if (value == step->value)
+ break;
+ udelay(POLL_DELAY);
+ }
+ if (try >= step->timeout)
+ printk(BIOS_WARNING, "%s: POLL timeout waiting for "
+ "0x%x to be 0x%lx, got 0x%lx\n", __func__,
+ step->reg, (unsigned long)step->value,
+ (unsigned long)value);
+ break;
+ case REG_SCRIPT_COMMAND_SET_DEV:
+ reg_script_set_dev(ctx, step->dev);
+ break;
+ case REG_SCRIPT_COMMAND_NEXT:
+ reg_script_run_next(ctx, step->next);
+ break;
+ default:
+ printk(BIOS_WARNING, "Invalid command: %08x\n",
+ step->command);
+ break;
+ }
+}
+
+static void reg_script_run_with_context(struct reg_script_context *ctx)
+{
+ while (1) {
+ const struct reg_script *step = reg_script_get_step(ctx);
+
+ if (step->command == REG_SCRIPT_COMMAND_END)
+ break;
+
+ reg_script_run_step(ctx, step);
+ reg_script_set_step(ctx, step + 1);
+ }
+}
+
+static void reg_script_run_next(struct reg_script_context *prev_ctx,
+ const struct reg_script *step)
+{
+ struct reg_script_context ctx;
+
+ /* Use prev context as a basis but start at a new step. */
+ ctx = *prev_ctx;
+ reg_script_set_step(&ctx, step);
+ reg_script_run_with_context(&ctx);
+}
+
+void reg_script_run_on_dev(device_t dev, const struct reg_script *step)
+{
+ struct reg_script_context ctx;
+
+ reg_script_set_dev(&ctx, dev);
+ reg_script_set_step(&ctx, step);
+ reg_script_run_with_context(&ctx);
+}
+
+void reg_script_run(const struct reg_script *step)
+{
+ reg_script_run_on_dev(EMPTY_DEV, step);
+}
diff --git a/src/soc/intel/baytrail/reg_script.h b/src/soc/intel/baytrail/reg_script.h
new file mode 100644
index 0000000..72e1e96
--- /dev/null
+++ b/src/soc/intel/baytrail/reg_script.h
@@ -0,0 +1,339 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef REG_SCRIPT_H
+#define REG_SCRIPT_H
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/resource.h>
+
+/*
+ * The reg script library is a way to provide data-driven I/O accesses for
+ * initializing devices. It currently supports PCI, legacy I/O,
+ * memory-mapped I/O, and IOSF accesses.
+ *
+ * In order to simplify things for the developer the following features
+ * are employed:
+ * - Chaining of tables that allow runtime tables to chain to compile-time
+ * tables.
+ * - Notion of current device (device_t) being worked on. This allows for
+ * PCI config, io, and mmio on a particular device's resources.
+ *
+ * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
+ * and pop of the context. A chained reg_script inherits the previous
+ * context (such as current device), but it does not impact the previous
+ * context in any way.
+ */
+
+enum {
+ REG_SCRIPT_COMMAND_READ,
+ REG_SCRIPT_COMMAND_WRITE,
+ REG_SCRIPT_COMMAND_RMW,
+ REG_SCRIPT_COMMAND_POLL,
+ REG_SCRIPT_COMMAND_SET_DEV,
+ REG_SCRIPT_COMMAND_NEXT,
+ REG_SCRIPT_COMMAND_END,
+};
+
+enum {
+ REG_SCRIPT_TYPE_PCI,
+ REG_SCRIPT_TYPE_IO,
+ REG_SCRIPT_TYPE_MMIO,
+ REG_SCRIPT_TYPE_RES,
+ REG_SCRIPT_TYPE_IOSF,
+ REG_SCRIPT_TYPE_MSR,
+};
+
+enum {
+ REG_SCRIPT_SIZE_8,
+ REG_SCRIPT_SIZE_16,
+ REG_SCRIPT_SIZE_32,
+ REG_SCRIPT_SIZE_64,
+};
+
+struct reg_script {
+ uint32_t command;
+ uint32_t type;
+ uint32_t size;
+ uint32_t reg;
+ uint64_t mask;
+ uint64_t value;
+ uint32_t timeout;
+ union {
+ uint32_t id;
+ const struct reg_script *next;
+ device_t dev;
+ unsigned int res_index;
+ };
+};
+
+/* Internal helper Macros. */
+
+#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
+ mask_, value_, timeout_, id_) \
+ { .command = cmd_, \
+ .type = type_, \
+ .size = size_, \
+ .reg = reg_, \
+ .mask = mask_, \
+ .value = value_, \
+ .timeout = timeout_, \
+ .id = id_, \
+ }
+
+#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
+ mask_, value_, timeout_) \
+ { .command = cmd_, \
+ .type = type_, \
+ .size = size_, \
+ .reg = reg_, \
+ .mask = mask_, \
+ .value = value_, \
+ .timeout = timeout_, \
+ .res_index = res_index_, \
+ }
+
+/*
+ * PCI
+ */
+
+#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
+ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
+ REG_SCRIPT_TYPE_PCI, \
+ REG_SCRIPT_SIZE_##bits_, \
+ reg_, mask_, value_, timeout_, 0)
+#define REG_PCI_READ8(reg_) \
+ REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
+#define REG_PCI_READ16(reg_) \
+ REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
+#define REG_PCI_READ32(reg_) \
+ REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
+#define REG_PCI_WRITE8(reg_, value_) \
+ REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
+#define REG_PCI_WRITE16(reg_, value_) \
+ REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
+#define REG_PCI_WRITE32(reg_, value_) \
+ REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
+#define REG_PCI_RMW8(reg_, mask_, value_) \
+ REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
+#define REG_PCI_RMW16(reg_, mask_, value_) \
+ REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
+#define REG_PCI_RMW32(reg_, mask_, value_) \
+ REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
+#define REG_PCI_OR8(reg_, value_) \
+ REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
+#define REG_PCI_OR16(reg_, value_) \
+ REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
+#define REG_PCI_OR32(reg_, value_) \
+ REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
+#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
+#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
+#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
+
+/*
+ * Legacy IO
+ */
+
+#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
+ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
+ REG_SCRIPT_TYPE_IO, \
+ REG_SCRIPT_SIZE_##bits_, \
+ reg_, mask_, value_, timeout_, 0)
+#define REG_IO_READ8(reg_) \
+ REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
+#define REG_IO_READ16(reg_) \
+ REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
+#define REG_IO_READ32(reg_) \
+ REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
+#define REG_IO_WRITE8(reg_, value_) \
+ REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
+#define REG_IO_WRITE16(reg_, value_) \
+ REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
+#define REG_IO_WRITE32(reg_, value_) \
+ REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
+#define REG_IO_RMW8(reg_, mask_, value_) \
+ REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
+#define REG_IO_RMW16(reg_, mask_, value_) \
+ REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
+#define REG_IO_RMW32(reg_, mask_, value_) \
+ REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
+#define REG_IO_OR8(reg_, value_) \
+ REG_SCRIPT_IO_RMW8(_reg, 0xff, value)
+#define REG_IO_OR16(reg_, value_) \
+ REG_SCRIPT_IO_RMW16(_reg, 0xffff, value)
+#define REG_IO_OR32(reg_, value_) \
+ REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value)
+#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
+#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
+#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
+
+/*
+ * Memory Mapped IO
+ */
+
+#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
+ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
+ REG_SCRIPT_TYPE_MMIO, \
+ REG_SCRIPT_SIZE_##bits_, \
+ reg_, mask_, value_, timeout_, 0)
+#define REG_MMIO_READ8(reg_) \
+ REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
+#define REG_MMIO_READ16(reg_) \
+ REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
+#define REG_MMIO_READ32(reg_) \
+ REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
+#define REG_MMIO_WRITE8(reg_, value_) \
+ REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
+#define REG_MMIO_WRITE16(reg_, value_) \
+ REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
+#define REG_MMIO_WRITE32(reg_, value_) \
+ REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
+#define REG_MMIO_RMW8(reg_, mask_, value_) \
+ REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
+#define REG_MMIO_RMW16(reg_, mask_, value_) \
+ REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
+#define REG_MMIO_RMW32(reg_, mask_, value_) \
+ REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
+#define REG_MMIO_OR8(reg_, value_) \
+ REG_MMIO_RMW8(reg_, 0xff, value_)
+#define REG_MMIO_OR16(reg_, value_) \
+ REG_MMIO_RMW16(reg_, 0xffff, value_)
+#define REG_MMIO_OR32(reg_, value_) \
+ REG_MMIO_RMW32(reg_, 0xffffffff, value_)
+#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
+#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
+#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
+
+/*
+ * Access through a device's resource such as a Base Address Register (BAR)
+ */
+
+#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
+ _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \
+ REG_SCRIPT_TYPE_RES, bar_, \
+ REG_SCRIPT_SIZE_##bits_, \
+ reg_, mask_, value_, timeout_)
+#define REG_RES_READ8(bar_, reg_) \
+ REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
+#define REG_RES_READ16(bar_, reg_) \
+ REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
+#define REG_RES_READ32(bar_, reg_) \
+ REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
+#define REG_RES_WRITE8(bar_, reg_, value_) \
+ REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
+#define REG_RES_WRITE16(bar_, reg_, value_) \
+ REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
+#define REG_RES_WRITE32(bar_, reg_, value_) \
+ REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
+#define REG_RES_RMW8(bar_, reg_, mask_, value_) \
+ REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
+#define REG_RES_RMW16(bar_, reg_, mask_, value_) \
+ REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
+#define REG_RES_RMW32(bar_, reg_, mask_, value_) \
+ REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
+#define REG_RES_OR8(bar_, reg_, value_) \
+ REG_RES_RMW8(bar_, reg_, 0xff, value_)
+#define REG_RES_OR16(bar_, reg_, value_) \
+ REG_RES_RMW16(bar_, reg_, 0xffff, value_)
+#define REG_RES_OR32(bar_, reg_, value_) \
+ REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
+#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
+#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
+#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
+
+/*
+ * IO Sideband Function
+ */
+
+#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
+ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
+ REG_SCRIPT_TYPE_IOSF, \
+ REG_SCRIPT_SIZE_32, \
+ reg_, mask_, value_, timeout_, unit_)
+#define REG_IOSF_READ(unit_, reg_) \
+ REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
+#define REG_IOSF_WRITE(unit_, reg_, value_) \
+ REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
+#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
+ REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
+#define REG_IOSF_OR(unit_, reg_, value_) \
+ REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
+#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
+
+/*
+ * CPU Model Specific Register
+ */
+
+#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \
+ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
+ REG_SCRIPT_TYPE_MSR, \
+ REG_SCRIPT_SIZE_64, \
+ reg_, mask_, value_, timeout_, 0)
+#define REG_MSR_READ(reg_) \
+ REG_SCRIPT_MSR(READ, reg_, 0, 0, 0)
+#define REG_MSR_WRITE(reg_, value_) \
+ REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0)
+#define REG_MSR_RMW(reg_, mask_, value_) \
+ REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0)
+#define REG_MSR_OR(reg_, value_) \
+ REG_MSR_RMW(reg_, -1ULL, value_)
+#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_)
+
+/*
+ * Chain to another table.
+ */
+#define REG_SCRIPT_NEXT(next_) \
+ { .command = REG_SCRIPT_COMMAND_NEXT, \
+ .next = next_, \
+ }
+
+/*
+ * Set current device
+ */
+#define REG_SCRIPT_SET_DEV(dev_) \
+ { .command = REG_SCRIPT_COMMAND_SET_DEV, \
+ .dev = dev_, \
+ }
+
+/*
+ * Last script entry. All tables need to end with REG_SCRIPT_END.
+ */
+#define REG_SCRIPT_END \
+ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
+
+void reg_script_run(const struct reg_script *script);
+void reg_script_run_on_dev(device_t dev, const struct reg_script *step);
+
+#endif /* REG_SCRIPT_H */
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index cb4757b..c2b747c 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
select PARALLEL_MP
- select REG_SCRIPT
select SMP
select SPI_FLASH
select SSE2
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