[coreboot-gerrit] Patch merged into coreboot/master: 3ffdafd Exynos5420: Remove code for enabling read leveling

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 3ffdafdfa4cabdae4828638c402a6a81780bc275
Author: David Hendricks <dhendrix at chromium.org>
Date:   Fri Aug 23 15:47:06 2013 -0700

    Exynos5420: Remove code for enabling read leveling
    
    This patch intends to remove all code which enables hardware read
    leveling. We need to disable h/w read leveling because new ASV table
    is merged in kernel (which is based on the new characterization
    condition) and new characterization environment has h/w read leveling
    disabled, so we should also disable this. Also, disabling h/w read
    leveling improves the MIF LVcc value (LVcc value is the value at which
    DDR will fail to work properly), improve LVcc means we have enough
    voltage margin for MIF. When h/w leveling is enabled, we have almost
    zero volatge margin.
    
    This was ported from: https://gerrit.chromium.org/gerrit/66070
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Change-Id: Id0a2d77e6214325f226d51ae08464b39424cea83
    Reviewed-on: https://chromium-review.googlesource.com/66994
    Reviewed-by: Gabe Black <gabeblack at chromium.org>
    Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit d29add98f52876aaed4fee2b76edf6b4591e66e8)
    Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
    Reviewed-on: http://review.coreboot.org/6610
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See http://review.coreboot.org/6610 for details.

-gerrit