[coreboot-gerrit] New patch to review for coreboot: eef3f8f trustzone: Pull trustzone init out of cpu.c and do it in romstage.
Isaac Christensen (isaac.christensen@se-eng.com)
gerrit at coreboot.org
Thu Aug 14 20:48:56 CEST 2014
Isaac Christensen (isaac.christensen at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6666
-gerrit
commit eef3f8ffa7bfcf0ef5f1d6adfe0b8692210db0e6
Author: Gabe Black <gabeblack at google.com>
Date: Wed Sep 18 05:48:37 2013 -0700
trustzone: Pull trustzone init out of cpu.c and do it in romstage.
Trustzone needs to be initialized/disabled both on boot and on wake, so it
needs to be done before ramstage which doesn't run on wake. cpu.c isn't
compiled into romstage and fixing that causes other problems, so the trustzone
functions were split out.
Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e
Signed-off-by: Gabe Black <gabeblack at google.com>
Reviewed-on: https://chromium-review.googlesource.com/169817
Reviewed-by: Gabe Black <gabeblack at chromium.org>
Tested-by: Gabe Black <gabeblack at chromium.org>
Commit-Queue: Gabe Black <gabeblack at chromium.org>
(cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee)
Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
---
src/cpu/samsung/exynos5250/Makefile.inc | 1 +
src/cpu/samsung/exynos5250/cpu.c | 24 ----------
src/cpu/samsung/exynos5250/cpu.h | 54 ----------------------
src/cpu/samsung/exynos5250/trustzone.c | 44 ++++++++++++++++++
src/cpu/samsung/exynos5250/trustzone.h | 81 +++++++++++++++++++++++++++++++++
src/cpu/samsung/exynos5420/Makefile.inc | 1 +
src/cpu/samsung/exynos5420/cpu.c | 22 ---------
src/cpu/samsung/exynos5420/cpu.h | 54 ----------------------
src/cpu/samsung/exynos5420/trustzone.c | 42 +++++++++++++++++
src/cpu/samsung/exynos5420/trustzone.h | 81 +++++++++++++++++++++++++++++++++
src/mainboard/google/pit/romstage.c | 3 ++
src/mainboard/google/snow/romstage.c | 4 ++
12 files changed, 257 insertions(+), 154 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index a5e3456..4b967b0 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -31,6 +31,7 @@ endif
romstage-y += wakeup.c
romstage-y += gpio.c
romstage-y += timer.c
+romstage-y += trustzone.c
romstage-y += i2c.c
#romstage-y += wdt.c
romstage-y += cbmem.c
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index 6f20ad6..fd1bf2d 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -35,28 +35,6 @@
static unsigned int cpu_id;
static unsigned int cpu_rev;
-/* Setting TZPC[TrustZone Protection Controller] */
-static void tzpc_init(void)
-{
- struct exynos_tzpc *tzpc;
- unsigned int addr;
-
- for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
- tzpc = (struct exynos_tzpc *)addr;
-
- if (addr == TZPC0_BASE)
- writel(R0SIZE, &tzpc->r0size);
-
- writel(DECPROTXSET, &tzpc->decprot0set);
- writel(DECPROTXSET, &tzpc->decprot1set);
-
- if (addr != TZPC9_BASE) {
- writel(DECPROTXSET, &tzpc->decprot2set);
- writel(DECPROTXSET, &tzpc->decprot3set);
- }
- }
-}
-
static void set_cpu_id(void)
{
cpu_id = readl((void *)EXYNOS5_PRO_ID);
@@ -144,8 +122,6 @@ static void cpu_enable(device_t dev)
exynos_displayport_init(dev, lcdbase, fb_size);
set_cpu_id();
-
- tzpc_init();
}
static void cpu_init(device_t dev)
diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h
index 85b6fae..10f9ef4 100644
--- a/src/cpu/samsung/exynos5250/cpu.h
+++ b/src/cpu/samsung/exynos5250/cpu.h
@@ -67,34 +67,6 @@
/* Marker values stored at the bottom of IRAM stack by SPL */
#define EXYNOS5_SPL_MARKER 0xb004f1a9 /* hexspeak word: bootflag */
-/* Distance between each Trust Zone PC register set */
-#define TZPC_BASE_OFFSET 0x10000
-/* TZPC : Register Offsets */
-#define TZPC0_BASE 0x10100000
-#define TZPC1_BASE 0x10110000
-#define TZPC2_BASE 0x10120000
-#define TZPC3_BASE 0x10130000
-#define TZPC4_BASE 0x10140000
-#define TZPC5_BASE 0x10150000
-#define TZPC6_BASE 0x10160000
-#define TZPC7_BASE 0x10170000
-#define TZPC8_BASE 0x10180000
-#define TZPC9_BASE 0x10190000
-#define TZPC10_BASE 0x100E0000
-#define TZPC11_BASE 0x100F0000
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET 0xFF
-
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
#define EXYNOS_I2C_MAX_CONTROLLERS 8
@@ -107,32 +79,6 @@ extern struct tmu_info exynos5250_tmu_info;
#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
-struct exynos_tzpc {
- u32 r0size;
- u8 res1[0x7FC];
- u32 decprot0stat;
- u32 decprot0set;
- u32 decprot0clr;
- u32 decprot1stat;
- u32 decprot1set;
- u32 decprot1clr;
- u32 decprot2stat;
- u32 decprot2set;
- u32 decprot2clr;
- u32 decprot3stat;
- u32 decprot3set;
- u32 decprot3clr;
- u8 res2[0x7B0];
- u32 periphid0;
- u32 periphid1;
- u32 periphid2;
- u32 periphid3;
- u32 pcellid0;
- u32 pcellid1;
- u32 pcellid2;
- u32 pcellid3;
-};
-
static inline u32 get_fb_base_kb(void)
{
return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;
diff --git a/src/cpu/samsung/exynos5250/trustzone.c b/src/cpu/samsung/exynos5250/trustzone.c
new file mode 100644
index 0000000..d67eb33
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/trustzone.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "trustzone.h"
+
+/* Setting TZPC[TrustZone Protection Controller] */
+void trustzone_init(void)
+{
+ struct exynos_tzpc *tzpc;
+ unsigned int addr;
+
+ for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+ tzpc = (struct exynos_tzpc *)addr;
+
+ if (addr == TZPC0_BASE)
+ writel(R0SIZE, &tzpc->r0size);
+
+ writel(DECPROTXSET, &tzpc->decprot0set);
+ writel(DECPROTXSET, &tzpc->decprot1set);
+
+ if (addr != TZPC9_BASE) {
+ writel(DECPROTXSET, &tzpc->decprot2set);
+ writel(DECPROTXSET, &tzpc->decprot3set);
+ }
+ }
+}
diff --git a/src/cpu/samsung/exynos5250/trustzone.h b/src/cpu/samsung/exynos5250/trustzone.h
new file mode 100644
index 0000000..7b4af9b
--- /dev/null
+++ b/src/cpu/samsung/exynos5250/trustzone.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H
+#define CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H
+
+#include <stdint.h>
+
+/* Distance between each Trust Zone PC register set */
+#define TZPC_BASE_OFFSET 0x10000
+/* TZPC : Register Offsets */
+#define TZPC0_BASE 0x10100000
+#define TZPC1_BASE 0x10110000
+#define TZPC2_BASE 0x10120000
+#define TZPC3_BASE 0x10130000
+#define TZPC4_BASE 0x10140000
+#define TZPC5_BASE 0x10150000
+#define TZPC6_BASE 0x10160000
+#define TZPC7_BASE 0x10170000
+#define TZPC8_BASE 0x10180000
+#define TZPC9_BASE 0x10190000
+#define TZPC10_BASE 0x100E0000
+#define TZPC11_BASE 0x100F0000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+
+struct exynos_tzpc {
+ u32 r0size;
+ u8 res1[0x7FC];
+ u32 decprot0stat;
+ u32 decprot0set;
+ u32 decprot0clr;
+ u32 decprot1stat;
+ u32 decprot1set;
+ u32 decprot1clr;
+ u32 decprot2stat;
+ u32 decprot2set;
+ u32 decprot2clr;
+ u32 decprot3stat;
+ u32 decprot3set;
+ u32 decprot3clr;
+ u8 res2[0x7B0];
+ u32 periphid0;
+ u32 periphid1;
+ u32 periphid2;
+ u32 periphid3;
+ u32 pcellid0;
+ u32 pcellid1;
+ u32 pcellid2;
+ u32 pcellid3;
+};
+
+void trustzone_init(void);
+
+#endif /* CPU_SAMSUNG_EXYNOS5250_TRUSTZONE_H */
diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc
index bb6d8fe..897944c 100644
--- a/src/cpu/samsung/exynos5420/Makefile.inc
+++ b/src/cpu/samsung/exynos5420/Makefile.inc
@@ -35,6 +35,7 @@ romstage-y += timer.c
romstage-y += i2c.c
#romstage-y += wdt.c
romstage-y += cbmem.c
+romstage-y += trustzone.c
ramstage-y += spi.c alternate_cbfs.c
ramstage-y += clock.c
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index a0c33ca..bfb8421 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -37,26 +37,6 @@
static unsigned int cpu_id;
static unsigned int cpu_rev;
-/* Setting TZPC[TrustZone Protection Controller]
- * We pretty much disable it all, as the kernel
- * expects it that way -- and that's not the default.
- */
-static void tzpc_init(void)
-{
- struct exynos_tzpc *tzpc;
- unsigned int addr;
-
- for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
- tzpc = (struct exynos_tzpc *)addr;
- if (addr == TZPC0_BASE)
- writel(R0SIZE, &tzpc->r0size);
- writel(DECPROTXSET, &tzpc->decprot0set);
- writel(DECPROTXSET, &tzpc->decprot1set);
- writel(DECPROTXSET, &tzpc->decprot2set);
- writel(DECPROTXSET, &tzpc->decprot3set);
- }
-}
-
static void set_cpu_id(void)
{
u32 pro_id = (read32((void *)EXYNOS5_PRO_ID) & 0x00FFF000) >> 12;
@@ -172,8 +152,6 @@ static void cpu_enable(device_t dev)
exynos_displayport_init(dev, lcdbase, fb_size);
set_cpu_id();
-
- tzpc_init();
}
static void cpu_init(device_t dev)
diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h
index 847800d..5b5c731 100644
--- a/src/cpu/samsung/exynos5420/cpu.h
+++ b/src/cpu/samsung/exynos5420/cpu.h
@@ -75,34 +75,6 @@
/* Marker values stored at the bottom of IRAM stack by SPL */
#define EXYNOS5_SPL_MARKER 0xb004f1a9 /* hexspeak word: bootflag */
-/* Distance between each Trust Zone PC register set */
-#define TZPC_BASE_OFFSET 0x10000
-/* TZPC : Register Offsets */
-#define TZPC0_BASE 0x10100000
-#define TZPC1_BASE 0x10110000
-#define TZPC2_BASE 0x10120000
-#define TZPC3_BASE 0x10130000
-#define TZPC4_BASE 0x10140000
-#define TZPC5_BASE 0x10150000
-#define TZPC6_BASE 0x10160000
-#define TZPC7_BASE 0x10170000
-#define TZPC8_BASE 0x10180000
-#define TZPC9_BASE 0x10190000
-#define TZPC10_BASE 0x100E0000
-#define TZPC11_BASE 0x100F0000
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE 0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET 0xFF
-
#define RST_FLAG_VAL 0xfcba0d10
#define EXYNOS5_SPI_NUM_CONTROLLERS 5
@@ -115,32 +87,6 @@ extern struct tmu_info exynos5420_tmu_info;
#define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10)
#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
-struct exynos_tzpc {
- u32 r0size;
- u8 res1[0x7FC];
- u32 decprot0stat;
- u32 decprot0set;
- u32 decprot0clr;
- u32 decprot1stat;
- u32 decprot1set;
- u32 decprot1clr;
- u32 decprot2stat;
- u32 decprot2set;
- u32 decprot2clr;
- u32 decprot3stat;
- u32 decprot3set;
- u32 decprot3clr;
- u8 res2[0x7B0];
- u32 periphid0;
- u32 periphid1;
- u32 periphid2;
- u32 periphid3;
- u32 pcellid0;
- u32 pcellid1;
- u32 pcellid2;
- u32 pcellid3;
-};
-
static inline u32 get_fb_base_kb(void)
{
return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;
diff --git a/src/cpu/samsung/exynos5420/trustzone.c b/src/cpu/samsung/exynos5420/trustzone.c
new file mode 100644
index 0000000..7b1489a
--- /dev/null
+++ b/src/cpu/samsung/exynos5420/trustzone.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "trustzone.h"
+
+/* Setting TZPC[TrustZone Protection Controller]
+ * We pretty much disable it all, as the kernel
+ * expects it that way -- and that's not the default.
+ */
+void trustzone_init(void)
+{
+ struct exynos_tzpc *tzpc;
+ unsigned int addr;
+
+ for (addr = TZPC10_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+ tzpc = (struct exynos_tzpc *)addr;
+ if (addr == TZPC0_BASE)
+ writel(R0SIZE, &tzpc->r0size);
+ writel(DECPROTXSET, &tzpc->decprot0set);
+ writel(DECPROTXSET, &tzpc->decprot1set);
+ writel(DECPROTXSET, &tzpc->decprot2set);
+ writel(DECPROTXSET, &tzpc->decprot3set);
+ }
+}
diff --git a/src/cpu/samsung/exynos5420/trustzone.h b/src/cpu/samsung/exynos5420/trustzone.h
new file mode 100644
index 0000000..69e683a
--- /dev/null
+++ b/src/cpu/samsung/exynos5420/trustzone.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H
+#define CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H
+
+#include <stdint.h>
+
+/* Distance between each Trust Zone PC register set */
+#define TZPC_BASE_OFFSET 0x10000
+/* TZPC : Register Offsets */
+#define TZPC0_BASE 0x10100000
+#define TZPC1_BASE 0x10110000
+#define TZPC2_BASE 0x10120000
+#define TZPC3_BASE 0x10130000
+#define TZPC4_BASE 0x10140000
+#define TZPC5_BASE 0x10150000
+#define TZPC6_BASE 0x10160000
+#define TZPC7_BASE 0x10170000
+#define TZPC8_BASE 0x10180000
+#define TZPC9_BASE 0x10190000
+#define TZPC10_BASE 0x100E0000
+#define TZPC11_BASE 0x100F0000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+
+struct exynos_tzpc {
+ u32 r0size;
+ u8 res1[0x7FC];
+ u32 decprot0stat;
+ u32 decprot0set;
+ u32 decprot0clr;
+ u32 decprot1stat;
+ u32 decprot1set;
+ u32 decprot1clr;
+ u32 decprot2stat;
+ u32 decprot2set;
+ u32 decprot2clr;
+ u32 decprot3stat;
+ u32 decprot3set;
+ u32 decprot3clr;
+ u8 res2[0x7B0];
+ u32 periphid0;
+ u32 periphid1;
+ u32 periphid2;
+ u32 periphid3;
+ u32 pcellid0;
+ u32 pcellid1;
+ u32 pcellid2;
+ u32 pcellid3;
+};
+
+void trustzone_init(void);
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H */
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 7967a55..7e096a7 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -33,6 +33,7 @@
#include <cpu/samsung/exynos5420/setup.h>
#include <cpu/samsung/exynos5420/periph.h>
#include <cpu/samsung/exynos5420/power.h>
+#include <cpu/samsung/exynos5420/trustzone.h>
#include <cpu/samsung/exynos5420/wakeup.h>
#include <console/console.h>
#include <arch/stages.h>
@@ -252,6 +253,8 @@ void main(void)
primitive_mem_test();
+ trustzone_init();
+
if (is_resume) {
wakeup();
}
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 44074c5..1c49d35 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -32,6 +32,7 @@
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/power.h>
+#include <cpu/samsung/exynos5250/trustzone.h>
#include <cpu/samsung/exynos5250/wakeup.h>
#include <console/console.h>
#include <arch/stages.h>
@@ -154,6 +155,9 @@ void main(void)
setup_power(is_resume);
setup_memory(mem, is_resume);
+ /* This needs to happen on normal boots and on resume. */
+ trustzone_init();
+
if (is_resume) {
wakeup();
}
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