[coreboot-gerrit] New patch to review for coreboot: 12aaaf2 lenovo/t520: fix PCIe interrupt and function disable config

[Nicolas Reinecke (nr@das-labor.org)]

Nicolas Reinecke (nr at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6758

-gerrit

commit 12aaaf258c74a930fba78abb619a7d6ae25f326e
Author: Nicolas Reinecke <nr at das-labor.org>
Date:   Sun Aug 24 19:49:35 2014 +0200

    lenovo/t520: fix PCIe interrupt and function disable config
    
    Change-Id: I33e71c0a246583885368dc3d3af761c190b2fb5c
    Signed-off-by: Nicolas Reinecke <nr at das-labor.org>
---
 src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl |  6 +++---
 src/mainboard/lenovo/t520/romstage.c                    | 12 ++++++------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl
index 6c1c695..b4b81a2 100644
--- a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl
+++ b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl
@@ -29,9 +29,9 @@ Method(_PRT)
 			// High Definition Audio	0:1b.0
 			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
 			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
-			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
-			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
+			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P2IP  WLAN   INTA -> PIRQB
+			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P4IP  EXC    INTB -> PIRQF
+			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P5IP  SDCARD INTC -> PIRQD
 			// EHCI	#1			0:1d.0
 			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
 			// EHCI	#2			0:1a.0
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index c3cd602..8aef922 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -64,9 +64,9 @@ static void rcba_config(void)
 {
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  WLAN   INTA -> PIRQB
-	 * D28IP_P2IP  ETH0   INTB -> PIRQF
-	 * D28IP_P3IP  SDCARD INTC -> PIRQD
+	 * D28IP_P2IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  EXC    INTB -> PIRQF
+	 * D28IP_P5IP  SDCARD INTC -> PIRQD
 	 * D29IP_E1P   EHCI1  INTA -> PIRQD
 	 * D26IP_E2P   EHCI2  INTA -> PIRQF
 	 * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
@@ -83,8 +83,8 @@ static void rcba_config(void)
 	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
 			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
 	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
-			(INTC << D28IP_P3IP);
+	RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) |
+			(INTC << D28IP_P5IP);
 	RCBA32(D27IP) = (INTA << D27IP_ZIP);
 	RCBA32(D26IP) = (INTA << D26IP_E2P);
 	RCBA32(D25IP) = (NOINT << D25IP_LIP);
@@ -105,7 +105,7 @@ static void rcba_config(void)
 	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17f81fe3;
+	RCBA32(FD) = 0x1ee51fe3;
 	RCBA32(BUC) = 0;
 }