[coreboot-gerrit] New patch to review for coreboot: e014d69 FSP platform microcode: Update to remove Kconfig variable
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Fri Dec 5 02:25:36 CET 2014
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7646
-gerrit
commit e014d69812ffbcaacb9906bfa5414e03b9866a49
Author: Martin Roth <martin.roth at se-eng.com>
Date: Thu Dec 4 18:06:36 2014 -0700
FSP platform microcode: Update to remove Kconfig variable
Move the Kconfig variable into a .h file - this does not need to be
in Kconfig.
Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/cpu/intel/fsp_model_206ax/Kconfig | 6 ------
src/cpu/intel/fsp_model_206ax/Makefile.inc | 1 +
src/cpu/intel/fsp_model_206ax/microcode_blob.h | 4 ++--
src/cpu/intel/fsp_model_206ax/microcode_size.h | 7 +++++++
src/cpu/intel/fsp_model_406dx/Kconfig | 6 ------
src/cpu/intel/fsp_model_406dx/Makefile.inc | 1 +
src/cpu/intel/fsp_model_406dx/microcode_blob.c | 4 ++--
src/cpu/intel/fsp_model_406dx/microcode_size.h | 7 +++++++
src/drivers/intel/fsp/cache_as_ram.inc | 3 ++-
src/soc/intel/fsp_baytrail/Kconfig | 6 ------
src/soc/intel/fsp_baytrail/microcode/Makefile.inc | 1 +
src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 2 +-
src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 ++
13 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig
index 043320c..c05b12b 100644
--- a/src/cpu/intel/fsp_model_206ax/Kconfig
+++ b/src/cpu/intel/fsp_model_206ax/Kconfig
@@ -58,12 +58,6 @@ config CPU_MICROCODE_CBFS_LOC
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff70000
-config CPU_MICROCODE_CBFS_LEN
- hex
- depends on SUPPORT_CPU_UCODE_IN_CBFS
- default 0xC000 if CPU_INTEL_FSP_MODEL_306AX
- default 0x2800 if CPU_INTEL_FSP_MODEL_206AX
-
config MICROCODE_INCLUDE_PATH
string "Location of the intel microcode patches"
default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc
index e3d3ca5..aee3101 100644
--- a/src/cpu/intel/fsp_model_206ax/Makefile.inc
+++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc
@@ -10,5 +10,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
+CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax
endif
endif
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
index e56bef1..6a3eaaf 100644
--- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h
+++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.h
@@ -19,12 +19,12 @@
*/
#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
- /* Size is 0x2800 - Update in Kconfigs when any included file changes*/
+ /* Size is 0x2800 - Update in microcode_size.h when any included file changes*/
#include <microcode-m12206a7_00000029.h>
#endif
#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
- /* Size is 0xC000 - Update in Kconfigs when any included file changes*/
+ /* Size is 0xC000 - Update in microcode_size.h when any included file changes*/
#include <microcode-m12306a2_00000008.h>
#include <microcode-m12306a4_00000007.h>
#include <microcode-m12306a5_00000007.h>
diff --git a/src/cpu/intel/fsp_model_206ax/microcode_size.h b/src/cpu/intel/fsp_model_206ax/microcode_size.h
new file mode 100644
index 0000000..0b0364c
--- /dev/null
+++ b/src/cpu/intel/fsp_model_206ax/microcode_size.h
@@ -0,0 +1,7 @@
+/* Maximum size of the area that the FSP will search for the correct microcode */
+
+#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX)
+ #define MICROCODE_REGION_LENGTH 0xC000
+#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX)
+ #define MICROCODE_REGION_LENGTH 0x2800
+#endif
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 11a92a0..5cd4c65 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -62,12 +62,6 @@ config CPU_MICROCODE_CBFS_LOC
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff60040
-config CPU_MICROCODE_CBFS_LEN
- hex
- depends on SUPPORT_CPU_UCODE_IN_CBFS
- default 0x14400 if FSP_MODEL_406DX_A1
- default 0x14800 if FSP_MODEL_406DX_B0
-
config MICROCODE_INCLUDE_PATH
string "Location of the intel microcode patches"
default "../intel/cpu/rangeley/microcode"
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 767cc20..3516bcc 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -27,5 +27,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
+CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
endif
endif
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
index a4b7d42..74fe76c 100644
--- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c
+++ b/src/cpu/intel/fsp_model_406dx/microcode_blob.c
@@ -20,10 +20,10 @@
unsigned microcode[] = {
#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
- /* Size is 0x14400 */
+ /* Size is 0x14400 - update in microcode_size.h when the file changes */
#include <microcode-m01406d000e.h>
#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
- /* Size is 0x14800 */
+ /* Size is 0x14800 - update in microcode_size.h when the file changes */
#include <microcode-m01406d811d.h>
#endif
};
diff --git a/src/cpu/intel/fsp_model_406dx/microcode_size.h b/src/cpu/intel/fsp_model_406dx/microcode_size.h
new file mode 100644
index 0000000..b638ae5
--- /dev/null
+++ b/src/cpu/intel/fsp_model_406dx/microcode_size.h
@@ -0,0 +1,7 @@
+/* Maximum size of the area that the FSP will search for the correct microcode */
+
+#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1)
+ #define MICROCODE_REGION_LENGTH 0x14400
+#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0)
+ #define MICROCODE_REGION_LENGTH 0x14800
+#endif
diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc
index 0fc33cb..9e8b2a2 100644
--- a/src/drivers/intel/fsp/cache_as_ram.inc
+++ b/src/drivers/intel/fsp/cache_as_ram.inc
@@ -22,6 +22,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
+#include <microcode_size.h>
#include <cbmem.h>
#ifndef CONFIG_FSP_LOC
@@ -158,7 +159,7 @@ fake_fsp_stack:
CAR_init_params:
.long CONFIG_CPU_MICROCODE_CBFS_LOC
- .long CONFIG_CPU_MICROCODE_CBFS_LEN
+ .long MICROCODE_REGION_LENGTH
.long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */
.long CACHE_ROM_SIZE /* Total Firmware Length */
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index e9391c3..85b3d32 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -102,12 +102,6 @@ config CPU_MICROCODE_CBFS_LOC
hex
default 0xfff10040
-config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x19800
- help
- This should be updated when the microcode patch changes.
-
config CBFS_SIZE
hex
default 0x200000
diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
index f6ee135..3a17acb 100644
--- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc
@@ -21,5 +21,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
+CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode
endif
endif
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
index 43cbf00..51b6c19 100644
--- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
+++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c
@@ -19,7 +19,7 @@
unsigned microcode[] = {
-/* Size is 0x19800 - update in Kconfig when the patch gets updated. */
+/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */
#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1
#include "M013067331E.h" // M0130673: Baytrail I B2 / B3
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
new file mode 100644
index 0000000..df6082d
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h
@@ -0,0 +1,2 @@
+/* Maximum size of the area that the FSP will search for the correct microcode */
+#define MICROCODE_REGION_LENGTH 0x19800
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