[coreboot-gerrit] Patch set updated for coreboot: b2857c4 northbridge/amd/gx2/northbridgeinit.c: Silence compiler warn

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7720

-gerrit

commit b2857c449f91ca44982e4c37a4903ef14ff2a1ab
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Tue Dec 9 03:42:42 2014 +1100

    northbridge/amd/gx2/northbridgeinit.c: Silence compiler warn
    
    Clang complains that a signed shift result (0x4040000000)
    requires 40 bits to represent, but 'int' only has 32 bits.
    However, we write the high bits seperately and so this is
    a spurious warning.
    
    Change-Id: Ib04737f7eb7ba14fa43a37b70a7f6e1a3c1d6d41
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/northbridge/amd/gx2/northbridgeinit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 0cb7803..3bbaab0 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -181,7 +181,7 @@ static void SMMGL0Init(struct gliutable *gl)
 	msr.hi = offset << 8 | gl->hi;
 	msr.hi |= SMM_OFFSET >> 24;
 
-	msr.lo = SMM_OFFSET << 8;
+	msr.lo = (uint32_t) ((uint64_t) SMM_OFFSET << 8ULL);
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
@@ -197,7 +197,7 @@ static void SMMGL1Init(struct gliutable *gl)
 	/* I don't think this is needed */
 	msr.hi &= 0xffffff00;
 	msr.hi |= (SMM_OFFSET >> 24);
-	msr.lo = (SMM_OFFSET << 8) & 0xfff00000;
+	msr.lo = ((uint32_t) ((uint64_t) SMM_OFFSET << 8ULL)) & 0xfff00000;
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */