[coreboot-gerrit] New patch to review for coreboot: ca9d7f1 arm: Fix minor mistake in cache maintenance assembly

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7745

-gerrit

commit ca9d7f1ca9cb7a7586af4c7c170a3f5d9893928a
Author: Julius Werner <jwerner at chromium.org>
Date:   Fri Apr 4 14:01:15 2014 -0700

    arm: Fix minor mistake in cache maintenance assembly
    
    Turns out that when you clear 28 bits starting with bit 3, you leave bit
    31 standing. Ooops...
    
    This shouldn't really matter since that bit is reserved/SBZ in CLIDR
    anyway, but it's still nice to fix it. This whole thing should really be
    an AND for clarity anyway in my opinion.
    
    Bug found in upstream NetBSD (who would've thought...).
    
    BUG=None
    TEST=Still boots.
    
    Change-Id: Ic826e82d58fd1ce984971afea3dfa9296f746d9f
    Signed-off-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193300
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit d270c0ec18b74b272451c456cbf07e99d95896cb)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
 payloads/libpayload/arch/arm/cpu.S | 2 +-
 src/arch/arm/armv7/cpu.S           | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/arch/arm/cpu.S b/payloads/libpayload/arch/arm/cpu.S
index 29a19e7..4a1d41d 100644
--- a/payloads/libpayload/arch/arm/cpu.S
+++ b/payloads/libpayload/arch/arm/cpu.S
@@ -60,7 +60,7 @@
 
 	add	r2, r3, r3, lsr #1	@ r2 = (level << 1) * 3 / 2
 	mov	r1, r0, lsr r2		@ r1 = cache type
-	bfc	r1, #3, #28
+	and	r1, r1, #7
 	cmp	r1, #2			@ is it data or i&d?
 	blt	1b @next_level		@ nope, skip level
 
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index 5738116..589bc07 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -60,7 +60,7 @@
 
 	add	r2, r3, r3, lsr #1	@ r2 = (level << 1) * 3 / 2
 	mov	r1, r0, lsr r2		@ r1 = cache type
-	bfc	r1, #3, #28
+	and	r1, r1, #7
 	cmp	r1, #2			@ is it data or i&d?
 	blt	1b @next_level		@ nope, skip level