[coreboot-gerrit] Patch set updated for coreboot: bca3d70 nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 register

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7767

-gerrit

commit bca3d70bde1cf4c1cc58692ccc74c58f1efe2529
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Mon Apr 14 12:47:37 2014 -0700

    nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 register
    
    This register needs to be set properly during display init.
    
    BRANCH=none
    BUG=chrome-os-partner:27413
    TEST=build nyan and nyan_big. nyan display works fine.
         nyan_big display works as well. However, the mode setting
         needs to be based on either devicetree or EDID.
    
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    
    Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031
    Original-Reviewed-on: https://chromium-review.googlesource.com/194739
    Original-Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Original-Commit-Queue: Hung-Te Lin <hungte at chromium.org>
    Original-Tested-by: Hung-Te Lin <hungte at chromium.org>
    (cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c
---
 src/soc/nvidia/tegra124/dp.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index cc341b8..ad6c0da 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -618,6 +618,22 @@ static int tegra_dc_dp_init_link_cfg(
 	return 0;
 }
 
+static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, int ena)
+{
+	int ret;
+
+	u8 dpcd_data = ena ?
+		NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE :
+		NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE;
+
+	CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET,
+			dpcd_data));
+
+	/* Also reset the scrambler to 0xfffe */
+	tegra_dc_sor_set_internal_panel(&dp->sor, ena);
+	return 0;
+}
+
 static void tegra_dp_update_config(struct tegra_dc_dp_data *dp,
 				   struct soc_nvidia_tegra124_config *config)
 {
@@ -738,6 +754,12 @@ void dp_enable(void * _dp)
 		goto error_enable;
         }
 
+	/* enable ASSR */
+	if (tegra_dc_dp_set_assr(dp, dp->link_cfg.scramble_ena)) {
+		printk(BIOS_ERR, "dp: failed to enable ASSR\n");
+		goto error_enable;
+        }
+
 	tegra_dc_sor_enable_dp(&dp->sor);
 
 	tegra_dc_sor_set_panel_power(&dp->sor, 1);