[coreboot-gerrit] New patch to review for coreboot: 5242471 AGESA fam12: Fix MMCONF region

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7812

-gerrit

commit 5242471face00a0677faa34bbcdbb6e5b6eb8d35
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sun Dec 14 16:36:09 2014 +0200

    AGESA fam12: Fix MMCONF region
    
    MMIO for non-posted region used hard-coded setting for 64 buses
    while MSR programming was for 256 buses.
    
    Change-Id: I690237dd459f7b7b4da68ae55ae9d22b79e5f255
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/amd/agesa/family12/agesawrapper.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c
index 0c441ee..d2aa330 100644
--- a/src/northbridge/amd/agesa/family12/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family12/agesawrapper.c
@@ -151,7 +151,7 @@ AGESA_STATUS agesawrapper_amdinitcpuio(VOID)
 	PciData = 0x00FFFF00 | 0x80;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8);
-	PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
+	PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
@@ -176,7 +176,7 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
 	   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
 	   Address MSR register.
 	 */
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
 
 	/*
@@ -187,7 +187,9 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
 	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
 
 	/* Enable Non-Post Memory in CPU */
-	PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
+	PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
+	PciData = (PciData >> 8) & ~0xff;
+	PciData |= 0x80;
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
@@ -198,7 +200,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
 	/* Enable memory access */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
 	LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
-
 	PciData |= BIT1;
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
 	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);