[coreboot-gerrit] New patch to review for coreboot: 524c525 CBMEM: Tag chipsets with LATE_CBMEM_INIT
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Dec 17 17:58:51 CET 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7850
-gerrit
commit 524c5257ffc099a51a121b7202ded6330d2c3845
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Nov 11 00:49:07 2014 +0200
CBMEM: Tag chipsets with LATE_CBMEM_INIT
In preparation to remove the static CBMEM allocator, tag the chipsets
that still do not implement get_top_of_ram() for romstage.
The lack of CBMEM in romstage also implies no CAR migration.
Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/Kconfig | 19 +++++++++----------
src/arch/x86/boot/Makefile.inc | 3 +--
src/arch/x86/boot/cbmem.c | 17 ++++++++++-------
src/include/cbmem.h | 15 +++++++++++----
src/lib/cbmem_console.c | 2 +-
src/lib/dynamic_cbmem.c | 31 +++++++++++++++++++++++++++++--
src/northbridge/amd/agesa/Kconfig | 1 +
src/northbridge/amd/amdfam10/Kconfig | 1 +
src/northbridge/amd/amdk8/Kconfig | 1 +
src/northbridge/amd/gx2/Kconfig | 1 +
src/northbridge/amd/lx/Kconfig | 1 +
src/northbridge/dmp/vortex86ex/Kconfig | 1 +
src/northbridge/intel/e7501/Kconfig | 1 +
src/northbridge/intel/e7505/Kconfig | 1 +
src/northbridge/intel/e7520/Kconfig | 1 +
src/northbridge/intel/e7525/Kconfig | 1 +
src/northbridge/intel/i3100/Kconfig | 1 +
src/northbridge/intel/i440bx/Kconfig | 1 +
src/northbridge/intel/i440lx/Kconfig | 1 +
src/northbridge/intel/i5000/Kconfig | 1 +
src/northbridge/intel/i82810/Kconfig | 1 +
src/northbridge/intel/i82830/Kconfig | 1 +
src/northbridge/intel/i855/Kconfig | 1 +
src/northbridge/intel/sch/Kconfig | 1 +
src/northbridge/rdc/r8610/Kconfig | 1 +
src/northbridge/via/cn400/Kconfig | 1 +
src/northbridge/via/cn700/Kconfig | 1 +
src/northbridge/via/cx700/Kconfig | 1 +
src/northbridge/via/vt8601/Kconfig | 1 +
src/northbridge/via/vt8623/Kconfig | 1 +
src/northbridge/via/vx900/Kconfig | 1 +
src/southbridge/amd/amd8131/Kconfig | 1 +
32 files changed, 87 insertions(+), 26 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 7b52589..6a7b809 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -149,18 +149,18 @@ config INCLUDE_CONFIG_FILE
(empty) 0x8e480 null 3610440
config EARLY_CBMEM_INIT
- bool
- default n
+ def_bool !LATE_CBMEM_INIT
+
+config LATE_CBMEM_INIT
+ def_bool n
+ select BROKEN_CAR_MIGRATE
help
- Make coreboot initialize the CBMEM structures while running in ROM
- stage. This is useful when the ROM stage wants to communicate
- some, for instance, execution timestamps. It needs support in
- romstage.c and should be enabled by the board's Kconfig.
+ Enable this in chipset's Kconfig if northbridge does not implement
+ early get_top_of_ram() call for romstage. CBMEM tables will be
+ allocated late in ramstage, after PCI devices resources are known.
config BROKEN_CAR_MIGRATE
- bool
- default y if !EARLY_CBMEM_INIT && HAVE_ACPI_RESUME
- default n
+ def_bool n
help
Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and
manage CAR migration on S3 resume path only. Couple boards use
@@ -169,7 +169,6 @@ config BROKEN_CAR_MIGRATE
config DYNAMIC_CBMEM
bool
default n
- select EARLY_CBMEM_INIT
help
Instead of reserving a static amount of CBMEM space the CBMEM
area grows dynamically. CBMEM can be used both in romstage (after
diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc
index 9a68d81..9f06b4f 100644
--- a/src/arch/x86/boot/Makefile.inc
+++ b/src/arch/x86/boot/Makefile.inc
@@ -1,8 +1,7 @@
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
-romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c
-romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += cbmem.c
+romstage-y += cbmem.c
endif # CONFIG_ARCH_ROMSTAGE_X86_32
diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c
index 8b2b6da..95de062 100644
--- a/src/arch/x86/boot/cbmem.c
+++ b/src/arch/x86/boot/cbmem.c
@@ -33,6 +33,9 @@ void get_cbmem_table(uint64_t *base, uint64_t *size)
*size = 0;
}
}
+#endif /* !DYNAMIC_CBMEM */
+
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
#if !defined(__PRE_RAM__)
void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop)
@@ -40,26 +43,26 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop)
/* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */
}
-/* This is for compatibility with old boards only. Any new chipset and board
- * must implement get_top_of_ram() for both romstage and ramstage to support
- * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE.
- */
void set_top_of_ram(uint64_t ramtop)
{
backup_top_of_ram(ramtop);
+#if !CONFIG_DYNAMIC_CBMEM
cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE);
+#else
+ cbmem_set_top(ramtop);
+#endif
}
#endif /* !__PRE_RAM__ */
-#if CONFIG_BROKEN_CAR_MIGRATE || !defined(__PRE_RAM__)
unsigned long __attribute__((weak)) get_top_of_ram(void)
{
printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n");
return 0;
}
-#endif
-#else
+#endif /* LATE_CBMEM_INIT */
+
+#if CONFIG_DYNAMIC_CBMEM
void *cbmem_top(void)
{
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 0b2eba7..589ce01 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -114,6 +114,8 @@ void cbmem_initialize_empty(void);
* below 4GiB. */
void *cbmem_top(void);
+void cbmem_set_top(uint64_t ramtop);
+
/* Add a cbmem entry of a given size and id. These return NULL on failure. The
* add function performs a find first and do not check against the original
* size. */
@@ -146,13 +148,9 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry);
#define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000)
-
#ifndef __PRE_RAM__
-void set_top_of_ram(uint64_t ramtop);
-void backup_top_of_ram(uint64_t ramtop);
void cbmem_late_set_table(uint64_t base, uint64_t size);
#endif
-
void get_cbmem_table(uint64_t *base, uint64_t *size);
struct cbmem_entry *get_cbmem_toc(void);
@@ -189,6 +187,15 @@ static inline void cbmem_arch_init(void) {}
static inline void cbmem_fail_resume(void) {}
#endif /* __PRE_RAM__ */
+/* These are for compatibility with old boards only. Any new chipset and board
+ * must implement get_top_of_ram() for both romstage and ramstage to support
+ * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE.
+ */
+#if !defined(__PRE_RAM__)
+void set_top_of_ram(uint64_t ramtop);
+void backup_top_of_ram(uint64_t ramtop);
+#endif
+
#endif /* __ASSEMBLER__ */
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index 997bb7d..b48d6ac 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -55,7 +55,7 @@ extern struct cbmem_console preram_cbmem_console;
* during the ROM stage, once CBMEM becomes available at RAM stage.
*/
-#if CONFIG_DYNAMIC_CBMEM
+#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
#define STATIC_CONSOLE_SIZE 1024
#else
#define STATIC_CONSOLE_SIZE CONFIG_CONSOLE_CBMEM_BUFFER_SIZE
diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c
index 5eddbca..3a6fac2 100644
--- a/src/lib/dynamic_cbmem.c
+++ b/src/lib/dynamic_cbmem.c
@@ -70,11 +70,18 @@ struct cbmem_root {
} __attribute__((packed));
+#if !defined(__PRE_RAM__)
+static void *cached_cbmem_top;
+
+void cbmem_set_top(uint64_t ramtop)
+{
+ cached_cbmem_top = (void*) ramtop;
+}
+#endif
+
static inline void *cbmem_top_cached(void)
{
#if !defined(__PRE_RAM__)
- static void *cached_cbmem_top;
-
if (cached_cbmem_top == NULL)
cached_cbmem_top = cbmem_top();
@@ -420,6 +427,8 @@ void *cbmem_entry_start(const struct cbmem_entry *entry)
#if !defined(__PRE_RAM__)
+
+#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
/* selected cbmem can be initialized early in ramstage. Additionally, that
* means cbmem console can be reinitialized early as well. The post_device
* function is empty since cbmem was initialized early in ramstage. */
@@ -434,6 +443,24 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = {
init_cbmem_pre_device, NULL),
};
+#else
+
+static void init_cbmem_post_device(void *unused)
+{
+ if (acpi_is_wakeup())
+ cbmem_initialize();
+ else
+ cbmem_initialize_empty();
+
+ cbmemc_reinit();
+}
+
+BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = {
+ BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY,
+ init_cbmem_post_device, NULL),
+};
+#endif
+
void cbmem_add_bootmem(void)
{
unsigned long base;
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index 68551fb..8fd8bfd 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -20,6 +20,7 @@
config NORTHBRIDGE_AMD_AGESA
bool
default CPU_AMD_AGESA
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_AGESA
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 0789ac3..13b912e 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -25,6 +25,7 @@ config NORTHBRIDGE_AMD_AMDFAM10
select HYPERTRANSPORT_PLUGIN_SUPPORT
select MMCONF_SUPPORT
select PER_DEVICE_ACPI_TABLES
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_AMDFAM10
config AGP_APERTURE_SIZE
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 8bee5ca..65dc173 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -24,6 +24,7 @@ config NORTHBRIDGE_AMD_AMDK8
select HAVE_DEBUG_CAR
select HYPERTRANSPORT_PLUGIN_SUPPORT
select PER_DEVICE_ACPI_TABLES
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_AMDK8
config AGP_APERTURE_SIZE
diff --git a/src/northbridge/amd/gx2/Kconfig b/src/northbridge/amd/gx2/Kconfig
index dc347c4..1fe33f8 100644
--- a/src/northbridge/amd/gx2/Kconfig
+++ b/src/northbridge/amd/gx2/Kconfig
@@ -20,6 +20,7 @@
config NORTHBRIDGE_AMD_GX2
bool
select GEODE_VSA
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_GX2
diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig
index d74d715..abc3e4c 100644
--- a/src/northbridge/amd/lx/Kconfig
+++ b/src/northbridge/amd/lx/Kconfig
@@ -1,6 +1,7 @@
config NORTHBRIDGE_AMD_LX
bool
select GEODE_VSA
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_LX
diff --git a/src/northbridge/dmp/vortex86ex/Kconfig b/src/northbridge/dmp/vortex86ex/Kconfig
index 7bf5235..74239ad 100644
--- a/src/northbridge/dmp/vortex86ex/Kconfig
+++ b/src/northbridge/dmp/vortex86ex/Kconfig
@@ -19,3 +19,4 @@
config NORTHBRIDGE_DMP_VORTEX86EX
bool
+ select LATE_CBMEM_INIT
diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig
index 88c0b45..763b96e 100644
--- a/src/northbridge/intel/e7501/Kconfig
+++ b/src/northbridge/intel/e7501/Kconfig
@@ -2,4 +2,5 @@ config NORTHBRIDGE_INTEL_E7501
bool
select HAVE_DEBUG_RAM_SETUP
select PER_DEVICE_ACPI_TABLES
+ select LATE_CBMEM_INIT
diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
index ff7f5a5..e755852 100644
--- a/src/northbridge/intel/e7505/Kconfig
+++ b/src/northbridge/intel/e7505/Kconfig
@@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
select PER_DEVICE_ACPI_TABLES
+ select LATE_CBMEM_INIT
config HW_SCRUBBER
bool
diff --git a/src/northbridge/intel/e7520/Kconfig b/src/northbridge/intel/e7520/Kconfig
index ef2b7f6..1fe306b 100644
--- a/src/northbridge/intel/e7520/Kconfig
+++ b/src/northbridge/intel/e7520/Kconfig
@@ -1,5 +1,6 @@
config NORTHBRIDGE_INTEL_E7520
bool
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_INTEL_E7520
config DIMM_MAP_LOGICAL
diff --git a/src/northbridge/intel/e7525/Kconfig b/src/northbridge/intel/e7525/Kconfig
index 04e3d8b..a081dac 100644
--- a/src/northbridge/intel/e7525/Kconfig
+++ b/src/northbridge/intel/e7525/Kconfig
@@ -1,5 +1,6 @@
config NORTHBRIDGE_INTEL_E7525
bool
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_INTEL_E7525
config DIMM_MAP_LOGICAL
diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig
index 079004b..cb0bd38 100644
--- a/src/northbridge/intel/i3100/Kconfig
+++ b/src/northbridge/intel/i3100/Kconfig
@@ -1,5 +1,6 @@
config NORTHBRIDGE_INTEL_I3100
bool
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_INTEL_I3100
config DIMM_MAP_LOGICAL
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index 902eb73..c5cc43e 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -20,6 +20,7 @@
config NORTHBRIDGE_INTEL_I440BX
bool
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
config SDRAMPWR_4DIMM
bool
diff --git a/src/northbridge/intel/i440lx/Kconfig b/src/northbridge/intel/i440lx/Kconfig
index a88a7a1..1ccaac6 100644
--- a/src/northbridge/intel/i440lx/Kconfig
+++ b/src/northbridge/intel/i440lx/Kconfig
@@ -20,4 +20,5 @@
config NORTHBRIDGE_INTEL_I440LX
bool
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
index f7344ca..3bd685a 100644
--- a/src/northbridge/intel/i5000/Kconfig
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_I5000
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_INTEL_I5000
diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig
index 79fe36a..723f751 100644
--- a/src/northbridge/intel/i82810/Kconfig
+++ b/src/northbridge/intel/i82810/Kconfig
@@ -20,6 +20,7 @@
config NORTHBRIDGE_INTEL_I82810
bool
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
choice
prompt "Onboard graphics"
diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig
index 20b31a2..662840f 100644
--- a/src/northbridge/intel/i82830/Kconfig
+++ b/src/northbridge/intel/i82830/Kconfig
@@ -1,6 +1,7 @@
config NORTHBRIDGE_INTEL_I82830
bool
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
choice
prompt "Onboard graphics"
diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig
index f5c2890..44becf6 100644
--- a/src/northbridge/intel/i855/Kconfig
+++ b/src/northbridge/intel/i855/Kconfig
@@ -1,6 +1,7 @@
config NORTHBRIDGE_INTEL_I855
bool
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
choice
prompt "Onboard graphics"
diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig
index b8dad72..f495e6a 100644
--- a/src/northbridge/intel/sch/Kconfig
+++ b/src/northbridge/intel/sch/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_SCH
bool
select MMCONF_SUPPORT
select PER_DEVICE_ACPI_TABLES
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_INTEL_SCH
diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig
index 85461b7..e93a3e6 100644
--- a/src/northbridge/rdc/r8610/Kconfig
+++ b/src/northbridge/rdc/r8610/Kconfig
@@ -1,2 +1,3 @@
config NORTHBRIDGE_RDC_R8610
bool
+ select LATE_CBMEM_INIT
diff --git a/src/northbridge/via/cn400/Kconfig b/src/northbridge/via/cn400/Kconfig
index 42fa096..6aceceb 100644
--- a/src/northbridge/via/cn400/Kconfig
+++ b/src/northbridge/via/cn400/Kconfig
@@ -1,5 +1,6 @@
config NORTHBRIDGE_VIA_CN400
bool
+ select LATE_CBMEM_INIT
# TODO: Values are from the CX700 datasheet, not sure if this matches CN400.
# TODO: What should be the per-chipset default value here?
diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig
index 34c330e..15c86eb 100644
--- a/src/northbridge/via/cn700/Kconfig
+++ b/src/northbridge/via/cn700/Kconfig
@@ -1,6 +1,7 @@
config NORTHBRIDGE_VIA_CN700
bool
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
# TODO: Values are from the CX700 datasheet, not sure if this matches CN700.
# TODO: What should be the per-chipset default value here?
diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig
index 8f6e337..03014eb 100644
--- a/src/northbridge/via/cx700/Kconfig
+++ b/src/northbridge/via/cx700/Kconfig
@@ -5,6 +5,7 @@ config NORTHBRIDGE_VIA_CX700
select HAVE_HARD_RESET
select IOAPIC
select SMP
+ select LATE_CBMEM_INIT
# TODO: What should be the per-chipset default value here?
choice
diff --git a/src/northbridge/via/vt8601/Kconfig b/src/northbridge/via/vt8601/Kconfig
index 1b20267..517343b 100644
--- a/src/northbridge/via/vt8601/Kconfig
+++ b/src/northbridge/via/vt8601/Kconfig
@@ -1,4 +1,5 @@
config NORTHBRIDGE_VIA_VT8601
bool
select HAVE_DEBUG_RAM_SETUP
+ select LATE_CBMEM_INIT
diff --git a/src/northbridge/via/vt8623/Kconfig b/src/northbridge/via/vt8623/Kconfig
index c2aa82b..050773b 100644
--- a/src/northbridge/via/vt8623/Kconfig
+++ b/src/northbridge/via/vt8623/Kconfig
@@ -1,3 +1,4 @@
config NORTHBRIDGE_VIA_VT8623
bool
+ select LATE_CBMEM_INIT
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 9fe5909..617074f 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -26,6 +26,7 @@ config NORTHBRIDGE_VIA_VX900
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
+ select LATE_CBMEM_INIT
if NORTHBRIDGE_VIA_VX900
diff --git a/src/southbridge/amd/amd8131/Kconfig b/src/southbridge/amd/amd8131/Kconfig
index 6093a56..d7a7834 100644
--- a/src/southbridge/amd/amd8131/Kconfig
+++ b/src/southbridge/amd/amd8131/Kconfig
@@ -19,4 +19,5 @@
config SOUTHBRIDGE_AMD_AMD8131
bool
+ select LATE_CBMEM_INIT
More information about the coreboot-gerrit
mailing list