[coreboot-gerrit] Patch set updated for coreboot: d1bd733 tegra124: Add a utility function to read the cause of the most recent reset.

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7899

-gerrit

commit d1bd733e465c37d2e3fd4b41ff09d7317d53cdb6
Author: Gabe Black <gabeblack at google.com>
Date:   Tue May 6 15:33:37 2014 -0700

    tegra124: Add a utility function to read the cause of the most recent reset.
    
    When a watchdog reset happens, the SOC will reset but other parts of the
    system might not. In order to detect those situations we can check the
    rst_status register in the PMC.
    
    BUG=chrome-os-partner:28559
    TEST=With this and a change which uses the new function in the nyan boards,
    built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset,
    software reset ("reboot" command from the terminal), and through watch dog
    reset. Verified that the new code only triggered during the watchdog reset and
    that the system rebooted and was able to boot without going into recovery mode
    unnecessarily.
    BRANCH=nyan
    
    Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/198581
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72
---
 src/soc/nvidia/tegra124/Makefile.inc |  1 +
 src/soc/nvidia/tegra124/power.c      |  5 +++++
 src/soc/nvidia/tegra124/power.h      | 11 +++++++++++
 3 files changed, 17 insertions(+)

diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index fe66d43..c7b2e16 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -26,6 +26,7 @@ romstage-y += early_display.c
 romstage-y += dma.c
 romstage-y += i2c.c
 romstage-y += monotonic_timer.c
+romstage-y += power.c
 romstage-y += sdram.c
 romstage-y += sdram_lp0.c
 romstage-y += spi.c
diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c
index a3cf5ef..760d058 100644
--- a/src/soc/nvidia/tegra124/power.c
+++ b/src/soc/nvidia/tegra124/power.c
@@ -85,3 +85,8 @@ void power_ungate_cpu(void)
 	// Ungate power to CPU0 in the fast cluster.
 	power_ungate_partition(POWER_PARTID_CE0);
 }
+
+int power_reset_status(void)
+{
+	return read32(&pmc->rst_status) & 0x7;
+}
diff --git a/src/soc/nvidia/tegra124/power.h b/src/soc/nvidia/tegra124/power.h
index 6454699..130ed25 100644
--- a/src/soc/nvidia/tegra124/power.h
+++ b/src/soc/nvidia/tegra124/power.h
@@ -26,4 +26,15 @@ void power_enable_cpu_rail(void);
 
 void power_ungate_cpu(void);
 
+// power_reset_status returns one of the following possible sources for the
+// most recent reset.
+enum {
+	POWER_RESET_POR = 0,
+	POWER_RESET_WATCHDOG = 1,
+	POWER_RESET_SENSOR = 2,
+	POWER_RESET_SW_MAIN = 3,
+	POWER_RESET_LP0 = 4
+};
+int power_reset_status(void);
+
 #endif	/* __SOC_NVIDIA_TEGRA124_POWER_H__ */