[coreboot-gerrit] Patch set updated for coreboot: 452eaa4 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to a pointer
Kevin Paul Herbert (kph@meraki.net)
gerrit at coreboot.org
Thu Dec 25 03:52:54 CET 2014
Kevin Paul Herbert (kph at meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7784
-gerrit
commit 452eaa4766d287f9ff25b7fee0f435e1420c7da6
Author: Kevin Paul Herbert <kph at meraki.net>
Date: Wed Dec 24 18:43:20 2014 -0800
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to a pointer
On x86, change the type of the address parameter in read8()/read16/read32()/
write8()/write16()/write32() to be a pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph at meraki.net>
---
src/arch/x86/boot/mpspec.c | 2 +-
src/arch/x86/include/arch/ebda.h | 6 +-
src/arch/x86/include/arch/io.h | 12 +-
src/arch/x86/include/arch/ioapic.h | 10 +-
src/arch/x86/include/arch/pci_mmio_cfg.h | 24 +-
src/arch/x86/include/arch/smp/mpspec.h | 4 +-
src/arch/x86/lib/ebda.c | 2 +-
src/arch/x86/lib/ioapic.c | 18 +-
src/arch/x86/lib/pci_ops_mmconf.c | 12 +-
src/device/azalia_device.c | 47 +-
src/device/oprom/realmode/x86.c | 2 +-
src/drivers/ati/ragexl/atyfb.h | 12 +-
src/drivers/generic/ioapic/chip.h | 2 +-
src/drivers/generic/ioapic/ioapic.c | 6 +-
src/drivers/intel/gma/edid.c | 24 +-
src/drivers/intel/gma/edid.h | 2 +-
src/drivers/usb/ehci_debug.c | 106 +-
src/drivers/usb/pci_ehci.c | 4 +-
src/lib/reg_script.c | 12 +-
src/mainboard/advansus/a785e-i/mptable.c | 2 +-
src/mainboard/amd/bimini_fam10/mptable.c | 2 +-
src/mainboard/amd/dbm690t/mptable.c | 3 +-
src/mainboard/amd/dinar/mptable.c | 6 +-
src/mainboard/amd/inagua/mptable.c | 6 +-
src/mainboard/amd/mahogany/mptable.c | 3 +-
src/mainboard/amd/mahogany_fam10/mptable.c | 3 +-
src/mainboard/amd/olivehill/mptable.c | 8 +-
src/mainboard/amd/olivehillplus/mptable.c | 8 +-
src/mainboard/amd/parmer/mptable.c | 6 +-
src/mainboard/amd/persimmon/mptable.c | 6 +-
src/mainboard/amd/pistachio/mptable.c | 3 +-
src/mainboard/amd/serengeti_cheetah/mptable.c | 12 +-
.../amd/serengeti_cheetah_fam10/mptable.c | 12 +-
src/mainboard/amd/south_station/mptable.c | 6 +-
src/mainboard/amd/thatcher/mptable.c | 6 +-
src/mainboard/amd/tilapia_fam10/mptable.c | 3 +-
src/mainboard/amd/torpedo/mptable.c | 8 +-
src/mainboard/amd/union_station/mptable.c | 6 +-
src/mainboard/apple/macbook21/mptable.c | 2 +-
src/mainboard/arima/hdama/mptable.c | 6 +-
src/mainboard/asrock/939a785gmh/mptable.c | 3 +-
src/mainboard/asrock/e350m1/mptable.c | 6 +-
src/mainboard/asrock/imb-a180/mptable.c | 8 +-
src/mainboard/asus/a8n_e/mptable.c | 2 +-
src/mainboard/asus/a8v-e_deluxe/mptable.c | 4 +-
src/mainboard/asus/a8v-e_se/mptable.c | 4 +-
src/mainboard/asus/dsbf/devicetree.cb | 4 +-
src/mainboard/asus/dsbf/romstage.c | 14 +-
src/mainboard/asus/f2a85-m/mptable.c | 6 +-
src/mainboard/asus/k8v-x/mptable.c | 4 +-
src/mainboard/asus/m2n-e/mptable.c | 2 +-
src/mainboard/asus/m2v/mptable.c | 4 +-
src/mainboard/asus/m4a78-em/mptable.c | 3 +-
src/mainboard/asus/m4a785-m/mptable.c | 3 +-
src/mainboard/asus/m5a88-v/mptable.c | 2 +-
src/mainboard/asus/p2b-d/mptable.c | 2 +-
src/mainboard/asus/p2b-ds/mptable.c | 2 +-
src/mainboard/avalue/eax-785e/mptable.c | 2 +-
src/mainboard/broadcom/blast/mptable.c | 4 +-
src/mainboard/getac/p470/mptable.c | 2 +-
src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +-
src/mainboard/gigabyte/m57sli/mptable.c | 2 +-
src/mainboard/gigabyte/ma785gm/mptable.c | 3 +-
src/mainboard/gigabyte/ma785gmt/mptable.c | 3 +-
src/mainboard/gigabyte/ma78gm/mptable.c | 3 +-
src/mainboard/gizmosphere/gizmo/mptable.c | 6 +-
src/mainboard/gizmosphere/gizmo2/mptable.c | 6 +-
src/mainboard/hp/dl145_g1/mptable.c | 6 +-
src/mainboard/hp/dl145_g3/mptable.c | 2 +-
src/mainboard/hp/dl165_g6_fam10/mptable.c | 2 +-
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 6 +-
src/mainboard/ibase/mb899/mptable.c | 2 +-
src/mainboard/ibm/e325/mptable.c | 6 +-
src/mainboard/ibm/e326/mptable.c | 6 +-
src/mainboard/iei/kino-780am2-fam10/mptable.c | 3 +-
src/mainboard/intel/d945gclf/mptable.c | 2 +-
src/mainboard/intel/eagleheights/mptable.c | 18 +-
src/mainboard/intel/eagleheights/romstage.c | 22 +-
src/mainboard/intel/mohonpeak/romstage.c | 20 +-
src/mainboard/intel/mtarvon/mptable.c | 2 +-
src/mainboard/intel/truxton/mptable.c | 2 +-
src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +-
src/mainboard/iwill/dk8_htx/mptable.c | 10 +-
src/mainboard/iwill/dk8s2/mptable.c | 6 +-
src/mainboard/iwill/dk8x/mptable.c | 6 +-
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 6 +-
src/mainboard/jetway/pa78vm5/mptable.c | 3 +-
src/mainboard/kontron/986lcd-m/mptable.c | 2 +-
src/mainboard/kontron/kt690/mptable.c | 3 +-
src/mainboard/lenovo/g505s/mptable.c | 6 +-
src/mainboard/lenovo/t60/mptable.c | 2 +-
src/mainboard/lenovo/x200/devicetree.cb | 2 +-
src/mainboard/lenovo/x60/mptable.c | 2 +-
src/mainboard/lippert/frontrunner-af/mptable.c | 6 +-
src/mainboard/lippert/toucan-af/mptable.c | 6 +-
src/mainboard/msi/ms7135/mptable.c | 2 +-
src/mainboard/msi/ms7260/mptable.c | 2 +-
src/mainboard/msi/ms9185/mptable.c | 2 +-
src/mainboard/msi/ms9282/mptable.c | 2 +-
src/mainboard/msi/ms9652_fam10/mptable.c | 2 +-
src/mainboard/newisys/khepri/mptable.c | 6 +-
src/mainboard/nvidia/l1_2pvv/mptable.c | 4 +-
src/mainboard/roda/rk886ex/mptable.c | 2 +-
src/mainboard/roda/rk9/devicetree.cb | 2 +-
src/mainboard/samsung/lumpy/devicetree.cb | 2 +-
src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +-
src/mainboard/sunw/ultra40/mptable.c | 8 +-
src/mainboard/supermicro/h8dme/mptable.c | 2 +-
src/mainboard/supermicro/h8dmr/mptable.c | 2 +-
src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +-
src/mainboard/supermicro/h8qgi/mptable.c | 10 +-
src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +-
src/mainboard/supermicro/h8scm/mptable.c | 12 +-
src/mainboard/supermicro/h8scm_fam10/mptable.c | 14 +-
src/mainboard/supermicro/x7db8/romstage.c | 14 +-
src/mainboard/technexion/tim5690/mptable.c | 3 +-
src/mainboard/technexion/tim8690/mptable.c | 3 +-
src/mainboard/thomson/ip1000/mainboard.c | 6 +-
src/mainboard/tyan/s2735/mptable.c | 6 +-
src/mainboard/tyan/s2850/mptable.c | 2 +-
src/mainboard/tyan/s2875/mptable.c | 2 +-
src/mainboard/tyan/s2880/mptable.c | 6 +-
src/mainboard/tyan/s2881/mptable.c | 6 +-
src/mainboard/tyan/s2882/mptable.c | 6 +-
src/mainboard/tyan/s2885/mptable.c | 6 +-
src/mainboard/tyan/s2891/mptable.c | 6 +-
src/mainboard/tyan/s2892/mptable.c | 6 +-
src/mainboard/tyan/s2895/mptable.c | 8 +-
src/mainboard/tyan/s2912/mptable.c | 2 +-
src/mainboard/tyan/s2912_fam10/mptable.c | 2 +-
src/mainboard/tyan/s4880/mptable.c | 6 +-
src/mainboard/tyan/s4882/mptable.c | 6 +-
src/mainboard/tyan/s8226/mptable.c | 10 +-
src/mainboard/via/epia-m850/devicetree.cb | 4 +-
src/mainboard/via/pc2500e/mptable.c | 2 +-
src/mainboard/via/vt8454c/mptable.c | 2 +-
src/mainboard/winent/mb6047/mptable.c | 2 +-
src/northbridge/amd/cimx/rd890/late.c | 4 +-
src/northbridge/intel/e7501/raminit.c | 54 +-
src/northbridge/intel/e7505/raminit.c | 72 +-
src/northbridge/intel/fsp_sandybridge/acpi.c | 2 +-
src/northbridge/intel/gm45/gma.c | 329 +++---
src/northbridge/intel/gm45/raminit.c | 12 +-
.../intel/gm45/raminit_read_write_training.c | 12 +-
.../gm45/raminit_receive_enable_calibration.c | 2 +-
src/northbridge/intel/haswell/acpi.c | 2 +-
src/northbridge/intel/haswell/gma.c | 4 +-
src/northbridge/intel/haswell/minihd.c | 7 +-
src/northbridge/intel/i3100/raminit.c | 122 ++-
src/northbridge/intel/i3100/raminit_ep80579.c | 94 +-
src/northbridge/intel/i440bx/raminit.c | 5 +-
src/northbridge/intel/i5000/raminit.c | 8 +-
src/northbridge/intel/i82810/raminit.c | 10 +-
src/northbridge/intel/i82830/raminit.c | 8 +-
src/northbridge/intel/i82830/smihandler.c | 6 +-
src/northbridge/intel/i855/raminit.c | 2 +-
src/northbridge/intel/i945/raminit.c | 2 +-
src/northbridge/intel/i945/rcven.c | 4 +-
src/northbridge/intel/nehalem/acpi.c | 2 +-
src/northbridge/intel/nehalem/gma.c | 392 ++++---
src/northbridge/intel/nehalem/raminit.c | 160 +--
src/northbridge/intel/sandybridge/acpi.c | 2 +-
src/northbridge/intel/sandybridge/gma.c | 8 +-
src/northbridge/intel/sandybridge/gma.h | 2 +-
.../intel/sandybridge/gma_ivybridge_lvds.c | 377 +++----
.../intel/sandybridge/gma_sandybridge_lvds.c | 406 ++++---
src/northbridge/intel/sandybridge/raminit_native.c | 1148 +++++++++++---------
src/northbridge/via/cn700/raminit.c | 26 +-
src/northbridge/via/cx700/lpc.c | 2 +-
src/northbridge/via/cx700/raminit.c | 152 +--
src/northbridge/via/vx900/lpc.c | 6 +-
src/northbridge/via/vx900/traf_ctrl.c | 12 +-
src/soc/intel/baytrail/acpi.c | 2 +-
src/soc/intel/baytrail/baytrail/gpio.h | 16 +-
src/soc/intel/baytrail/gfx.c | 4 +-
src/soc/intel/baytrail/gpio.c | 16 +-
src/soc/intel/baytrail/hda.c | 6 +-
src/soc/intel/baytrail/iosf.c | 4 +-
src/soc/intel/baytrail/lpe.c | 12 +-
src/soc/intel/baytrail/pmutil.c | 8 +-
src/soc/intel/baytrail/romstage/romstage.c | 10 +-
src/soc/intel/baytrail/sata.c | 2 +-
src/soc/intel/baytrail/smm.c | 2 +-
src/soc/intel/baytrail/southcluster.c | 30 +-
src/soc/intel/baytrail/spi.c | 18 +-
src/soc/intel/broadwell/lpc.c | 6 +-
src/soc/intel/common/hda_verb.c | 12 +-
src/soc/intel/common/hda_verb.h | 6 +-
src/soc/intel/fsp_baytrail/acpi.c | 2 +-
src/soc/intel/fsp_baytrail/baytrail/gpio.h | 16 +-
src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 2 +-
src/soc/intel/fsp_baytrail/gpio.c | 30 +-
src/soc/intel/fsp_baytrail/iosf.c | 4 +-
src/soc/intel/fsp_baytrail/pmutil.c | 8 +-
src/soc/intel/fsp_baytrail/romstage/romstage.c | 16 +-
src/soc/intel/fsp_baytrail/smm.c | 2 +-
src/soc/intel/fsp_baytrail/southcluster.c | 34 +-
src/soc/intel/fsp_baytrail/spi.c | 18 +-
src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 6 +-
src/southbridge/amd/agesa/hudson/hudson.c | 8 +-
src/southbridge/amd/agesa/hudson/imc.c | 20 +-
src/southbridge/amd/agesa/hudson/sm.c | 2 +-
src/southbridge/amd/agesa/hudson/smi.h | 8 +-
src/southbridge/amd/agesa/hudson/spi.c | 4 +-
src/southbridge/amd/amd8111/lpc.c | 2 +-
src/southbridge/amd/amd8111/nic.c | 6 +-
src/southbridge/amd/cimx/sb700/late.c | 6 +-
src/southbridge/amd/cimx/sb800/late.c | 8 +-
src/southbridge/amd/cimx/sb800/spi.c | 20 +-
src/southbridge/amd/cs5536/cs5536.c | 12 +-
src/southbridge/amd/pi/avalon/hudson.c | 8 +-
src/southbridge/amd/pi/avalon/sm.c | 2 +-
src/southbridge/amd/pi/avalon/smi.h | 8 +-
src/southbridge/amd/sb600/hda.c | 18 +-
src/southbridge/amd/sb600/sata.c | 6 +-
src/southbridge/amd/sb600/sm.c | 2 +-
src/southbridge/amd/sb600/usb.c | 6 +-
src/southbridge/amd/sb700/hda.c | 18 +-
src/southbridge/amd/sb700/sata.c | 6 +-
src/southbridge/amd/sb700/sm.c | 4 +-
src/southbridge/amd/sb700/usb.c | 6 +-
src/southbridge/amd/sb800/hda.c | 18 +-
src/southbridge/amd/sb800/sata.c | 6 +-
src/southbridge/amd/sb800/sm.c | 2 +-
src/southbridge/amd/sb800/usb.c | 6 +-
src/southbridge/amd/sr5650/ht.c | 2 +-
src/southbridge/broadcom/bcm5785/sata.c | 19 +-
src/southbridge/intel/bd82x6x/azalia.c | 41 +-
src/southbridge/intel/bd82x6x/early_pch_native.c | 452 ++++----
src/southbridge/intel/bd82x6x/early_thermal.c | 25 +-
src/southbridge/intel/bd82x6x/early_usb_native.c | 19 +-
src/southbridge/intel/bd82x6x/lpc.c | 8 +-
src/southbridge/intel/bd82x6x/me.c | 18 +-
src/southbridge/intel/bd82x6x/me_8.x.c | 18 +-
src/southbridge/intel/bd82x6x/sata.c | 24 +-
src/southbridge/intel/bd82x6x/usb_ehci.c | 5 +-
src/southbridge/intel/common/spi.c | 30 +-
src/southbridge/intel/esb6300/lpc.c | 2 +-
src/southbridge/intel/esb6300/pic.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/azalia.c | 41 +-
src/southbridge/intel/fsp_bd82x6x/me.c | 18 +-
src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 18 +-
src/southbridge/intel/fsp_bd82x6x/sata.c | 10 +-
src/southbridge/intel/fsp_rangeley/early_init.c | 9 +-
src/southbridge/intel/fsp_rangeley/gpio.c | 26 +-
src/southbridge/intel/fsp_rangeley/lpc.c | 24 +-
src/southbridge/intel/fsp_rangeley/romstage.c | 2 +-
src/southbridge/intel/fsp_rangeley/sata.c | 10 +-
src/southbridge/intel/fsp_rangeley/spi.c | 22 +-
src/southbridge/intel/i3100/lpc.c | 2 +-
src/southbridge/intel/i82801ax/lpc.c | 4 +-
src/southbridge/intel/i82801bx/lpc.c | 4 +-
src/southbridge/intel/i82801cx/lpc.c | 4 +-
src/southbridge/intel/i82801dx/lpc.c | 4 +-
src/southbridge/intel/i82801ex/lpc.c | 2 +-
src/southbridge/intel/i82801gx/azalia.c | 38 +-
src/southbridge/intel/i82801gx/lpc.c | 4 +-
src/southbridge/intel/i82801gx/usb_ehci.c | 8 +-
src/southbridge/intel/i82801ix/hdaudio.c | 40 +-
src/southbridge/intel/i82801ix/lpc.c | 2 +-
src/southbridge/intel/i82801ix/sata.c | 24 +-
src/southbridge/intel/i82801ix/thermal.c | 16 +-
src/southbridge/intel/ibexpeak/azalia.c | 41 +-
src/southbridge/intel/ibexpeak/early_thermal.c | 7 +-
src/southbridge/intel/ibexpeak/lpc.c | 10 +-
src/southbridge/intel/ibexpeak/me.c | 18 +-
src/southbridge/intel/ibexpeak/sata.c | 18 +-
src/southbridge/intel/ibexpeak/thermal.c | 17 +-
src/southbridge/intel/ibexpeak/usb_ehci.c | 5 +-
src/southbridge/intel/lynxpoint/azalia.c | 10 +-
src/southbridge/intel/lynxpoint/hda_verb.c | 12 +-
src/southbridge/intel/lynxpoint/hda_verb.h | 6 +-
src/southbridge/intel/lynxpoint/lpc.c | 8 +-
src/southbridge/intel/lynxpoint/me_9.x.c | 18 +-
src/southbridge/intel/lynxpoint/sata.c | 16 +-
src/southbridge/intel/lynxpoint/serialio.c | 32 +-
src/southbridge/intel/lynxpoint/usb_ehci.c | 20 +-
src/southbridge/intel/lynxpoint/usb_xhci.c | 44 +-
src/southbridge/intel/sch/audio.c | 54 +-
src/southbridge/nvidia/ck804/lpc.c | 2 +-
src/southbridge/nvidia/ck804/nic.c | 16 +-
src/southbridge/nvidia/mcp55/azalia.c | 38 +-
src/southbridge/nvidia/mcp55/lpc.c | 4 +-
src/southbridge/nvidia/mcp55/nic.c | 38 +-
src/southbridge/sis/sis966/aza.c | 44 +-
src/southbridge/sis/sis966/lpc.c | 4 +-
src/southbridge/sis/sis966/nic.c | 30 +-
src/southbridge/sis/sis966/usb2.c | 8 +-
src/southbridge/via/vt8237r/lpc.c | 2 +-
289 files changed, 3221 insertions(+), 3145 deletions(-)
diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index 8049be4..299a383 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -222,7 +222,7 @@ static void smp_write_bus(struct mp_config_table *mc,
* APIC Flags:EN, Address
*/
void smp_write_ioapic(struct mp_config_table *mc,
- u8 id, u8 ver, u32 apicaddr)
+ u8 id, u8 ver, void *apicaddr)
{
struct mpc_config_ioapic *mpc;
mpc = smp_next_mpc_entry(mc);
diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h
index 1de6097..9ecb822 100644
--- a/src/arch/x86/include/arch/ebda.h
+++ b/src/arch/x86/include/arch/ebda.h
@@ -23,9 +23,9 @@
#define __ARCH_EBDA_H
#define X86_BDA_SIZE 0x200
-#define X86_BDA_BASE 0x400
-#define X86_EBDA_SEGMENT 0x40e
-#define X86_EBDA_LOWMEM 0x413
+#define X86_BDA_BASE (void *)0x400
+#define X86_EBDA_SEGMENT (void *)0x40e
+#define X86_EBDA_LOWMEM (void *)0x413
#define DEFAULT_EBDA_LOWMEM (1024 << 10)
#define DEFAULT_EBDA_SEGMENT 0xF600
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index d5cdf35..9987578 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -142,32 +142,32 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
);
}
-static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
+static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
{
return *((volatile uint8_t *)(addr));
}
-static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
+static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
{
return *((volatile uint16_t *)(addr));
}
-static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
+static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
{
return *((volatile uint32_t *)(addr));
}
-static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
+static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
{
*((volatile uint8_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
+static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
{
*((volatile uint16_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
+static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
{
*((volatile uint32_t *)(addr)) = value;
}
diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h
index bb0a35e..9542f14 100644
--- a/src/arch/x86/include/arch/ioapic.h
+++ b/src/arch/x86/include/arch/ioapic.h
@@ -42,11 +42,11 @@
#define SMI (2 << 8)
#define INT (1 << 8)
-u32 io_apic_read(u32 ioapic_base, u32 reg);
-void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
-void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
-void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
-void clear_ioapic(u32 ioapic_base);
+u32 io_apic_read(void *ioapic_base, u32 reg);
+void io_apic_write(void *ioapic_base, u32 reg, u32 value);
+void set_ioapic_id(void *ioapic_base, u8 ioapic_id);
+void setup_ioapic(void *ioapic_base, u8 ioapic_id);
+void clear_ioapic(void *ioapic_base);
#endif
#endif
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h
index b62a2166b..7966903 100644
--- a/src/arch/x86/include/arch/pci_mmio_cfg.h
+++ b/src/arch/x86/include/arch/pci_mmio_cfg.h
@@ -28,48 +28,48 @@
static inline __attribute__ ((always_inline))
u8 pcie_read_config8(pci_devfn_t dev, unsigned int where)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
return read8(addr);
}
static inline __attribute__ ((always_inline))
u16 pcie_read_config16(pci_devfn_t dev, unsigned int where)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
return read16(addr);
}
static inline __attribute__ ((always_inline))
u32 pcie_read_config32(pci_devfn_t dev, unsigned int where)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
return read32(addr);
}
static inline __attribute__ ((always_inline))
void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
write8(addr, value);
}
static inline __attribute__ ((always_inline))
void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
write16(addr, value);
}
static inline __attribute__ ((always_inline))
void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
+ void *addr;
+ addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
write32(addr, value);
}
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 8e74e46..481d8a5 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -123,7 +123,7 @@ struct mpc_config_ioapic
u8 mpc_apicver;
u8 mpc_flags;
#define MPC_APIC_USABLE 0x01
- u32 mpc_apicaddr;
+ void *mpc_apicaddr;
} __attribute__((packed));
struct mpc_config_intsrc
@@ -260,7 +260,7 @@ void smp_write_processor(struct mp_config_table *mc,
u32 featureflag);
void smp_write_processors(struct mp_config_table *mc);
void smp_write_ioapic(struct mp_config_table *mc,
- u8 id, u8 ver, u32 apicaddr);
+ u8 id, u8 ver, void *apicaddr);
void smp_write_intsrc(struct mp_config_table *mc,
u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq,
u8 dstapic, u8 dstirq);
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
index 7efc662..c6fa4a6 100644
--- a/src/arch/x86/lib/ebda.c
+++ b/src/arch/x86/lib/ebda.c
@@ -42,7 +42,7 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
/* Set up EBDA */
memset((void *)(ebda_segment << 4), 0, ebda_size);
- write16((ebda_segment << 4), (ebda_size >> 10));
+ write16((void*)(ebda_segment << 4), (ebda_size >> 10));
}
void setup_default_ebda(void)
diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index 7fb25ba..e752ccd 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -22,19 +22,19 @@
#include <console/console.h>
#include <cpu/x86/lapic.h>
-u32 io_apic_read(u32 ioapic_base, u32 reg)
+u32 io_apic_read(void *ioapic_base, u32 reg)
{
write32(ioapic_base, reg);
return read32(ioapic_base + 0x10);
}
-void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
+void io_apic_write(void *ioapic_base, u32 reg, u32 value)
{
write32(ioapic_base, reg);
write32(ioapic_base + 0x10, value);
}
-static int ioapic_interrupt_count(int ioapic_base)
+static int ioapic_interrupt_count(void *ioapic_base)
{
/* Read the available number of interrupts. */
int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
@@ -48,12 +48,12 @@ static int ioapic_interrupt_count(int ioapic_base)
return ioapic_interrupts;
}
-void clear_ioapic(u32 ioapic_base)
+void clear_ioapic(void *ioapic_base)
{
u32 low, high;
u32 i, ioapic_interrupts;
- printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
+ printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%p\n", ioapic_base);
ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
@@ -74,12 +74,12 @@ void clear_ioapic(u32 ioapic_base)
}
}
-void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
+void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
{
u32 bsp_lapicid = lapicid();
int i;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
+ printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
bsp_lapicid);
@@ -99,7 +99,7 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
}
-static void load_vectors(u32 ioapic_base)
+static void load_vectors(void *ioapic_base)
{
u32 bsp_lapicid = lapicid();
u32 low, high;
@@ -146,7 +146,7 @@ static void load_vectors(u32 ioapic_base)
}
}
-void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
+void setup_ioapic(void *ioapic_base, u8 ioapic_id)
{
set_ioapic_id(ioapic_base, ioapic_id);
load_vectors(ioapic_base);
diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c
index 4eaf297..4219a1a 100644
--- a/src/arch/x86/lib/pci_ops_mmconf.c
+++ b/src/arch/x86/lib/pci_ops_mmconf.c
@@ -18,37 +18,37 @@
static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read8(PCI_MMIO_ADDR(bus, devfn, where)));
+ return (read8((void *)(PCI_MMIO_ADDR(bus, devfn, where))));
}
static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read16(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
+ return (read16((void *)(PCI_MMIO_ADDR(bus, devfn, where) & ~1)));
}
static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read32(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
+ return (read32((void*)(PCI_MMIO_ADDR(bus, devfn, where) & ~3)));
}
static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
int where, uint8_t value)
{
- write8(PCI_MMIO_ADDR(bus, devfn, where), value);
+ write8((void *)(PCI_MMIO_ADDR(bus, devfn, where)), value);
}
static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
int where, uint16_t value)
{
- write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value);
+ write16((void *)(PCI_MMIO_ADDR(bus, devfn, where) & ~1), value);
}
static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
int where, uint32_t value)
{
- write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value);
+ write32((void *)(PCI_MMIO_ADDR(bus, devfn, where) & ~3), value);
}
const struct pci_bus_operations pci_ops_mmconf = {
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index b250f3d..9ff3a9e 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -59,19 +59,19 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u32 reg32;
int count;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* clear STATESTS bits (BAR + 0xE)[2:0] */
- reg32 = read32(base + 0x0E);
+ reg32 = read32(base + (0x0E / sizeof(u32)));
reg32 |= 7;
- write32(base + 0x0E, reg32);
+ write32(base + (0x0E / sizeof(u32)), reg32);
/* Wait for readback of register to
* match what was just written to it
@@ -80,22 +80,22 @@ static int codec_detect(u32 base)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(base + 0x0E);
+ reg32 = read32(base + (0x0E / sizeof(u32)));
} while ((reg32 != 0) && --count);
/* Timeout occured */
if (!count)
goto no_codec;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 0) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 0) == -1)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
- reg32 = read32(base + 0xe);
+ reg32 = read32(base + (0xe / sizeof(u32)));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -105,7 +105,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
return 0;
}
@@ -136,7 +136,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -144,7 +144,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -159,20 +159,21 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 25;
- write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY);
+ write32(base + (HDA_ICII_REG / sizeof(u32)),
+ HDA_ICII_VALID | HDA_ICII_BUSY);
while (timeout--) {
udelay(1);
}
timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -182,7 +183,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -196,12 +197,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
@@ -218,7 +219,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -226,7 +227,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
@@ -238,7 +239,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
void azalia_audio_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
@@ -248,8 +249,8 @@ void azalia_audio_init(struct device *dev)
// NOTE this will break as soon as the azalia_audio get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32) res->base;
- printk(BIOS_DEBUG, "azalia_audio: base = %08x\n", (u32) base);
+ base = (u32 *)(uintptr_t) res->base;
+ printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index fc3c40c..c3f87a8 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -80,7 +80,7 @@ static void setup_rombios(void)
memcpy((void *)0xfffd9, &ident, 7);
/* system model: IBM-AT */
- write8(0xffffe, 0xfc);
+ write8((void *)0xffffe, 0xfc);
}
static int (*intXX_handler[256])(void) = { NULL };
diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h
index 94f31fe..8e9a144 100644
--- a/src/drivers/ati/ragexl/atyfb.h
+++ b/src/drivers/ati/ragexl/atyfb.h
@@ -211,7 +211,7 @@ static inline u32 aty_ld_le32(int regindex,
#ifdef ATARI
return in_le32((volatile u32 *)(info->ati_regbase+regindex));
#else
- return read32 (info->ati_regbase + regindex);
+ return read32 ((u32 *)(info->ati_regbase + regindex));
#endif
}
@@ -225,7 +225,7 @@ static inline void aty_st_le32(int regindex, u32 val,
#ifdef ATARI
out_le32 (info->ati_regbase+regindex, val);
#else
- write32 (info->ati_regbase + regindex, val);
+ write32 ((u32 *)(info->ati_regbase + regindex), val);
#endif
}
@@ -239,7 +239,7 @@ static inline u16 aty_ld_le16(int regindex,
#if defined(__mc68000__)
return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex)));
#else
- return read16 (info->ati_regbase + regindex);
+ return read16 ((u16 *)(info->ati_regbase + regindex));
#endif
}
@@ -253,7 +253,7 @@ static inline void aty_st_le16(int regindex, u16 val,
#if defined(__mc68000__)
*((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val);
#else
- write16 (info->ati_regbase + regindex, val);
+ write16 ((u16 *)(info->ati_regbase + regindex), val);
#endif
}
@@ -267,7 +267,7 @@ static inline u8 aty_ld_8(int regindex,
#ifdef ATARI
return in_8 (info->ati_regbase + regindex);
#else
- return read8 (info->ati_regbase + regindex);
+ return read8 ((u8 *)(info->ati_regbase + regindex));
#endif
}
@@ -281,7 +281,7 @@ static inline void aty_st_8(int regindex, u8 val,
#ifdef ATARI
out_8 (info->ati_regbase + regindex, val);
#else
- write8 (info->ati_regbase + regindex, val);
+ write8 ((u8 *)(info->ati_regbase + regindex), val);
#endif
}
diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h
index 665e926..e74c60c 100644
--- a/src/drivers/generic/ioapic/chip.h
+++ b/src/drivers/generic/ioapic/chip.h
@@ -27,7 +27,7 @@ typedef struct drivers_generic_ioapic_config {
u8 irq_on_fsb;
u8 enable_virtual_wire;
u8 have_isa_interrupts;
- u32 base;
+ void *base;
} ioapic_config_t;
#endif
diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c
index 463474a..44f1b02 100644
--- a/src/drivers/generic/ioapic/ioapic.c
+++ b/src/drivers/generic/ioapic/ioapic.c
@@ -18,7 +18,7 @@ static void ioapic_init(struct device *dev)
u32 bsp_lapicid = lapicid();
u32 low, high;
u32 i, ioapic_interrupts;
- u32 ioapic_base;
+ void *ioapic_base;
u8 ioapic_id;
if (!dev->enabled || !config)
@@ -27,7 +27,7 @@ static void ioapic_init(struct device *dev)
ioapic_base = config->base;
ioapic_id = config->apicid;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
+ printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
ioapic_base);
printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
bsp_lapicid);
@@ -93,7 +93,7 @@ static void ioapic_read_resources(struct device *dev)
struct resource *res;
res = new_resource(dev, 0);
- res->base = config->base;
+ res->base = (resource_t)(uintptr_t)config->base;
res->size = 0x1000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c
index 91ad742..8c309e6 100644
--- a/src/drivers/intel/gma/edid.c
+++ b/src/drivers/intel/gma/edid.c
@@ -26,18 +26,18 @@
#include "i915_reg.h"
#include "edid.h"
-static void wait_rdy(u32 mmio)
+static void wait_rdy(u32 *mmio)
{
unsigned try = 100;
while (try--) {
- if (read32(mmio + 8) & (1 << 11))
+ if (read32(mmio + 2) & (1 << 11))
return;
udelay(10);
}
}
-void intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
+void intel_gmbus_read_edid(u32 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
{
int i;
@@ -46,30 +46,30 @@ void intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
wait_rdy(mmio);
/* 100 KHz, hold 0ns, */
- write32(mmio + 4 * 0, bus);
+ write32(mmio + 0, bus);
wait_rdy(mmio);
/* Ensure index bits are disabled. */
- write32(mmio + 4 * 5, 0);
- write32(mmio + 4 * 1, 0x46000000 | (slave << 1));
+ write32(mmio + 5, 0);
+ write32(mmio + 1, 0x46000000 | (slave << 1));
wait_rdy(mmio);
/* Ensure index bits are disabled. */
- write32(mmio + 4 * 5, 0);
- write32(mmio + 4 * 1, 0x4a000001 | (slave << 1)
+ write32(mmio + 5, 0);
+ write32(mmio + 1, 0x4a000001 | (slave << 1)
| (edid_size << 16));
for (i = 0; i < edid_size / 4; i++) {
u32 reg32;
wait_rdy(mmio);
- reg32 = read32(mmio + 4 * 3);
+ reg32 = read32(mmio + 3);
edid[4 * i] = reg32 & 0xff;
edid[4 * i + 1] = (reg32 >> 8) & 0xff;
edid[4 * i + 2] = (reg32 >> 16) & 0xff;
edid[4 * i + 3] = (reg32 >> 24) & 0xff;
}
wait_rdy(mmio);
- write32(mmio + 4 * 1, 0x4a800000 | (slave << 1));
+ write32(mmio + 1, 0x4a800000 | (slave << 1));
wait_rdy(mmio);
- write32(mmio + 4 * 0, 0x48000000);
- write32(mmio + 4 * 2, 0x00008000);
+ write32(mmio + 0, 0x48000000);
+ write32(mmio + 2, 0x00008000);
printk (BIOS_SPEW, "EDID:\n");
for (i = 0; i < 128; i++) {
diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h
index cb54b46..c6466fa 100644
--- a/src/drivers/intel/gma/edid.h
+++ b/src/drivers/intel/gma/edid.h
@@ -1 +1 @@
-void intel_gmbus_read_edid(u32 gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);
+void intel_gmbus_read_edid(u32 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index 83c23a3..379a1bd 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -78,7 +78,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
int loop = 0;
do {
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
/* Stop when the transaction is finished */
if (ctrl & DBGP_DONE)
break;
@@ -92,7 +92,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
/* Now that we have observed the completed transaction,
* clear the done bit.
*/
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
+ write32(&ehci_debug->control, ctrl | DBGP_DONE);
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
}
@@ -122,10 +122,10 @@ host_retry:
if (loop == 1 || host_retries > 1)
dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
loop, host_retries, ctrl | DBGP_GO);
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
+ write32(&ehci_debug->control, ctrl | DBGP_GO);
ret = dbgp_wait_until_complete(ehci_debug);
- rd_ctrl = read32((unsigned long)&ehci_debug->control);
- rd_pids = read32((unsigned long)&ehci_debug->pids);
+ rd_ctrl = read32(&ehci_debug->control);
+ rd_pids = read32(&ehci_debug->pids);
if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
ctrl_prev = rd_ctrl;
@@ -184,8 +184,8 @@ static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int
lo |= bytes[i] << (8*i);
for (; i < 8 && i < size; i++)
hi |= bytes[i] << (8*(i - 4));
- write32((unsigned long)&ehci_debug->data03, lo);
- write32((unsigned long)&ehci_debug->data47, hi);
+ write32(&ehci_debug->data03, lo);
+ write32(&ehci_debug->data47, hi);
}
static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
@@ -194,8 +194,8 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
u32 lo, hi;
int i;
- lo = read32((unsigned long)&ehci_debug->data03);
- hi = read32((unsigned long)&ehci_debug->data47);
+ lo = read32(&ehci_debug->data03);
+ hi = read32(&ehci_debug->data47);
for (i = 0; i < 4 && i < size; i++)
bytes[i] = (lo >> (8*i)) & 0xff;
for (; i < 8 && i < size; i++)
@@ -205,9 +205,9 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
#if CONFIG_DEBUG_USBDEBUG
static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
{
- u32 ctrl = read32((unsigned long)&ehci_debug->control);
- u32 lo = read32((unsigned long)&ehci_debug->data03);
- u32 hi = read32((unsigned long)&ehci_debug->data47);
+ u32 ctrl = read32(&ehci_debug->control);
+ u32 lo = read32(&ehci_debug->data03);
+ u32 hi = read32(&ehci_debug->data47);
int len = DBGP_LEN(ctrl);
if (len) {
int i;
@@ -233,13 +233,13 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *p
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl |= DBGP_OUT;
dbgp_set_data(ehci_debug, bytes, size);
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->address, addr);
+ write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
@@ -264,12 +264,12 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl &= ~DBGP_OUT;
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->address, addr);
+ write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret < 0)
return ret;
@@ -324,14 +324,14 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
ctrl |= DBGP_OUT;
/* Setup stage */
dbgp_set_data(ehci_debug, &req, sizeof(req));
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->address, addr);
+ write32(&ehci_debug->pids, pids);
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
if (ret < 0)
return ret;
@@ -344,7 +344,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
/* Status stage in opposite direction */
pipe->pid = USB_PID_DATA1;
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl = DBGP_LEN_UPDATE(ctrl, 0);
if (read) {
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
@@ -354,7 +354,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
ctrl &= ~DBGP_OUT;
}
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(&ehci_debug->pids, pids);
ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret2 < 0)
return ret2;
@@ -368,21 +368,21 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
int loop;
/* Reset the usb debug port */
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc = read32(&ehci_regs->port_status[port - 1]);
portsc &= ~PORT_PE;
portsc |= PORT_RESET;
- write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
+ write32(&ehci_regs->port_status[port - 1], portsc);
dbgp_mdelay(HUB_ROOT_RESET_TIME);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- write32((unsigned long)&ehci_regs->port_status[port - 1],
+ portsc = read32(&ehci_regs->port_status[port - 1]);
+ write32(&ehci_regs->port_status[port - 1],
portsc & ~(PORT_RWC_BITS | PORT_RESET));
loop = 100;
do {
dbgp_mdelay(1);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc = read32(&ehci_regs->port_status[port - 1]);
} while ((portsc & PORT_RESET) && (--loop > 0));
/* Device went away? */
@@ -407,7 +407,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
for (reps = 0; reps < 3; reps++) {
dbgp_mdelay(100);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
if (status & STS_PCD) {
ret = ehci_reset_port(ehci_regs, port);
if (ret == 0)
@@ -440,7 +440,7 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
ehci_caps = (struct ehci_caps *)ehci_bar;
ehci_regs = (struct ehci_regs *)(ehci_bar +
- HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
+ HC_LENGTH(read32(&ehci_caps->hc_capbase)));
struct ehci_dbg_port *ehci_debug = info->ehci_debug;
@@ -453,7 +453,7 @@ try_next_time:
port_map_tried = 0;
try_next_port:
- hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
+ hcs_params = read32(&ehci_caps->hcs_params);
debug_port = HCS_DEBUG_PORT(hcs_params);
n_ports = HCS_N_PORTS(hcs_params);
@@ -461,7 +461,7 @@ try_next_port:
dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
for (i = 1; i <= n_ports; i++) {
- portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
+ portsc = read32(&ehci_regs->port_status[i-1]);
dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
}
@@ -474,15 +474,15 @@ try_next_port:
}
/* Wait until the controller is halted */
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
if (!(status & STS_HALT)) {
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
cmd &= ~CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(&ehci_regs->command, cmd);
loop = 100;
do {
dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
} while (!(status & STS_HALT) && (--loop > 0));
if (status & STS_HALT)
dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
@@ -492,12 +492,12 @@ try_next_port:
loop = 100;
/* Reset the EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
cmd |= CMD_RESET;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(&ehci_regs->command, cmd);
do {
dbgp_mdelay(10);
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
} while ((cmd & CMD_RESET) && (--loop > 0));
if(!loop) {
@@ -509,25 +509,25 @@ try_next_port:
}
/* Claim ownership, but do not enable yet */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_OWNER;
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
- write32((unsigned long)&ehci_debug->control, ctrl);
+ write32(&ehci_debug->control, ctrl);
/* Start EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32(&ehci_regs->command);
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
cmd |= CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(&ehci_regs->command, cmd);
/* Ensure everything is routed to the EHCI */
- write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
+ write32(&ehci_regs->configured_flag, FLAG_CF);
/* Wait until the controller is no longer halted */
loop = 10;
do {
dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32(&ehci_regs->status);
} while ((status & STS_HALT) && (--loop > 0));
if(!loop) {
@@ -546,13 +546,13 @@ try_next_port:
/* Enable the debug port */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_CLAIM;
- write32((unsigned long)&ehci_debug->control, ctrl);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ write32(&ehci_debug->control, ctrl);
+ ctrl = read32(&ehci_debug->control);
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
- write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
+ write32(&ehci_debug->control, ctrl & ~DBGP_CLAIM);
ret = -4;
goto err;
}
@@ -560,9 +560,9 @@ try_next_port:
#if 0
/* Completely transfer the debug device to the debug controller */
- portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]);
+ portsc = read32(&ehci_regs->port_status[debug_port - 1]);
portsc &= ~PORT_PE;
- write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc);
+ write32(&ehci_regs->port_status[debug_port - 1], portsc);
#endif
dbgp_mdelay(100);
@@ -577,9 +577,9 @@ try_next_port:
return 0;
err:
/* Things didn't work so remove my claim */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32(&ehci_debug->control);
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
- write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
+ write32(&ehci_debug->control, ctrl);
//return ret;
next_debug_port:
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index 8fe78b1..c8dca79 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -109,7 +109,7 @@ unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
#else
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
- unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
+ u32 *base = (u32 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
#endif
- return base + HC_LENGTH(read32(base));
+ return base + HC_LENGTH(read32((u32 *)base));
}
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
index 647723b..2fd943e 100644
--- a/src/lib/reg_script.c
+++ b/src/lib/reg_script.c
@@ -155,11 +155,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
switch (step->size) {
case REG_SCRIPT_SIZE_8:
- return read8(step->reg);
+ return read8((u8 *)step->reg);
case REG_SCRIPT_SIZE_16:
- return read16(step->reg);
+ return read16((u16 *)step->reg);
case REG_SCRIPT_SIZE_32:
- return read32(step->reg);
+ return read32((u32 *)step->reg);
}
return 0;
}
@@ -170,13 +170,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx)
switch (step->size) {
case REG_SCRIPT_SIZE_8:
- write8(step->reg, step->value);
+ write8((u8 *)step->reg, step->value);
break;
case REG_SCRIPT_SIZE_16:
- write16(step->reg, step->value);
+ write16((u16 *)step->reg, step->value);
break;
case REG_SCRIPT_SIZE_32:
- write32(step->reg, step->value);
+ write32((u32 *)step->reg, step->value);
break;
}
}
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index b04cf41..9d4feb8 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index 1d0f5bf..ea3cc72 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
dword |= (pm_ioread(0x35) & 0xFF) << 8;
dword |= (pm_ioread(0x36) & 0xFF) << 16;
dword |= (pm_ioread(0x37) & 0xFF) << 24;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index 09d137a..511db71 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index 4e481f5..64de83b 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sb700;
u32 apicid_rd890;
device_t dev;
- u32 dword;
+ u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set sb700 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
/*
@@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
}
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 7686bd2..e928a85 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -52,8 +52,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
u8 byte;
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index bd31846..4c1946c 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -60,7 +60,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index db4a3ff..4d403f8 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
- smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index 80ba5b5..520c96e 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,9 +92,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
- smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 05da01a..a698a93 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 1227d89..dea85f4 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -41,8 +41,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index 09d137a..511db71 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 866875d..11d6092 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, (void*)IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
@@ -37,14 +37,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
+ (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
+ (void *)(uintptr_t)res->base);
}
}
@@ -60,14 +62,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, (void *)(uintptr_t)res->base);
}
}
break;
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 5335cb8..db541f4 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, (void *)IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
@@ -56,14 +56,16 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11,
+ (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11,
+ (void *)(uintptr_t)res->base);
}
}
@@ -79,14 +81,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, (void *)(uintptr_t)res->base);
}
}
break;
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index c2ec4a2..f1645ae 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
u8 byte;
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 8ddd1b6..15379fe 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 477d97a..5ab2afb 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -107,14 +107,14 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
- u32 dword;
+ u32 *dword;
u8 byte;
- ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
- dword &= 0xFFFFFFF0;
+ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+ dword = (u32 *)(((uintptr_t) dword) & 0xFFFFFFF0);
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
+ write32 (dword + 0x04, IO_APIC_ID << 24);
apicid_sb900 = IO_APIC_ID;
smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index c2ec4a2..9c4c08a 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -49,8 +49,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
u8 byte;
diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c
index cc97e52..0a2c4ff 100644
--- a/src/mainboard/apple/macbook21/mptable.c
+++ b/src/mainboard/apple/macbook21/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 6ee2704..62c0581 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -125,7 +125,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
/* 8131 apic 4 */
@@ -142,7 +142,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index 790d1da..fe2ebd8 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 14fa316..1c6b4bf 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
u8 byte;
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index d9ca7b7..41c20fa 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -93,9 +93,9 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
- smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index a954d92..2b31b60 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
- res->base);
+ (void *)(uintptr_t)res->base);
}
/* Initialize interrupt mapping. */
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 71e0e1e..687c709 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, (void *)IO_APIC_ADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 71e0e1e..687c709 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, (void *)IO_APIC_ADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/dsbf/devicetree.cb b/src/mainboard/asus/dsbf/devicetree.cb
index b4d1b63..0d3b6c8 100644
--- a/src/mainboard/asus/dsbf/devicetree.cb
+++ b/src/mainboard/asus/dsbf/devicetree.cb
@@ -91,13 +91,13 @@ chip northbridge/intel/i5000
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 8 on end
end
chip drivers/generic/ioapic
register "irq_on_fsb" = "1"
- register "base" = "0xfec80000"
+ register "base" = "(void *)0xfec80000"
device ioapic 9 on end
end
diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c
index fbd0848..5ef601f 100644
--- a/src/mainboard/asus/dsbf/romstage.c
+++ b/src/mainboard/asus/dsbf/romstage.c
@@ -52,22 +52,22 @@ static void early_config(void)
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
- gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+ gcs = read32((void *)(DEFAULT_RCBA + RCBA_GCS));
gcs |= (1 << 5); /* No reset */
- write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+ write32((void *)(DEFAULT_RCBA + RCBA_GCS), gcs);
/* Configure PCIe port B as 4x */
- rpc = read32(DEFAULT_RCBA + RCBA_RPC);
+ rpc = read32((void *)(DEFAULT_RCBA + RCBA_RPC));
rpc |= (3 << 0);
- write32(DEFAULT_RCBA + RCBA_RPC, rpc);
+ write32((void *)(DEFAULT_RCBA + RCBA_RPC), rpc);
/* Disable Modem, Audio, PCIe ports 2/3/4 */
- fd = read32(DEFAULT_RCBA + RCBA_FD);
+ fd = read32((void *)(DEFAULT_RCBA + RCBA_FD));
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
- write32(DEFAULT_RCBA + RCBA_FD, fd);
+ write32((void *)(DEFAULT_RCBA + RCBA_FD), fd);
/* Enable HPET */
- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+ write32((void *)(DEFAULT_RCBA + RCBA_HPTC), (1 << 7));
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index cc81819..8eb3374 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -75,8 +75,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
index 794194c..1f51606 100644
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ b/src/mainboard/asus/k8v-x/mptable.c
@@ -38,8 +38,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, (void *)IO_APIC_ADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 333ec49..af5f76b 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
pci_write_config32(dev, 0x7c, 0x00000000);
pci_write_config32(dev, 0x80, 0x11002009);
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index b74a1e3..b60c558 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, (void *)IO_APIC_ADDR);
+ smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, (void*)K8T890_APIC_BASE);
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
index 5259dec..4d6bb22 100644
--- a/src/mainboard/asus/m5a88-v/mptable.c
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index 51d00a3..3ce2727 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index ee3c20e..2354d72 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index 9c25da6..9803fab 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
- smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index d7ae6b7..f46e647 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -41,7 +41,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, apicid_bcm5785[i],
+ 0x11,
+ (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 9b59bb4..ab8327c 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index 0af6cf0..705481c 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_sis966, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_sis966, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 1536823..e22445a 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11, (void **)(uintptr_t)res->base);
}
/* set up the interrupt registers of mcp55 */
pci_write_config32(dev, 0x7c, 0xc643c643);
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/gigabyte/ma785gm/mptable.c
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index b98598a..87405e6 100644
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -50,8 +50,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
u8 byte;
diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c
index fbf6744..281cbfb 100644
--- a/src/mainboard/gizmosphere/gizmo2/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo2/mptable.c
@@ -40,8 +40,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index b9af38b..b0478e4 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, m->apicid_8111, 0x20, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -37,14 +37,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
+ smp_write_ioapic(mc, m->apicid_8131_1, 0x20, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
+ smp_write_ioapic(mc, m->apicid_8131_2, 0x20, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 6c71bad..6e307b3 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 86f2cc6..6582b9a 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -68,7 +68,7 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base);
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 65b1279..2c3f609 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 1baf728..f8a7601 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 6eb6390..6eb0a08 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -67,7 +67,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11, (void *)(uintptr_t)res->base);
}
}
/* 8131-2 apic #4 */
@@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index f271166..dbbc2b2 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -66,7 +66,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11, (void *)(uintptr_t)res->base);
}
}
/* 8131-2 apic #4 */
@@ -74,7 +74,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 11426c2..6786103 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index b0360bf..d06208d 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 809feec..6bd2f9c 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -121,7 +121,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
@@ -145,10 +145,10 @@ static void *smp_write_config_table(void *v)
/* PCIe Port B
*/
for(i = 0; i < 4; i++) {
- pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+ pin = (read32((void *)(rcba + RCBA_D28IP)) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(rcba + RCBA_D28IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
}
}
@@ -156,20 +156,20 @@ static void *smp_write_config_table(void *v)
/* USB 1.1 : device 29, function 0, 1
*/
for(i = 0; i < 2; i++) {
- pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+ pin = (read32((void *)(rcba + RCBA_D29IP)) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(rcba + RCBA_D29IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
}
}
/* USB 2.0 : device 29, function 7
*/
- pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
+ pin = (read32((void *)(rcba + RCBA_D29IP)) >> (7 * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(rcba + RCBA_D29IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
}
@@ -178,10 +178,10 @@ static void *smp_write_config_table(void *v)
Performance counters : device 31 function 4
*/
for(i = 2; i < 5; i++) {
- pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+ pin = (read32((void *)(rcba + RCBA_D31IP)) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(rcba + RCBA_D31IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
}
}
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index c03c7d7..5a5ecf2 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -84,22 +84,22 @@ static void early_config(void)
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
- gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+ gcs = read32((void *)(DEFAULT_RCBA + RCBA_GCS));
gcs |= (1 << 5); /* No reset */
- write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+ write32((void *)(DEFAULT_RCBA + RCBA_GCS), gcs);
/* Configure PCIe port B as 4x */
- rpc = read32(DEFAULT_RCBA + RCBA_RPC);
+ rpc = read32((void *)(DEFAULT_RCBA + RCBA_RPC));
rpc |= (3 << 0);
- write32(DEFAULT_RCBA + RCBA_RPC, rpc);
+ write32((void *)(DEFAULT_RCBA + RCBA_RPC), rpc);
/* Disable Modem, Audio, PCIe ports 2/3/4 */
- fd = read32(DEFAULT_RCBA + RCBA_FD);
+ fd = read32((void *)(DEFAULT_RCBA + RCBA_FD));
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
- write32(DEFAULT_RCBA + RCBA_FD, fd);
+ write32((void *)(DEFAULT_RCBA + RCBA_FD), fd);
/* Enable HPET */
- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+ write32((void *)(DEFAULT_RCBA + RCBA_HPTC), (1 << 7));
/* Improve interrupt routing
* D31:F2 SATA INTB# -> PIRQD
@@ -111,10 +111,10 @@ static void early_config(void)
* D28:F0 PCIe Port 1 INTA# -> PIRQE
*/
- write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
- write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
- write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
- write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
+ write16((void *)(DEFAULT_RCBA + RCBA_D31IR), 0x0230);
+ write16((void *)(DEFAULT_RCBA + RCBA_D30IR), 0x3210);
+ write16((void *)(DEFAULT_RCBA + RCBA_D29IR), 0x3237);
+ write16((void *)(DEFAULT_RCBA + RCBA_D28IR), 0x3214);
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
index b1fb995..d46abcd 100644
--- a/src/mainboard/intel/mohonpeak/romstage.c
+++ b/src/mainboard/intel/mohonpeak/romstage.c
@@ -40,16 +40,16 @@ static void interrupt_routing_config(void)
* PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
* This should match devicetree and the ACPI IRQ routing/
*/
- write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */
- write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */
- write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
- write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */
- write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */
- write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */
- write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */
- write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */
- write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */
- write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */
+ write32((void *)(ilb_base + ILB_ACTL), 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */
+ write16((void *)(ilb_base + ILB_IR01), 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */
+ write16((void *)(ilb_base + ILB_IR02), 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
+ write16((void *)(ilb_base + ILB_IR03), 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */
+ write16((void *)(ilb_base + ILB_IR04), 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */
+ write16((void *)(ilb_base + ILB_IR20), 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */
+ write16((void *)(ilb_base + ILB_IR22), 0x0007); /* IR16h IR(A) - PIRQ(H) */
+ write16((void *)(ilb_base + ILB_IR23), 0x0003); /* IR17h IR(A) - PIRQ(D) */
+ write16((void *)(ilb_base + ILB_IR24), 0x0003); /* IR18h IR(A) - PIRQ(D) */
+ write16((void *)(ilb_base + ILB_IR31), 0x0020); /* IR1Fh IR(B) - PIRQ(C) */
}
/**
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 4dd13f9..613c3c8 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 0x01, 0x20, (void *)IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index 9ad6ea6..ba95582 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 0x8, 0x20, (void *)IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 87de022..6f4cb64 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -34,7 +34,7 @@ void *smp_write_config_table(void *v)
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index ff6e582..839d8bd 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, (void *)IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
@@ -37,14 +37,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11, (void *)(uintptr_t)res->base);
}
}
@@ -60,14 +60,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, (void *)(uintptr_t)res->base);
}
}
break;
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index c7bb33d..99e59df 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11, (void *)(uintptr_t)res->base);
}
}
/* 8131 apic 4 */
@@ -71,7 +71,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index c7bb33d..99e59df 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11, (void *)(uintptr_t)res->base);
}
}
/* 8131 apic 4 */
@@ -71,7 +71,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 4390605..b3b78e6 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -44,8 +44,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index 7cabdf1..e28d057 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -60,7 +60,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb700,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 03f7370..7f66d84 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 8b86b02..45212be 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
index 65b1279..2c3f609 100644
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -76,8 +76,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index 744ef30..82929f7 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index edd3c64..cc27d25 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -77,7 +77,7 @@ chip northbridge/intel/gm45
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 2 on end
end
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index 8ade71b..c3fff64 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 078601e..13db614 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -61,7 +61,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
u8 byte;
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 078601e..13db614 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -48,8 +48,8 @@ static void *smp_write_config_table(void *v)
* have been written so they can be read to get the correct
* APIC ID and Version
*/
- u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+ u8 ioapic_id = (io_apic_read((void *)IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read((void *)IO_APIC_ADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -61,7 +61,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC_ADDR);
u8 byte;
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index b43a516..bde3a7d 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
- res->base);
+ (void *)(uintptr_t)res->base);
}
/* Initialize interrupt mapping */
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index ea003a8..9dfc5d2 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword);
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index b30ab73..e57b9dc 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -63,7 +63,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index 1764cf3..66f5285 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 09a25f2..41e4e35 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index 1d7c79e..8050449 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v)
/* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -64,7 +64,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, 0x03, 0x11, (void *)(uintptr_t)res->base);
}
}
/* 8131 apic 4 */
@@ -72,7 +72,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, 0x04, 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index e991efd..0258934 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
/* Initialize interrupt mapping*/
dword = pci_read_config32(dev, 0x74);
@@ -81,7 +81,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res)
- smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, (void *)(uintptr_t)res->base);
dword = 0x43c60000;
pci_write_config32(dev, 0x7c, dword);
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 9b59bb4..ab8327c 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 0x20, (void *)IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb
index deece86..2bd2358 100644
--- a/src/mainboard/roda/rk9/devicetree.cb
+++ b/src/mainboard/roda/rk9/devicetree.cb
@@ -66,7 +66,7 @@ chip northbridge/intel/gm45
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 2 on end
end
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 9b0fc40..0372614 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -112,7 +112,7 @@ chip northbridge/intel/sandybridge
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 4 on end
end
end
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index de5151d..606be27 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
struct resource *res;
res = find_resource(dev, 0x74);
- smp_write_ioapic(mc, apicid_sb600, 0x20, res->base);
+ smp_write_ioapic(mc, apicid_sb600, 0x20, (void *)(uintptr_t)res->base);
}
}
mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0);
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index 1ba1dcf..8e121d8 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11, (void *)(uintptr_t)res->base);
}
/* Initialize interrupt mapping*/
@@ -77,14 +77,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
@@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804b, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x0000d218;
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index 17067ed..1905e7e 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 11db23f..a331352 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 4e2d48c..f3c9e5e 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 5ec4a35..63ec044 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sp5100;
u32 apicid_sr5650;
device_t dev;
- u32 dword;
+ u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
#ifdef UNUSED_CODE
@@ -72,8 +72,8 @@ static void *smp_write_config_table(void *v)
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xAC);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = dword & ~(7 << 26);
+ dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xAC, dword);
#endif
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 4fbb4c8..3fd2de7 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x00000ab5;
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 5ec4a35..a47e190 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sp5100;
u32 apicid_sr5650;
device_t dev;
- u32 dword;
+ u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
#ifdef UNUSED_CODE
@@ -71,9 +71,9 @@ static void *smp_write_config_table(void *v)
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
- dword = pci_read_config32(dev, 0xAC);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = (u32 *)pci_read_config32(dev, 0xAC);
+ dword = dword & ~(7 << 26);
+ dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xAC, dword);
#endif
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
}
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 84593fc..860c417 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -56,13 +56,13 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
- u32 dword;
+ u32 *dword;
u8 byte;
dev = dev_find_slot(0, //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x11, dword);
/* Initialize interrupt mapping */
@@ -73,11 +73,11 @@ static void *smp_write_config_table(void *v)
pci_write_config8(dev, 0x63, byte);
/* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = (u32 *)((pci_read_config32(dev, 0xac) &
+ ~(7 << 26)) | (6 << 26));
+
/* dword |= 1<<22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
+ pci_write_config32(dev, 0xac, (u32)dword);
/*
* 00:12.0: PROG SATA : INT F
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100+1, 0x11, dword);
}
}
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
index 83e34b5..9bffd54 100644
--- a/src/mainboard/supermicro/x7db8/romstage.c
+++ b/src/mainboard/supermicro/x7db8/romstage.c
@@ -54,22 +54,22 @@ static void early_config(void)
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
- gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+ gcs = read32((u32 *)(DEFAULT_RCBA + RCBA_GCS));
gcs |= (1 << 5); /* No reset */
- write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+ write32((u32 *)(DEFAULT_RCBA + RCBA_GCS), gcs);
/* Configure PCIe port B as 4x */
- rpc = read32(DEFAULT_RCBA + RCBA_RPC);
+ rpc = read32((u32 *)(DEFAULT_RCBA + RCBA_RPC));
rpc |= (3 << 0);
- write32(DEFAULT_RCBA + RCBA_RPC, rpc);
+ write32((u32 *)(DEFAULT_RCBA + RCBA_RPC), rpc);
/* Disable Modem, Audio, PCIe ports 2/3/4 */
- fd = read32(DEFAULT_RCBA + RCBA_FD);
+ fd = read32((u32 *)(DEFAULT_RCBA + RCBA_FD));
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
- write32(DEFAULT_RCBA + RCBA_FD, fd);
+ write32((u32 *)(DEFAULT_RCBA + RCBA_FD), fd);
/* Enable HPET */
- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+ write32((u32 *)(DEFAULT_RCBA + RCBA_HPTC), (1 << 7));
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 8b86b02..45212be 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 8b86b02..45212be 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -59,7 +59,8 @@ static void *smp_write_config_table(void *v)
PCI_DEVFN(sbdn_sb600 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
- smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
+ smp_write_ioapic(mc, apicid_sb600,
+ 0x11,(void *) dword);
/* Initialize interrupt mapping */
/* aza */
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
index 7267696..4fb8056 100644
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ b/src/mainboard/thomson/ip1000/mainboard.c
@@ -65,14 +65,14 @@ static void parport_gpios(void)
static void flash_gpios(void)
{
- u8 manufacturer_id = read8(0xffbc0000);
- u8 device_id = read8(0xffbc0001);
+ u8 manufacturer_id = read8((u8 *)0xffbc0000);
+ u8 device_id = read8((u8 *)0xffbc0001);
if ((manufacturer_id == 0x20) &&
((device_id == 0x2c) || (device_id == 0x2d))) {
printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
(device_id==0x2c)?'4':'8');
- u8 fgpi = read8(0xffbc0100);
+ u8 fgpi = read8((u8 *)0xffbc0100);
printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
(fgpi & (1 << 0)) ? 'X' : ' ',
(fgpi & (1 << 1)) ? 'X' : ' ',
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 9073728..6a27a24 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 8, 0x20, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -25,14 +25,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x09, 0x20, res->base);
+ smp_write_ioapic(mc, 0x09, 0x20, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x0a, 0x20, res->base);
+ smp_write_ioapic(mc, 0x0a, 0x20, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 371d9a3..c476c6d 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v)
#endif
apicid_8111 = apicid_base+0;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 90299a7..09b232b 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_8111 = apicid_base+0;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 32fc639..95151e3 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v)
apicid_8111 = apicid_base+0;
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
@@ -126,14 +126,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index 7df5e87..9c7ed91 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -33,7 +33,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -41,14 +41,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 6c07965..c66d59d 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -116,7 +116,7 @@ static void *smp_write_config_table(void *v)
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -124,14 +124,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index 26081c7..d58894d 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR); //8111
{
device_t dev;
struct resource *res;
@@ -44,14 +44,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
}
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index cb49434..b53cca0 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11, (void *)(uintptr_t)res->base);
}
/* Initialize interrupt mapping*/
@@ -67,14 +67,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index 882ac69..720b481 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11, (void *)(uintptr_t)res->base);
}
/* Initialize interrupt mapping*/
@@ -67,14 +67,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index 20fa92c..228b494 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11, (void *)(uintptr_t)res->base);
}
/* Initialize interrupt mapping*/
@@ -75,14 +75,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
@@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804b, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x0000d218; // Why does the factory BIOS have 0?
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index 133ce43..dca09b8 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index e15387d..f7397b9 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+ smp_write_ioapic(mc, m->apicid_mcp55, 0x11, (void *)(uintptr_t)res->base);
}
dword = 0x43c6c643;
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index dcc0fd8..f668419 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v)
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -126,14 +126,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index 350b55c..8a8e540 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v)
apicid_8111 = apicid_base+0;
apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2;
- smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
+ smp_write_ioapic(mc, apicid_8111, 0x11, (void *)IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@@ -125,14 +125,14 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, (void *)(uintptr_t)res->base);
}
}
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, (void *)(uintptr_t)res->base);
}
}
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
index 5ec4a35..63ec044 100644
--- a/src/mainboard/tyan/s8226/mptable.c
+++ b/src/mainboard/tyan/s8226/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
u32 apicid_sp5100;
u32 apicid_sr5650;
device_t dev;
- u32 dword;
+ u32 *dword;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
#ifdef UNUSED_CODE
@@ -72,8 +72,8 @@ static void *smp_write_config_table(void *v)
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xAC);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = dword & ~(7 << 26);
+ dword = dword | (6 << 26); /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xAC, dword);
#endif
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
}
diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb
index 0c21cc8..aa2db2a 100644
--- a/src/mainboard/via/epia-m850/devicetree.cb
+++ b/src/mainboard/via/epia-m850/devicetree.cb
@@ -38,7 +38,7 @@ chip northbridge/via/vx900 # Northbridge
register "have_isa_interrupts" = "0"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfecc0000"
+ register "base" = "(void *)0xfecc0000"
device ioapic 2 on end
end
end
@@ -71,7 +71,7 @@ chip northbridge/via/vx900 # Northbridge
register "have_isa_interrupts" = "1"
register "irq_on_fsb" = "1"
register "enable_virtual_wire" = "1"
- register "base" = "0xfec00000"
+ register "base" = "(void *)0xfec00000"
device ioapic 1 on end
end
#chip drivers/generic/generic # DIMM 0 channel 1
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index f3f8186..760f595 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
+ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, (void *)IO_APIC_ADDR);
/* Now, assemble the table. */
mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0);
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index fc9cb99..434a532 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 17, IO_APIC_ADDR);
+ smp_write_ioapic(mc, 2, 17, (void *)IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c
index 26e79ca..1d00e31 100644
--- a/src/mainboard/winent/mb6047/mptable.c
+++ b/src/mainboard/winent/mb6047/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_ck804, 0x11, (void *)(uintptr_t)res->base);
}
/* Initialize interrupt mapping*/
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
index fa23344..9a73e63 100644
--- a/src/northbridge/amd/cimx/rd890/late.c
+++ b/src/northbridge/amd/cimx/rd890/late.c
@@ -119,10 +119,10 @@ struct chip_operations northbridge_amd_cimx_rd890_ops = {
static void ioapic_init(struct device *dev)
{
- u32 ioapic_base;
+ void *ioapic_base;
pci_write_config32(dev, 0xF8, 0x1);
- ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
clear_ioapic(ioapic_base);
setup_ioapic(ioapic_base, 1);
}
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 2247a25..a4d6c94 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -900,7 +900,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
RAM_DEBUG_MESSAGE("\n");
- read32(dimm_start_address + e7501_mode_bits);
+ read32((u32 *)(dimm_start_address + e7501_mode_bits));
// Set the start of the next DIMM
dimm_start_64M_multiple =
@@ -1708,7 +1708,7 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
- write32(dst_addr, *src_addr);
+ write32((u32 *)dst_addr, *src_addr);
src_addr++;
dst_addr += sizeof(uint32_t);
}
@@ -1740,82 +1740,82 @@ static void ram_set_rcomp_regs(void)
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
// Block RCOMP updates while we configure the registers
- dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword = read32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL));
dword |= (1 << 9);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL), dword);
/* Begin to write the RCOMP registers */
// Set CMD and DQ/DQS strength to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
+ maybe_strength_control = read8((u8 *)(RCOMP_MMIO + MAYBE_DQCMDSTR)) & 0x88;
maybe_strength_control |= 0x44;
- write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
+ write8((u8 *)(RCOMP_MMIO + MAYBE_DQCMDSTR), maybe_strength_control);
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
- write16(RCOMP_MMIO + 0x42, 0);
+ write16((u16 *)(RCOMP_MMIO + 0x42), 0);
write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
// NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
- write16(RCOMP_MMIO + 0x40, 0);
+ write16((u16 *)(RCOMP_MMIO + 0x40), 0);
// Set RCVEnOut# strength to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
+ maybe_strength_control = read8((u8 *)(RCOMP_MMIO + MAYBE_RCVENSTR)) & 0xF8;
maybe_strength_control |= 4;
- write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
+ write8((u8 *)(RCOMP_MMIO + MAYBE_RCVENSTR), maybe_strength_control);
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
- write16(RCOMP_MMIO + 0x50, 0);
+ write16((u16 *)(RCOMP_MMIO + 0x50), 0);
// Set CS# strength for x4 SDRAM to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
+ maybe_strength_control = read8((u8 *)(RCOMP_MMIO + MAYBE_CSBSTR)) & 0xF8;
maybe_strength_control |= 4;
- write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
+ write8((u8 *)(RCOMP_MMIO + MAYBE_CSBSTR), maybe_strength_control);
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
- write16(RCOMP_MMIO + 0x48, 0);
+ write16((u16 *)(RCOMP_MMIO + 0x48), 0);
// Set CKE strength for x4 SDRAM to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
+ maybe_strength_control = read8((u8 *)(RCOMP_MMIO + MAYBE_CKESTR)) & 0xF8;
maybe_strength_control |= 4;
- write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
+ write8((u8 *)(RCOMP_MMIO + MAYBE_CKESTR), maybe_strength_control);
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
- write16(RCOMP_MMIO + 0x44, 0);
+ write16((u16 *)(RCOMP_MMIO + 0x44), 0);
// Set CK strength for x4 SDRAM to 1x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
+ maybe_strength_control = read8((u8 *)(RCOMP_MMIO + MAYBE_CKSTR)) & 0xF8;
maybe_strength_control |= 1;
- write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
+ write8((u8 *)(RCOMP_MMIO + MAYBE_CKSTR), maybe_strength_control);
write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
- write16(RCOMP_MMIO + 0x4c, 0);
+ write16((u16 *)(RCOMP_MMIO + 0x4c), 0);
- write8(RCOMP_MMIO + 0x2c, 0xff);
+ write8((u8 *)(RCOMP_MMIO + 0x2c), 0xff);
// Set the digital filter length to 8 (?)
- dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword = read32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL));
// NOTE: Some factory BIOS don't do this.
// Doesn't seem to matter either way.
dword &= ~2;
dword |= 1;
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL), dword);
/* Wait 40 usec */
SLOW_DOWN_IO;
/* unblock updates */
- dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword = read32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL));
dword &= ~(1 << 9);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL), dword);
// Force a RCOMP measurement cycle?
dword |= (1 << 8);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL), dword);
dword &= ~(1 << 8);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32((u32 *)(RCOMP_MMIO + MAYBE_SMRCTL), dword);
/* Wait 40 usec */
SLOW_DOWN_IO;
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 909e740..35dc6b2 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -280,7 +280,7 @@ static void d060_control(d060_cc cmd)
*/
static void rcomp_smr_control(rcomp_smr_cc cmd)
{
- uint32_t dword = read32(RCOMP_MMIO + SMRCTL);
+ uint32_t dword = read32((void *)(RCOMP_MMIO + SMRCTL));
switch (cmd) {
case RCOMP_HOLD:
dword |= (1 << 9);
@@ -296,7 +296,7 @@ static void rcomp_smr_control(rcomp_smr_cc cmd)
dword |= (1 << 10) | (1 << 8);
break;
}
- write32(RCOMP_MMIO + SMRCTL, dword);
+ write32((void *)(RCOMP_MMIO + SMRCTL), dword);
}
/*-----------------------------------------------------------------------------
@@ -713,7 +713,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
dimm_start_address &= 0x3ffffff;
dimm_start_address |= dimm_start_64M_multiple << 26;
- read32(dimm_start_address);
+ read32((void *)dimm_start_address);
// Set the start of the next DIMM
dimm_start_64M_multiple = dimm_end_64M_multiple;
}
@@ -1525,7 +1525,7 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
- write32(dst_addr, *src_addr);
+ write32((void *)dst_addr, *src_addr);
src_addr++;
dst_addr += sizeof(uint32_t);
}
@@ -1549,78 +1549,78 @@ static void rcomp_copy_registers(void)
RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
/* Begin to write the RCOMP registers */
- write8(RCOMP_MMIO + 0x2c, 0x0);
+ write8((void *)(RCOMP_MMIO + 0x2c), 0x0);
// Set CMD and DQ/DQS strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88;
+ strength_control = read8((void *)(RCOMP_MMIO + DQCMDSTR)) & 0x88;
strength_control |= 0x40;
- write8(RCOMP_MMIO + DQCMDSTR, strength_control);
+ write8((void *)(RCOMP_MMIO + DQCMDSTR), strength_control);
write_8dwords(slew_2x, RCOMP_MMIO + 0x80);
- write16(RCOMP_MMIO + 0x42, 0);
+ write16((void *)(RCOMP_MMIO + 0x42), 0);
// Set CMD and DQ/DQS strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8;
+ strength_control = read8((void *)(RCOMP_MMIO + DQCMDSTR)) & 0xF8;
strength_control |= 0x04;
- write8(RCOMP_MMIO + DQCMDSTR, strength_control);
+ write8((void *)(RCOMP_MMIO + DQCMDSTR), strength_control);
write_8dwords(slew_2x, RCOMP_MMIO + 0x60);
- write16(RCOMP_MMIO + 0x40, 0);
+ write16((void *)(RCOMP_MMIO + 0x40), 0);
// Set RCVEnOut# strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8;
+ strength_control = read8((void *)(RCOMP_MMIO + RCVENSTR)) & 0xF8;
strength_control |= 0x04;
- write8(RCOMP_MMIO + RCVENSTR, strength_control);
+ write8((void *)(RCOMP_MMIO + RCVENSTR), strength_control);
write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0);
- write16(RCOMP_MMIO + 0x50, 0);
+ write16((void *)(RCOMP_MMIO + 0x50), 0);
// Set CS# strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88;
+ strength_control = read8((void *)(RCOMP_MMIO + CSBSTR)) & 0x88;
strength_control |= 0x04;
- write8(RCOMP_MMIO + CSBSTR, strength_control);
+ write8((void *)(RCOMP_MMIO + CSBSTR), strength_control);
write_8dwords(slew_2x, RCOMP_MMIO + 0x140);
- write16(RCOMP_MMIO + 0x48, 0);
+ write16((void *)(RCOMP_MMIO + 0x48), 0);
// Set CS# strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F;
+ strength_control = read8((void *)(RCOMP_MMIO + CSBSTR)) & 0x8F;
strength_control |= 0x40;
- write8(RCOMP_MMIO + CSBSTR, strength_control);
+ write8((void *)(RCOMP_MMIO + CSBSTR), strength_control);
write_8dwords(slew_2x, RCOMP_MMIO + 0x160);
- write16(RCOMP_MMIO + 0x4a, 0);
+ write16((void *)(RCOMP_MMIO + 0x4a), 0);
// Set CKE strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88;
+ strength_control = read8((void *)(RCOMP_MMIO + CKESTR)) & 0x88;
strength_control |= 0x04;
- write8(RCOMP_MMIO + CKESTR, strength_control);
+ write8((void *)(RCOMP_MMIO + CKESTR), strength_control);
write_8dwords(slew_2x, RCOMP_MMIO + 0xa0);
- write16(RCOMP_MMIO + 0x44, 0);
+ write16((void *)(RCOMP_MMIO + 0x44), 0);
// Set CKE strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F;
+ strength_control = read8((void *)(RCOMP_MMIO + CKESTR)) & 0x8F;
strength_control |= 0x40;
- write8(RCOMP_MMIO + CKESTR, strength_control);
+ write8((void *)(RCOMP_MMIO + CKESTR), strength_control);
write_8dwords(slew_2x, RCOMP_MMIO + 0xc0);
- write16(RCOMP_MMIO + 0x46, 0);
+ write16((void *)(RCOMP_MMIO + 0x46), 0);
// Set CK strength for x4 SDRAM to 1x (?)
- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88;
+ strength_control = read8((void *)(RCOMP_MMIO + CKSTR)) & 0x88;
strength_control |= 0x01;
- write8(RCOMP_MMIO + CKSTR, strength_control);
+ write8((void *)(RCOMP_MMIO + CKSTR), strength_control);
write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180);
- write16(RCOMP_MMIO + 0x4c, 0);
+ write16((void *)(RCOMP_MMIO + 0x4c), 0);
// Set CK strength for x4 SDRAM to 1x (?)
- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F;
+ strength_control = read8((void *)(RCOMP_MMIO + CKSTR)) & 0x8F;
strength_control |= 0x10;
- write8(RCOMP_MMIO + CKSTR, strength_control);
+ write8((void *)(RCOMP_MMIO + CKSTR), strength_control);
write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0);
- write16(RCOMP_MMIO + 0x4e, 0);
+ write16((void *)(RCOMP_MMIO + 0x4e), 0);
- dword = read32(RCOMP_MMIO + 0x400);
+ dword = read32((void *)(RCOMP_MMIO + 0x400));
dword &= 0x7f7fffff;
- write32(RCOMP_MMIO + 0x400, dword);
+ write32((void *)(RCOMP_MMIO + 0x400), dword);
- dword = read32(RCOMP_MMIO + 0x408);
+ dword = read32((void *)(RCOMP_MMIO + 0x408));
dword &= 0x7f7fffff;
- write32(RCOMP_MMIO + 0x408, dword);
+ write32((void *)(RCOMP_MMIO + 0x408), dword);
}
static void ram_set_rcomp_regs(void)
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index a372e7b..bf23e65 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 74e16ad..bafd1cb 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -43,63 +43,63 @@ static struct resource *gtt_res = NULL;
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32((u32 *)(uintptr_t)(gtt_res->base + reg), data);
}
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
static void power_port(u32 mmio)
{
- read32(mmio + 0x00061100); // = 0x00000000
- write32(mmio + 0x00061100, 0x00000000);
- write32(mmio + 0x00061100, 0x00010000);
- read32(mmio + 0x00061100); // = 0x00010000
- read32(mmio + 0x00061100); // = 0x00010000
- read32(mmio + 0x00061100); // = 0x00000000
- write32(mmio + 0x00061100, 0x00000000);
- read32(mmio + 0x00061100); // = 0x00000000
- read32(mmio + 0x00064200); // = 0x0000001c
- write32(mmio + 0x00064210, 0x8004003e);
- write32(mmio + 0x00064214, 0x80060002);
- write32(mmio + 0x00064218, 0x01000000);
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- read32(mmio + 0x00064210); // = 0x0144003e
- write32(mmio + 0x00064210, 0x8074003e);
- read32(mmio + 0x00064210); // = 0x5144003e
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- read32(mmio + 0x00064210); // = 0x0144003e
- write32(mmio + 0x00064210, 0x8074003e);
- read32(mmio + 0x00064210); // = 0x5144003e
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- read32(mmio + 0x00064210); // = 0x0144003e
- write32(mmio + 0x00064210, 0x8074003e);
- read32(mmio + 0x00064210); // = 0x5144003e
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- write32(mmio + 0x00064f00, 0x0100030c);
- write32(mmio + 0x00064f04, 0x00b8230c);
- write32(mmio + 0x00064f08, 0x06f8930c);
- write32(mmio + 0x00064f0c, 0x09f8e38e);
- write32(mmio + 0x00064f10, 0x00b8030c);
- write32(mmio + 0x00064f14, 0x0b78830c);
- write32(mmio + 0x00064f18, 0x0ff8d3cf);
- write32(mmio + 0x00064f1c, 0x01e8030c);
- write32(mmio + 0x00064f20, 0x0ff863cf);
- write32(mmio + 0x00064f24, 0x0ff803cf);
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x00044000); // = 0x00000000
- write32(mmio + 0x00044030, 0x00001000);
- read32(mmio + 0x00061150); // = 0x0000001c
- write32(mmio + 0x00061150, 0x0000089c);
- write32(mmio + 0x000fcc00, 0x01986f00);
- write32(mmio + 0x000fcc0c, 0x01986f00);
- write32(mmio + 0x000fcc18, 0x01986f00);
- write32(mmio + 0x000fcc24, 0x01986f00);
- read32(mmio + 0x00044000); // = 0x00000000
- read32(mmio + LVDS); // = 0x40000002
+ read32((u32 *)(mmio + 0x00061100)); // = 0x00000000
+ write32((u32 *)(mmio + 0x00061100), 0x00000000);
+ write32((u32 *)(mmio + 0x00061100), 0x00010000);
+ read32((u32 *)(mmio + 0x00061100)); // = 0x00010000
+ read32((u32 *)(mmio + 0x00061100)); // = 0x00010000
+ read32((u32 *)(mmio + 0x00061100)); // = 0x00000000
+ write32((u32 *)(mmio + 0x00061100), 0x00000000);
+ read32((u32 *)(mmio + 0x00061100)); // = 0x00000000
+ read32((u32 *)(mmio + 0x00064200)); // = 0x0000001c
+ write32((u32 *)(mmio + 0x00064210), 0x8004003e);
+ write32((u32 *)(mmio + 0x00064214), 0x80060002);
+ write32((u32 *)(mmio + 0x00064218), 0x01000000);
+ read32((u32 *)(mmio + 0x00064210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x00064210), 0x5344003e);
+ read32((u32 *)(mmio + 0x00064210)); // = 0x0144003e
+ write32((u32 *)(mmio + 0x00064210), 0x8074003e);
+ read32((u32 *)(mmio + 0x00064210)); // = 0x5144003e
+ read32((u32 *)(mmio + 0x00064210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x00064210), 0x5344003e);
+ read32((u32 *)(mmio + 0x00064210)); // = 0x0144003e
+ write32((u32 *)(mmio + 0x00064210), 0x8074003e);
+ read32((u32 *)(mmio + 0x00064210)); // = 0x5144003e
+ read32((u32 *)(mmio + 0x00064210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x00064210), 0x5344003e);
+ read32((u32 *)(mmio + 0x00064210)); // = 0x0144003e
+ write32((u32 *)(mmio + 0x00064210), 0x8074003e);
+ read32((u32 *)(mmio + 0x00064210)); // = 0x5144003e
+ read32((u32 *)(mmio + 0x00064210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x00064210), 0x5344003e);
+ write32((u32 *)(mmio + 0x00064f00), 0x0100030c);
+ write32((u32 *)(mmio + 0x00064f04), 0x00b8230c);
+ write32((u32 *)(mmio + 0x00064f08), 0x06f8930c);
+ write32((u32 *)(mmio + 0x00064f0c), 0x09f8e38e);
+ write32((u32 *)(mmio + 0x00064f10), 0x00b8030c);
+ write32((u32 *)(mmio + 0x00064f14), 0x0b78830c);
+ write32((u32 *)(mmio + 0x00064f18), 0x0ff8d3cf);
+ write32((u32 *)(mmio + 0x00064f1c), 0x01e8030c);
+ write32((u32 *)(mmio + 0x00064f20), 0x0ff863cf);
+ write32((u32 *)(mmio + 0x00064f24), 0x0ff803cf);
+ write32((u32 *)(mmio + 0x000c4030), 0x00001000);
+ read32((u32 *)(mmio + 0x00044000)); // = 0x00000000
+ write32((u32 *)(mmio + 0x00044030), 0x00001000);
+ read32((u32 *)(mmio + 0x00061150)); // = 0x0000001c
+ write32((u32 *)(mmio + 0x00061150), 0x0000089c);
+ write32((u32 *)(mmio + 0x000fcc00), 0x01986f00);
+ write32((u32 *)(mmio + 0x000fcc0c), 0x01986f00);
+ write32((u32 *)(mmio + 0x000fcc18), 0x01986f00);
+ write32((u32 *)(mmio + 0x000fcc24), 0x01986f00);
+ read32((u32 *)(mmio + 0x00044000)); // = 0x00000000
+ read32((u32 *)(mmio + LVDS)); // = 0x40000002
}
static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
@@ -134,9 +134,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
outl(physbase + (i << 12) + 1, piobase + 4);
}
- write32(mmio + 0x61100, 0x40008c18);
- write32(mmio + 0x7041c, 0x0);
- write32(mmio + 0x6020, 0x3);
+ write32((u32 *)(mmio + 0x61100), 0x40008c18);
+ write32((u32 *)(mmio + 0x7041c), 0x0);
+ write32((u32 *)(mmio + 0x6020), 0x3);
vga_misc_write(0x67);
@@ -194,12 +194,12 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32((u32 *)(mmio + DSPCNTR(0)), DISPPLANE_BGRX888);
+ write32((u32 *)(mmio + DSPADDR(0)), 0);
+ write32((u32 *)(mmio + DSPSTRIDE(0)), edid.bytes_per_line);
+ write32((u32 *)(mmio + DSPSURF(0)), 0);
for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ write32((u32 *)(mmio + LGC_PALETTE(0) + 4 * i), i * 0x010101);
#endif
/* Find suitable divisors. */
@@ -272,159 +272,136 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
+ write32((u32 *)(mmio + LVDS),
+ (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
mdelay(1);
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + FP0(0),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32((u32 *)(mmio + PP_CONTROL),
+ PANEL_UNLOCK_REGS | (read32((u32 *)(mmio + PP_CONTROL)) & ~PANEL_UNLOCK_MASK));
+ write32((u32 *)(mmio + FP0(0)),
+ ((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2);
+ write32((u32 *)(mmio + DPLL(0)),
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)));
mdelay(1);
- write32(mmio + DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32((u32 *)(mmio + DPLL(0)),
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */
- write32(mmio + PP_CONTROL,
- (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
- write32(mmio + LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-
- write32(mmio + HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
- write32(mmio + PF_WIN_POS(0), 0);
+ write32((u32 *)(mmio + PP_CONTROL),
+ (read32((u32 *)(mmio + PP_CONTROL)) & ~PANEL_UNLOCK_MASK));
+
+ write32((u32 *)(mmio + LVDS),
+ (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
+
+ write32((u32 *)(mmio + HTOTAL(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive - 1));
+ write32((u32 *)(mmio + HBLANK(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1));
+ write32((u32 *)(mmio + HSYNC(0)),
+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1));
+
+ write32((u32 *)(mmio + VTOTAL(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1));
+ write32((u32 *)(mmio + VBLANK(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1));
+ write32((u32 *)(mmio + VSYNC(0)),
+ (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1));
+
+ write32((u32 *)(mmio + PIPECONF(0)), PIPECONF_DISABLE);
+
+ write32((u32 *)(mmio + PF_WIN_POS(0)), 0);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
- write32(mmio + PFIT_CONTROL, 0x20000000);
+ write32((u32 *)(mmio + PIPESRC(0)),
+ ((hactive - 1) << 16) | (vactive - 1));
+ write32((u32 *)(mmio + PF_CTL(0)), 0);
+ write32((u32 *)(mmio + PF_WIN_SZ(0)), 0);
+ write32((u32 *)(mmio + PFIT_CONTROL), 0x20000000);
#else
- write32(mmio + PIPESRC(0), (639 << 16) | 399);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
- write32(mmio + PFIT_CONTROL, 0xa0000000);
+ write32((u32 *)(mmio + PIPESRC(0)), (639 << 16) | 399);
+ write32((u32 *)(mmio + PF_CTL(0)), PF_ENABLE | PF_FILTER_MED_3x3);
+ write32((u32 *)(mmio + PF_WIN_SZ(0)), vactive | (hactive << 16));
+ write32((u32 *)(mmio + PFIT_CONTROL), 0xa0000000);
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32((u32 *)(mmio + PIPE_DATA_M1(0)), 0x7e000000 | data_m1);
+ write32((u32 *)(mmio + PIPE_DATA_N1(0)), data_n1);
+ write32((u32 *)(mmio + PIPE_LINK_M1(0)), link_m1);
+ write32((u32 *)(mmio + PIPE_LINK_N1(0)), link_n1);
- write32(mmio + 0x000f000c, 0x00002040);
+ write32((u32 *)(mmio + 0x000f000c), 0x00002040);
mdelay(1);
- write32(mmio + 0x000f000c, 0x00002050);
- write32(mmio + 0x00060100, 0x00044000);
+ write32((u32 *)(mmio + 0x000f000c), 0x00002050);
+ write32((u32 *)(mmio + 0x00060100), 0x00044000);
mdelay(1);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
- write32(mmio + 0x000f0008, 0x00000040);
- write32(mmio + 0x000f000c, 0x00022050);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32((u32 *)(mmio + PIPECONF(0)), PIPECONF_BPP_6);
+ write32((u32 *)(mmio + 0x000f0008), 0x00000040);
+ write32((u32 *)(mmio + 0x000f000c), 0x00022050);
+ write32((u32 *)(mmio + PIPECONF(0)),
+ PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32((u32 *)(mmio + PIPECONF(0)),
+ PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE);
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32((u32 *)(mmio + VGACNTRL), 0x22c4008e | VGA_DISP_DISABLE);
+ write32((u32 *)(mmio + DSPCNTR(0)),
+ DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
#else
- write32(mmio + VGACNTRL, 0x22c4008e);
+ write32((u32 *)(mmio + VGACNTRL), 0x22c4008e);
#endif
- write32(mmio + TRANS_HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + TRANS_VTOTAL(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + 0x00060100, 0xb01c4000);
- write32(mmio + 0x000f000c, 0xb01a2050);
+ write32((u32 *)(mmio + TRANS_HTOTAL(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive - 1));
+ write32((u32 *)(mmio + TRANS_HBLANK(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1));
+ write32((u32 *)(mmio + TRANS_HSYNC(0)),
+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1));
+
+ write32((u32 *)(mmio + TRANS_VTOTAL(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1));
+ write32((u32 *)(mmio + TRANS_VBLANK(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1));
+ write32((u32 *)(mmio + TRANS_VSYNC(0)),
+ (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1));
+
+ write32((u32 *)(mmio + 0x00060100), 0xb01c4000);
+ write32((u32 *)(mmio + 0x000f000c), 0xb01a2050);
mdelay(1);
- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32((u32 *)(mmio + TRANSCONF(0)), TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
+
+ | TRANS_STATE_MASK
#endif
- );
- write32(mmio + LVDS,
- LVDS_PORT_ENABLE
- | (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+);
+ write32((u32 *)(mmio + LVDS),
+ LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
+
+ write32((u32 *)(mmio + PP_CONTROL),
+ PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ write32((u32 *)(mmio + PP_CONTROL),
+ PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
mdelay(1);
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32((u32 *)(mmio + PP_CONTROL),
+ PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET);
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
- reg32 = read32(mmio + PP_STATUS);
+ reg32 = read32((u32 *)(mmio + PP_STATUS));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32((u32 *)(mmio + PP_CONTROL),
+ PANEL_POWER_ON | PANEL_POWER_RESET);
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32((u32 *)(mmio + DEIIR), 0xffffffff);
+ write32((u32 *)(mmio + SDEIIR), 0xffffffff);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 60b05bd..2c810de 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1579,15 +1579,15 @@ static void jedec_init(const timings_t *const timings,
const u32 rankaddr = raminit_get_rank_addr(ch, r);
printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2);
- read32(rankaddr | WL);
+ read32((u32 *)(rankaddr | WL));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3);
- read32(rankaddr);
+ read32((u32 *)rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1);
- read32(rankaddr | ODT_120OHMS | ODS_34OHMS);
+ read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | DLL1 | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED));
}
}
@@ -1701,7 +1701,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
/* Wait for some bit, maybe TXT clear. */
if (sysinfo->txt_enabled) {
- while (!(read8(0xfed40000) & (1 << 7))) {}
+ while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
}
/* Enable SMBUS. */
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 5149c2b..b03cb33 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -114,7 +114,7 @@ static int read_training_test(const int channel, const int lane,
for (i = 0; i < addresses->count; ++i) {
unsigned int offset;
for (offset = lane_offset; offset < 320; offset += 8) {
- const u32 read = read32(addresses->addr[i] + offset);
+ const u32 read = read32((u32 *)(addresses->addr[i] + offset));
const u32 good = read_training_schedule[offset >> 3];
if ((read & lane_mask) != (good & lane_mask))
return 0;
@@ -228,7 +228,7 @@ static void perform_read_training(const dimminfo_t *const dimms)
/* Write test pattern. */
unsigned int offset;
for (offset = 0; offset < 320; offset += 4)
- write32(addresses.addr[i] + offset,
+ write32((u32 *)(addresses.addr[i] + offset),
read_training_schedule[offset >> 3]);
}
@@ -436,18 +436,18 @@ static int write_training_test(const address_bunch_t *const addresses,
unsigned int off;
for (off = 0; off < 640; off += 8) {
const u32 pattern = write_training_schedule[off >> 3];
- write32(addr + off, pattern);
- write32(addr + off + 4, pattern);
+ write32((u32 *)(addr + off), pattern);
+ write32((u32 *)(addr + off + 4), pattern);
}
MCHBAR8(0x78) |= 1;
for (off = 0; off < 640; off += 8) {
const u32 good = write_training_schedule[off >> 3];
- const u32 read1 = read32(addr + off);
+ const u32 read1 = read32((u32 *)(addr + off));
if ((read1 & masks[0]) != (good & masks[0]))
goto _bad_timing_out;
- const u32 read2 = read32(addr + off + 4);
+ const u32 read2 = read32((u32 *)(addr + off + 4));
if ((read2 & masks[1]) != (good & masks[1]))
goto _bad_timing_out;
}
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index 5130b59..62be05e 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -147,7 +147,7 @@ static int read_dqs_level(const int channel, const int lane)
MCHBAR32(mchbar) |= (1 << 9);
/* Read from this channel. */
- read32(raminit_get_rank_addr(channel, 0));
+ read32((u32 *)raminit_get_rank_addr(channel, 0));
mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4);
return MCHBAR32(mchbar) & (1 << 30);
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 488170d..1b77b64 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -118,7 +118,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 325edbd..3339f44 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -171,14 +171,14 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
u32 val;
- val = read32(gtt_res->base + reg);
+ val = read32((u32 *)(uintptr_t)(gtt_res->base + reg));
return val;
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32((u32 *)(uintptr_t)(gtt_res->base + reg), data);
}
static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index 4a38b28..1077468 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -67,7 +67,8 @@ static const u32 minihd_verb_table[] = {
static void minihd_init(struct device *dev)
{
struct resource *res;
- u32 base, reg32;
+ u32 reg32;
+ u8 *base;
int codec_mask, i;
/* Find base address */
@@ -75,8 +76,8 @@ static void minihd_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base);
+ base = (u8 *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 4f5a989..2af2a73 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -694,11 +694,11 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=2) {
- write32(MCBAR+DCALADDR, 0x0b840001);
- write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
+ write32((void *)(MCBAR + DCALADDR), 0x0b840001);
+ write32((void *)(MCBAR + DCALCSR), 0x81000003 | (dimm << 20));
for(i=0;i<1001;i++) {
- data32 = read32(MCBAR+DCALCSR);
+ data32 = read32((void *)(MCBAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
@@ -726,27 +726,29 @@ static void set_receive_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=1) {
if(!(dimm&1)) {
- write32(MCBAR+DCALDATA+(17*4), 0x04020000);
- write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
+ write32((void *)(MCBAR + DCALDATA + (17 * 4)),
+ 0x04020000);
+ write32((void *)(MCBAR + DCALCSR),
+ 0x81800004 | (dimm << 20));
for(i=0;i<1001;i++) {
- data32 = read32(MCBAR+DCALCSR);
+ data32 = read32((void *)(MCBAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
if(i>=1000)
continue;
- dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
- dcal_data32_1 = read32(MCBAR+DCALDATA + 4);
- dcal_data32_2 = read32(MCBAR+DCALDATA + 8);
- dcal_data32_3 = read32(MCBAR+DCALDATA + 12);
+ dcal_data32_0 = read32((void *)(MCBAR + DCALDATA + 0));
+ dcal_data32_1 = read32((void *)(MCBAR + DCALDATA + 4));
+ dcal_data32_2 = read32((void *)(MCBAR + DCALDATA + 8));
+ dcal_data32_3 = read32((void *)(MCBAR + DCALDATA + 12));
}
else {
- dcal_data32_0 = read32(MCBAR+DCALDATA + 16);
- dcal_data32_1 = read32(MCBAR+DCALDATA + 20);
- dcal_data32_2 = read32(MCBAR+DCALDATA + 24);
- dcal_data32_3 = read32(MCBAR+DCALDATA + 28);
+ dcal_data32_0 = read32((void *)(MCBAR + DCALDATA + 16));
+ dcal_data32_1 = read32((void *)(MCBAR + DCALDATA + 20));
+ dcal_data32_2 = read32((void *)(MCBAR + DCALDATA + 24));
+ dcal_data32_3 = read32((void *)(MCBAR + DCALDATA + 28));
}
/* check if bank is installed */
@@ -923,16 +925,16 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug("\n");
/* clear out the calibration area */
- write32(MCBAR+DCALDATA+(16*4), 0x00000000);
- write32(MCBAR+DCALDATA+(17*4), 0x00000000);
- write32(MCBAR+DCALDATA+(18*4), 0x00000000);
- write32(MCBAR+DCALDATA+(19*4), 0x00000000);
+ write32((void *)(MCBAR + DCALDATA + (16 * 4)), 0x00000000);
+ write32((void *)(MCBAR + DCALDATA + (17 * 4)), 0x00000000);
+ write32((void *)(MCBAR + DCALDATA + (18 * 4)), 0x00000000);
+ write32((void *)(MCBAR + DCALDATA + (19 * 4)), 0x00000000);
/* No command */
- write32(MCBAR+DCALCSR, 0x0000000f);
+ write32((void *)(MCBAR + DCALCSR), 0x0000000f);
- write32(MCBAR+0x150, recena);
- write32(MCBAR+0x154, recenb);
+ write32((void *)(MCBAR + 0x150), recena);
+ write32((void *)(MCBAR + 0x154), recenb);
}
@@ -1019,10 +1021,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
do_delay();
- write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
- write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
+ write32((void *)(MCBAR + DCALCSR), (0x01000000 | (i << 20)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000000 | (i << 20)));
- do data32 = read32(MCBAR+DCALCSR);
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1030,17 +1032,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALCSR), (0x81000000 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Precharg all banks */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, 0x04000000);
- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALADDR), 0x04000000);
+ write32((void *)(MCBAR + DCALCSR), (0x81000002 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1048,9 +1050,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs+=2) {
/* fixme hard code AL additive latency */
- write32(MCBAR+DCALADDR, 0x0b940001);
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALADDR), 0x0b940001);
+ write32((void *)(MCBAR + DCALCSR), (0x81000003 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* MRS reset dll's */
@@ -1060,9 +1062,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
else
mode_reg = 0x054a0000;
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, mode_reg);
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALADDR), mode_reg);
+ write32((void *)(MCBAR + DCALCSR), (0x81000003 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1071,72 +1073,72 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, 0x04000000);
- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALADDR), 0x04000000);
+ write32((void *)(MCBAR + DCALCSR), (0x81000002 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Do 2 refreshes */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
/* for good luck do 6 more */
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000001 | (cs << 20)));
}
do_delay();
/* MRS reset dll's normal */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALADDR), (mode_reg & ~(1 << 24)));
+ write32((void *)(MCBAR + DCALCSR), (0x81000003 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Do only if DDR2 EMRS dll's enabled */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, (0x0b940001));
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALADDR), (0x0b940001));
+ write32((void *)(MCBAR + DCALCSR), (0x81000003 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
/* No command */
- write32(MCBAR+DCALCSR, 0x0000000f);
+ write32((void *)(MCBAR + DCALCSR), 0x0000000f);
/* enable on dimm termination */
set_on_dimm_termination_enable(ctrl);
@@ -1147,7 +1149,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
- write32(cnt, dqs_data[i]);
+ write32((void *)cnt, dqs_data[i]);
}
pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
@@ -1155,17 +1157,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 0x7c DRC */
data32 = drc & ~(3 << 20); /* clear ECC mode */
pci_write_config32(ctrl->f0, DRC, data32);
- write32(MCBAR+DCALCSR, 0x0008000f);
+ write32((void *)(MCBAR + DCALCSR), 0x0008000f);
/* clear memory and init ECC */
print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
- write32(MCBAR+DCALDATA+i, 0x00000000);
+ write32((void *)(MCBAR + DCALDATA + i), 0x00000000);
}
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((void *)(MCBAR + DCALCSR), (0x810831d8 | (cs << 20)));
+ do data32 = read32((void *)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index cff7879..1e14644 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -531,9 +531,9 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
print_debug_hex8(i);
print_debug("\n");
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALADDR), 0x0b840001);
+ write32((u32 *)(BAR + DCALCSR), 0x80000003 | ((i + 1) << 21));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
}
@@ -548,7 +548,7 @@ static void dump_dcal_regs(void)
print_debug_hex16(i);
print_debug(": ");
}
- print_debug_hex32(read32(BAR+i));
+ print_debug_hex32(read32((u32 *)(BAR + i)));
print_debug(" ");
}
print_debug("\n");
@@ -597,9 +597,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug_hex8(cs);
print_debug("\n");
udelay(16);
- write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
- write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x00000000 | ((cs + 1) << 21)));
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000000 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -609,8 +611,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("NOP CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000000 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -620,9 +623,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Precharge CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x04000000);
- write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALADDR), 0x04000000);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000002 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -632,9 +636,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("EMRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALADDR), 0x0b840001);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000003 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
/* MRS: Reset DLLs */
@@ -643,9 +648,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("MRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, mode_reg);
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALADDR), mode_reg);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000003 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -655,9 +661,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Precharge CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x04000000);
- write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALADDR), 0x04000000);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000002 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -668,8 +675,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Refresh CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000001 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
}
@@ -680,9 +688,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("MRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALADDR), (mode_reg & ~(1 << 24)));
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000003 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -692,17 +701,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("EMRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALADDR), 0x0b840001);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x80000003 | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
udelay(16);
/* No command */
- write32(BAR+DCALCSR, 0x0000000f);
+ write32((u32 *)(BAR + DCALCSR), 0x0000000f);
- write32(BAR, 0x00100000);
+ write32((u32 *)BAR, 0x00100000);
/* Enable on-DIMM termination */
set_on_dimm_termination_enable(ctrl);
@@ -715,24 +725,25 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("receive enable calibration CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((u32 *)(BAR + DCALCSR),
+ (0x8000000c | ((cs + 1) << 21)));
+ do data32 = read32((u32 *)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
dump_dcal_regs();
/* Adjust RCOMP */
- data32 = read32(BAR+DDRIOMC2);
+ data32 = read32((u32 *)(BAR + DDRIOMC2));
data32 &= ~(0xf << 16);
data32 |= (0xb << 16);
- write32(BAR+DDRIOMC2, data32);
+ write32((u32 *)(BAR + DDRIOMC2), data32);
dump_dcal_regs();
data32 = drc & ~(3 << 20); /* clear ECC mode */
pci_write_config32(ctrl->f0, DRC, data32);
- write32(BAR+DCALCSR, 0x0008000f);
+ write32((u32 *)(BAR + DCALCSR), 0x0008000f);
/* Clear memory and init ECC */
for (cs = 0; cs < 2; cs++) {
@@ -741,8 +752,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("clear memory CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
- do data32 = read32(BAR+MBCSR);
+ write32((u32 *)(BAR + MBCSR),
+ 0xa00000f0 | ((cs + 1) << 20) | (0 << 16));
+ do data32 = read32((u32 *)(BAR + MBCSR));
while (data32 & 0x80000000);
if (data32 & 0x40000000)
print_debug("failed!\n");
@@ -750,9 +762,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Clear read/write FIFO pointers */
print_debug("clear read/write fifo pointers\n");
- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
+ write32((u32 *)(BAR + DDRIOMC2),
+ read32((u32 *)(BAR + DDRIOMC2)) | (1 << 15));
udelay(16);
- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
+ write32((u32 *)(BAR + DDRIOMC2),
+ read32((u32 *)(BAR + DDRIOMC2)) & ~(1 << 15));
udelay(16);
dump_dcal_regs();
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index e3cfbdf..4ee172a 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -387,7 +387,8 @@ static void do_ram_command(u32 command)
int i, caslatency;
u8 dimm_start, dimm_end;
u16 reg16;
- u32 addr, addr_offset;
+ void *addr;
+ u32 addr_offset;
/* Configure the RAM command. */
reg16 = pci_read_config16(NB, SDRAMC);
@@ -424,7 +425,7 @@ static void do_ram_command(u32 command)
dimm_end = pci_read_config8(NB, DRB + i);
- addr = (dimm_start * 8 * 1024 * 1024) + addr_offset;
+ addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset);
if (dimm_end > dimm_start) {
#if 0
PRINT_DEBUG(" Sending RAM command 0x%04x to 0x%08x\n",
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 5394002..b564bf1 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -458,25 +458,25 @@ static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
static void i5000_amb_write_config8(struct i5000_fbdimm *d,
int fn, int reg, u32 val)
{
- write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+ write8((u8 *)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)), val);
}
static void i5000_amb_write_config16(struct i5000_fbdimm *d,
int fn, int reg, u32 val)
{
- write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+ write16((u16 *)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)), val);
}
static void i5000_amb_write_config32(struct i5000_fbdimm *d,
int fn, int reg, u32 val)
{
- write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+ write32((u32 *)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)), val);
}
static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
int fn, int reg)
{
- return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+ return read32((u32 *)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)));
}
static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 904c960..3db1bbb 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -138,7 +138,7 @@ SDRAM configuration functions.
*/
static void do_ram_command(u8 command)
{
- u32 addr, addr_offset;
+ u32 *addr, addr_offset;
u16 dimm_size, dimm_start, dimm_bank;
u8 reg8, drp;
int i, caslatency;
@@ -191,15 +191,15 @@ static void do_ram_command(u8 command)
dimm_size = translate_i82810_to_mb[drp];
if (dimm_size) {
- addr = (dimm_start * 1024 * 1024) + addr_offset;
- PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
+ addr = (u32 *)((dimm_start * 1024 * 1024) + addr_offset);
+ PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr);
read32(addr);
}
dimm_bank = translate_i82810_to_bank[drp];
if (dimm_bank) {
- addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
- PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
+ addr = (u32 *)(((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset);
+ PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr);
read32(addr);
}
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index a42374c..bff59bf 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -77,15 +77,15 @@ static void ram_read32(u8 dimm_start, u32 offset)
{
u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;
if (offset == 0x55aa55aa) {
- reg32 = read32(base_addr);
+ reg32 = read32((u32 *)base_addr);
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);
- write32(base_addr, offset);
- reg32 = read32(base_addr);
+ write32((u32 *)base_addr, offset);
+ reg32 = read32((u32 *)base_addr);
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
} else {
PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);
- read32(base_addr + offset);
+ read32((u32 *)(base_addr + offset));
}
}
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index e4d93cf..65df70b 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -297,7 +297,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
static void smi_interface_call(void)
{
- u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
+ u32 *mmio = (u32 *)pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
// mmio &= 0xfff80000;
// printk(BIOS_DEBUG, "mmio=%x\n", mmio);
u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
@@ -317,7 +317,7 @@ static void smi_interface_call(void)
swsmi |= (PC13 << 8);
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
// write magic
- write32(mmio + 0x71428, 0x494e5443);
+ write32(mmio + (0x71428/sizeof(u32)), 0x494e5443);
return;
case 4:
printk(BIOS_DEBUG, "Get BIOS Data.\n");
@@ -325,7 +325,7 @@ static void smi_interface_call(void)
break;
case 5:
printk(BIOS_DEBUG, "Call MBI Functions.\n");
- mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
+ mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + (0x71428/sizeof(u32))) & 0x000fffff) + OBJ_OFFSET) );
// swsmi = 0x0000;
swsmi &= ~(7 << 5); // Exit: Result
swsmi |= (SMI_IFC_SUCCESS << 5);
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 0ab4d38..b12df6a 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -393,7 +393,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
- read32(dimm_start_address + i855_mode_bits);
+ read32((void *)(dimm_start_address + i855_mode_bits));
// Set the start of the next DIMM
dimm_start_32M_multiple = dimm_end_32M_multiple;
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index e9b6e3f..666991d 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -90,7 +90,7 @@ static void ram_read32(u32 offset)
{
PRINTK_DEBUG(" ram read: %08x\n", offset);
- read32(offset);
+ read32((void *)offset);
}
#if CONFIG_DEBUG_RAM_SETUP
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 88d6a00..6d429e4 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -42,8 +42,8 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
}
for (i = 0; i < 28; i++) {
- read32(addr);
- read32(addr + 0x80);
+ read32((void *)addr);
+ read32((void *)(addr + 0x80));
}
reg32 = MCHBAR32(RCVENMT);
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 460942f..4a208ce 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion)
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index c3e2a49..f546c5b 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -274,12 +274,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32((u32 *)(uintptr_t)(gtt_res->base + reg));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32((u32 *)(uintptr_t)(gtt_res->base + reg), data);
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -564,78 +564,78 @@ static void gma_pm_init_post_vbios(struct device *dev)
static void train_link(u32 mmio)
{
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
-
- write32(mmio + 0x000f0018, 0x000000ff);
- write32(mmio + 0x000f1018, 0x000000ff);
- write32(mmio + 0x000f000c, 0x001a2050);
- write32(mmio + 0x00060100, 0x001c4000);
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
+ write32((u32 *)(mmio + DEIIR), 0xffffffff);
+
+ write32((u32 *)(mmio + 0x000f0018), 0x000000ff);
+ write32((u32 *)(mmio + 0x000f1018), 0x000000ff);
+ write32((u32 *)(mmio + 0x000f000c), 0x001a2050);
+ write32((u32 *)(mmio + 0x00060100), 0x001c4000);
+ write32((u32 *)(mmio + 0x00060100), 0x801c4000);
+ write32((u32 *)(mmio + 0x000f000c), 0x801a2050);
+ write32((u32 *)(mmio + 0x00060100), 0x801c4000);
+ write32((u32 *)(mmio + 0x000f000c), 0x801a2050);
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000100
- write32(mmio + 0x000f0014, 0x00000100);
- write32(mmio + 0x00060100, 0x901c4000);
- write32(mmio + 0x000f000c, 0x901a2050);
+ read32((u32 *)(mmio + 0x000f0014)); // = 0x00000100
+ write32((u32 *)(mmio + 0x000f0014), 0x00000100);
+ write32((u32 *)(mmio + 0x00060100), 0x901c4000);
+ write32((u32 *)(mmio + 0x000f000c), 0x901a2050);
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000600
+ read32((u32 *)(mmio + 0x000f0014)); // = 0x00000600
}
static void power_port(u32 mmio)
{
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- write32(mmio + 0x000e1100, 0x00010000);
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- read32(mmio + 0x000e1100); // = 0x00000000
- read32(mmio + 0x000e4200); // = 0x0000001c
- write32(mmio + 0x000e4210, 0x8004003e);
- write32(mmio + 0x000e4214, 0x80060002);
- write32(mmio + 0x000e4218, 0x01000000);
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- write32(mmio + 0x000e4f00, 0x0100030c);
- write32(mmio + 0x000e4f04, 0x00b8230c);
- write32(mmio + 0x000e4f08, 0x06f8930c);
- write32(mmio + 0x000e4f0c, 0x09f8e38e);
- write32(mmio + 0x000e4f10, 0x00b8030c);
- write32(mmio + 0x000e4f14, 0x0b78830c);
- write32(mmio + 0x000e4f18, 0x0ff8d3cf);
- write32(mmio + 0x000e4f1c, 0x01e8030c);
- write32(mmio + 0x000e4f20, 0x0ff863cf);
- write32(mmio + 0x000e4f24, 0x0ff803cf);
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000c4000); // = 0x00000000
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000e1150); // = 0x0000001c
- write32(mmio + 0x000e1150, 0x0000089c);
- write32(mmio + 0x000fcc00, 0x01986f00);
- write32(mmio + 0x000fcc0c, 0x01986f00);
- write32(mmio + 0x000fcc18, 0x01986f00);
- write32(mmio + 0x000fcc24, 0x01986f00);
- read32(mmio + 0x000c4000); // = 0x00000000
- read32(mmio + 0x000e1180); // = 0x40000002
+ read32((u32 *)(mmio + 0x000e1100)); // = 0x00000000
+ write32((u32 *)(mmio + 0x000e1100), 0x00000000);
+ write32((u32 *)(mmio + 0x000e1100), 0x00010000);
+ read32((u32 *)(mmio + 0x000e1100)); // = 0x00010000
+ read32((u32 *)(mmio + 0x000e1100)); // = 0x00010000
+ read32((u32 *)(mmio + 0x000e1100)); // = 0x00000000
+ write32((u32 *)(mmio + 0x000e1100), 0x00000000);
+ read32((u32 *)(mmio + 0x000e1100)); // = 0x00000000
+ read32((u32 *)(mmio + 0x000e4200)); // = 0x0000001c
+ write32((u32 *)(mmio + 0x000e4210), 0x8004003e);
+ write32((u32 *)(mmio + 0x000e4214), 0x80060002);
+ write32((u32 *)(mmio + 0x000e4218), 0x01000000);
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x000e4210), 0x5344003e);
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x0144003e
+ write32((u32 *)(mmio + 0x000e4210), 0x8074003e);
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x000e4210), 0x5344003e);
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x0144003e
+ write32((u32 *)(mmio + 0x000e4210), 0x8074003e);
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x000e4210), 0x5344003e);
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x0144003e
+ write32((u32 *)(mmio + 0x000e4210), 0x8074003e);
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((u32 *)(mmio + 0x000e4210)); // = 0x5144003e
+ write32((u32 *)(mmio + 0x000e4210), 0x5344003e);
+ write32((u32 *)(mmio + 0x000e4f00), 0x0100030c);
+ write32((u32 *)(mmio + 0x000e4f04), 0x00b8230c);
+ write32((u32 *)(mmio + 0x000e4f08), 0x06f8930c);
+ write32((u32 *)(mmio + 0x000e4f0c), 0x09f8e38e);
+ write32((u32 *)(mmio + 0x000e4f10), 0x00b8030c);
+ write32((u32 *)(mmio + 0x000e4f14), 0x0b78830c);
+ write32((u32 *)(mmio + 0x000e4f18), 0x0ff8d3cf);
+ write32((u32 *)(mmio + 0x000e4f1c), 0x01e8030c);
+ write32((u32 *)(mmio + 0x000e4f20), 0x0ff863cf);
+ write32((u32 *)(mmio + 0x000e4f24), 0x0ff803cf);
+ write32((u32 *)(mmio + 0x000c4030), 0x00001000);
+ read32((u32 *)(mmio + 0x000c4000)); // = 0x00000000
+ write32((u32 *)(mmio + 0x000c4030), 0x00001000);
+ read32((u32 *)(mmio + 0x000e1150)); // = 0x0000001c
+ write32((u32 *)(mmio + 0x000e1150), 0x0000089c);
+ write32((u32 *)(mmio + 0x000fcc00), 0x01986f00);
+ write32((u32 *)(mmio + 0x000fcc0c), 0x01986f00);
+ write32((u32 *)(mmio + 0x000fcc18), 0x01986f00);
+ write32((u32 *)(mmio + 0x000fcc24), 0x01986f00);
+ read32((u32 *)(mmio + 0x000c4000)); // = 0x00000000
+ read32((u32 *)(mmio + 0x000e1180)); // = 0x40000002
}
static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
@@ -660,23 +660,23 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
u32 link_m1;
u32 link_n1 = 0x00080000;
- write32(mmio + 0x00070080, 0x00000000);
- write32(mmio + DSPCNTR(0), 0x00000000);
- write32(mmio + 0x00071180, 0x00000000);
- write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
- write32(mmio + 0x0007019c, 0x00000000);
- write32(mmio + 0x0007119c, 0x00000000);
- write32(mmio + 0x000fc008, 0x2c010000);
- write32(mmio + 0x000fc020, 0x2c010000);
- write32(mmio + 0x000fc038, 0x2c010000);
- write32(mmio + 0x000fc050, 0x2c010000);
- write32(mmio + 0x000fc408, 0x2c010000);
- write32(mmio + 0x000fc420, 0x2c010000);
- write32(mmio + 0x000fc438, 0x2c010000);
- write32(mmio + 0x000fc450, 0x2c010000);
+ write32((u32 *)(mmio + 0x00070080), 0x00000000);
+ write32((u32 *)(mmio + DSPCNTR(0)), 0x00000000);
+ write32((u32 *)(mmio + 0x00071180), 0x00000000);
+ write32((u32 *)(mmio + CPU_VGACNTRL), 0x0000298e | VGA_DISP_DISABLE);
+ write32((u32 *)(mmio + 0x0007019c), 0x00000000);
+ write32((u32 *)(mmio + 0x0007119c), 0x00000000);
+ write32((u32 *)(mmio + 0x000fc008), 0x2c010000);
+ write32((u32 *)(mmio + 0x000fc020), 0x2c010000);
+ write32((u32 *)(mmio + 0x000fc038), 0x2c010000);
+ write32((u32 *)(mmio + 0x000fc050), 0x2c010000);
+ write32((u32 *)(mmio + 0x000fc408), 0x2c010000);
+ write32((u32 *)(mmio + 0x000fc420), 0x2c010000);
+ write32((u32 *)(mmio + 0x000fc438), 0x2c010000);
+ write32((u32 *)(mmio + 0x000fc450), 0x2c010000);
vga_gr_write(0x18, 0);
- write32(mmio + 0x00042004, 0x02000000);
- write32(mmio + 0x000fd034, 0x8421ffe0);
+ write32((u32 *)(mmio + 0x00042004), 0x02000000);
+ write32((u32 *)(mmio + 0x000fd034), 0x8421ffe0);
/* Setup GTT. */
for (i = 0; i < 0x2000; i++)
@@ -742,12 +742,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32((u32 *)(mmio + DSPCNTR(0)), DISPPLANE_BGRX888);
+ write32((u32 *)(mmio + DSPADDR(0)), 0);
+ write32((u32 *)(mmio + DSPSTRIDE(0)), edid.bytes_per_line);
+ write32((u32 *)(mmio + DSPSURF(0)), 0);
for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ write32((u32 *)(mmio + LGC_PALETTE(0) + 4 * i), i * 0x010101);
#endif
/* Find suitable divisors. */
@@ -820,167 +820,141 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
- write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
- write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock
- ? 0x1002 : 0x400));
+ write32((u32 *)(mmio + PCH_LVDS),
+ (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED);
+ write32((u32 *)(mmio + BLC_PWM_CPU_CTL2), (1 << 31));
+ write32((u32 *)(mmio + PCH_DREF_CONTROL),
+ (info->gfx.use_spread_spectrum_clock ? 0x1002 : 0x400));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + _PCH_FP0(0),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32((u32 *)(mmio + PCH_PP_CONTROL),
+ PANEL_UNLOCK_REGS | (read32((u32 *)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK));
+ write32((u32 *)(mmio + _PCH_FP0(0)),
+ ((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2);
+ write32((u32 *)(mmio + _PCH_DPLL(0)),
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)));
mdelay(1);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32((u32 *)(mmio + _PCH_DPLL(0)),
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */
- write32(mmio + PCH_PP_CONTROL,
- (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
- write32(mmio + PF_WIN_POS(0), 0);
+ write32((u32 *)(mmio + PCH_PP_CONTROL),
+ (read32((u32 *)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK));
+
+ write32((u32 *)(mmio + PCH_LVDS),
+ (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED);
+
+ write32((u32 *)(mmio + HTOTAL(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive - 1));
+ write32((u32 *)(mmio + HBLANK(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1));
+ write32((u32 *)(mmio + HSYNC(0)),
+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1));
+
+ write32((u32 *)(mmio + VTOTAL(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1));
+ write32((u32 *)(mmio + VBLANK(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1));
+ write32((u32 *)(mmio + VSYNC(0)),
+ (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1));
+
+ write32((u32 *)(mmio + PIPECONF(0)), PIPECONF_DISABLE);
+
+ write32((u32 *)(mmio + PF_WIN_POS(0)), 0);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
+ write32((u32 *)(mmio + PIPESRC(0)),
+ ((hactive - 1) << 16) | (vactive - 1));
+ write32((u32 *)(mmio + PF_CTL(0)), 0);
+ write32((u32 *)(mmio + PF_WIN_SZ(0)), 0);
#else
- write32(mmio + PIPESRC(0), (639 << 16) | 399);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32((u32 *)(mmio + PIPESRC(0)), (639 << 16) | 399);
+ write32((u32 *)(mmio + PF_CTL(0)), PF_ENABLE | PF_FILTER_MED_3x3);
+ write32((u32 *)(mmio + PF_WIN_SZ(0)), vactive | (hactive << 16));
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32((u32 *)(mmio + PIPE_DATA_M1(0)), 0x7e000000 | data_m1);
+ write32((u32 *)(mmio + PIPE_DATA_N1(0)), data_n1);
+ write32((u32 *)(mmio + PIPE_LINK_M1(0)), link_m1);
+ write32((u32 *)(mmio + PIPE_LINK_N1(0)), link_n1);
- write32(mmio + 0x000f000c, 0x00002040);
+ write32((u32 *)(mmio + 0x000f000c), 0x00002040);
mdelay(1);
- write32(mmio + 0x000f000c, 0x00002050);
- write32(mmio + 0x00060100, 0x00044000);
+ write32((u32 *)(mmio + 0x000f000c), 0x00002050);
+ write32((u32 *)(mmio + 0x00060100), 0x00044000);
mdelay(1);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
- write32(mmio + 0x000f0008, 0x00000040);
- write32(mmio + 0x000f000c, 0x00022050);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32((u32 *)(mmio + PIPECONF(0)), PIPECONF_BPP_6);
+ write32((u32 *)(mmio + 0x000f0008), 0x00000040);
+ write32((u32 *)(mmio + 0x000f000c), 0x00022050);
+ write32((u32 *)(mmio + PIPECONF(0)),
+ PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32((u32 *)(mmio + PIPECONF(0)),
+ PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
+ write32((u32 *)(mmio + CPU_VGACNTRL), 0x20298e | VGA_DISP_DISABLE);
#else
- write32(mmio + CPU_VGACNTRL, 0x20298e);
+ write32((u32 *)(mmio + CPU_VGACNTRL), 0x20298e);
#endif
train_link(mmio);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32((u32 *)(mmio + DSPCNTR(0)),
+ DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
#endif
- write32(mmio + TRANS_HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + TRANS_VTOTAL(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + 0x00060100, 0xb01c4000);
- write32(mmio + 0x000f000c, 0xb01a2050);
+ write32((u32 *)(mmio + TRANS_HTOTAL(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive - 1));
+ write32((u32 *)(mmio + TRANS_HBLANK(0)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1));
+ write32((u32 *)(mmio + TRANS_HSYNC(0)),
+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1));
+
+ write32((u32 *)(mmio + TRANS_VTOTAL(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1));
+ write32((u32 *)(mmio + TRANS_VBLANK(0)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1));
+ write32((u32 *)(mmio + TRANS_VSYNC(0)),
+ (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1));
+
+ write32((u32 *)(mmio + 0x00060100), 0xb01c4000);
+ write32((u32 *)(mmio + 0x000f000c), 0xb01a2050);
mdelay(1);
- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32((u32 *)(mmio + TRANSCONF(0)), TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
+
+ | TRANS_STATE_MASK
#endif
- );
- write32(mmio + PCH_LVDS,
- LVDS_PORT_ENABLE
- | (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+);
+ write32((u32 *)(mmio + PCH_LVDS),
+ LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED);
+
+ write32((u32 *)(mmio + PCH_PP_CONTROL),
+ PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ write32((u32 *)(mmio + PCH_PP_CONTROL),
+ PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32((u32 *)(mmio + PCH_PP_CONTROL),
+ PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET);
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
- reg32 = read32(mmio + PCH_PP_STATUS);
+ reg32 = read32((u32 *)(mmio + PCH_PP_STATUS));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32((u32 *)(mmio + PCH_PP_CONTROL),
+ PANEL_POWER_ON | PANEL_POWER_RESET);
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32((u32 *)(mmio + DEIIR), 0xffffffff);
+ write32((u32 *)(mmio + SDEIIR), 0xffffffff);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 9ca98d5..d88e897 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -319,36 +319,36 @@ static int rw_test(int rank)
int ok = 0xff;
int i;
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32((u32 *)((rank << 28) | (i << 2)), 0);
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32((u32 *)((rank << 28) | (i << 2))));
sfence();
for (i = 0; i < 32; i++) {
u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0);
- write32((rank << 28) | (i << 3), pat);
- write32((rank << 28) | (i << 3) | 4, pat);
+ write32((u32 *)((rank << 28) | (i << 3)), pat);
+ write32((u32 *)((rank << 28) | (i << 3) | 4), pat);
}
sfence();
for (i = 0; i < 32; i++) {
u8 pat = (((mask >> i) & 1) ? 0xff : 0);
int j;
u32 val;
- gav(val = read32((rank << 28) | (i << 3)));
+ gav(val = read32((u32 *)((rank << 28) | (i << 3))));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(1 << j);
- gav(val = read32((rank << 28) | (i << 3) | 4));
+ gav(val = read32((u32 *)((rank << 28) | (i << 3) | 4)));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(16 << j);
}
sfence();
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32((u32 *)((rank << 28) | (i << 2)), 0);
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32((u32 *)((rank << 28) | (i << 2))));
return ok;
}
@@ -1077,12 +1077,12 @@ static void jedec_read(struct raminfo *info,
(value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8)
<< 1);
- read32((value << 3) | (total_rank << 28));
+ read32((u32 *)((value << 3) | (total_rank << 28)));
write_mchbar8(0x271, (read_mchbar8(0x271) & 0xC3) | 2);
write_mchbar8(0x671, (read_mchbar8(0x671) & 0xC3) | 2);
- read32(total_rank << 28);
+ read32((u32 *)(total_rank << 28));
}
enum {
@@ -1567,7 +1567,7 @@ static void collect_system_info(struct raminfo *info)
unsigned channel;
/* Wait for some bit, maybe TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((u8 *)0xfed40000) & (1 << 7))) ;
if (!info->heci_bar)
gav(info->heci_bar =
@@ -1751,9 +1751,9 @@ static const struct ram_training *get_cached_training(void)
/* FIXME: add timeout. */
static void wait_heci_ready(void)
{
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ; // = 0x8000000c
- write32((DEFAULT_HECIBAR | 0x4),
- (read32(DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc);
+ while (!(read32((u32 *)(DEFAULT_HECIBAR | 0xc)) & 8)) ; // = 0x8000000c
+ write32((u32 *)(DEFAULT_HECIBAR | 0x4),
+ (read32((u32 *)(DEFAULT_HECIBAR | 0x4)) & ~0x10) | 0xc);
}
/* FIXME: add timeout. */
@@ -1764,10 +1764,10 @@ static void wait_heci_cb_avail(int len)
u32 raw;
} csr;
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ;
+ while (!(read32((u32 *)(DEFAULT_HECIBAR | 0xc)) & 8)) ;
do
- csr.raw = read32(DEFAULT_HECIBAR | 0x4);
+ csr.raw = read32((u32 *)(DEFAULT_HECIBAR | 0x4));
while (len >
csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
csr.csr.buffer_read_ptr));
@@ -1781,12 +1781,14 @@ static void send_heci_packet(struct mei_header *head, u32 * payload)
wait_heci_cb_avail(len + 1);
/* FIXME: handle leftovers correctly. */
- write32(DEFAULT_HECIBAR | 0, *(u32 *) head);
+ write32((u32 *)(DEFAULT_HECIBAR | 0), *(u32 *)head);
for (i = 0; i < len - 1; i++)
- write32(DEFAULT_HECIBAR | 0, payload[i]);
+ write32((u32 *)(DEFAULT_HECIBAR | 0), payload[i]);
- write32(DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1));
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 0x4);
+ write32((u32 *)(DEFAULT_HECIBAR | 0),
+ payload[i] & ((1 << (8 * len)) - 1));
+ write32((u32 *)(DEFAULT_HECIBAR | 0x4),
+ read32((u32 *)(DEFAULT_HECIBAR | 0x4)) | 0x4);
}
static void
@@ -1796,7 +1798,7 @@ send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)
int maxlen;
wait_heci_ready();
- maxlen = (read32(DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4;
+ maxlen = (read32((u32 *)(DEFAULT_HECIBAR | 0x4)) >> 24) * 4 - 4;
while (len) {
int cur = len;
@@ -1826,19 +1828,20 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
} csr;
int i = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32((u32 *)(DEFAULT_HECIBAR | 0x4),
+ read32((u32 *)(DEFAULT_HECIBAR | 0x4)) | 2);
do {
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32((u32 *)(DEFAULT_HECIBAR | 0xc));
#if !REAL
if (i++ > 346)
return -1;
#endif
}
while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
- *(u32 *) head = read32(DEFAULT_HECIBAR | 0x8);
+ *(u32 *) head = read32((u32 *)(DEFAULT_HECIBAR | 0x8));
if (!head->length) {
- write32(DEFAULT_HECIBAR | 0x4,
- read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32((u32 *)(DEFAULT_HECIBAR | 0x4),
+ read32((u32 *)(DEFAULT_HECIBAR | 0x4)) | 2);
*packet_size = 0;
return 0;
}
@@ -1849,16 +1852,17 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
}
do
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32((u32 *)(DEFAULT_HECIBAR | 0xc));
while ((head->length + 3) >> 2 >
csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
for (i = 0; i < (head->length + 3) >> 2; i++)
- packet[i++] = read32(DEFAULT_HECIBAR | 0x8);
+ packet[i++] = read32((u32 *)(DEFAULT_HECIBAR | 0x8));
*packet_size = head->length;
if (!csr.csr.ready)
*packet_size = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 4);
+ write32((u32 *)(DEFAULT_HECIBAR | 0x4),
+ read32((u32 *)(DEFAULT_HECIBAR | 0x4)) | 4);
return 0;
}
@@ -1946,27 +1950,27 @@ static void setup_heci_uma(struct raminfo *info)
pcie_read_config32(NORTHBRIDGE, DMIBAR);
if (info->memory_reserved_for_heci_mb) {
- write32(DEFAULT_DMIBAR | 0x14,
- read32(DEFAULT_DMIBAR | 0x14) & ~0x80);
- write32(DEFAULT_RCBA | 0x14,
- read32(DEFAULT_RCBA | 0x14) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x20,
- read32(DEFAULT_DMIBAR | 0x20) & ~0x80);
- write32(DEFAULT_RCBA | 0x20,
- read32(DEFAULT_RCBA | 0x20) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x2c,
- read32(DEFAULT_DMIBAR | 0x2c) & ~0x80);
- write32(DEFAULT_RCBA | 0x30,
- read32(DEFAULT_RCBA | 0x30) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x38,
- read32(DEFAULT_DMIBAR | 0x38) & ~0x80);
- write32(DEFAULT_RCBA | 0x40,
- read32(DEFAULT_RCBA | 0x40) & ~0x80);
-
- write32(DEFAULT_RCBA | 0x40, 0x87000080); // OK
- write32(DEFAULT_DMIBAR | 0x38, 0x87000080); // OK
- while (read16(DEFAULT_RCBA | 0x46) & 2
- && read16(DEFAULT_DMIBAR | 0x3e) & 2) ;
+ write32((u32 *)(DEFAULT_DMIBAR | 0x14),
+ read32((u32 *)(DEFAULT_DMIBAR | 0x14)) & ~0x80);
+ write32((u32 *)(DEFAULT_RCBA | 0x14),
+ read32((u32 *)(DEFAULT_RCBA | 0x14)) & ~0x80);
+ write32((u32 *)(DEFAULT_DMIBAR | 0x20),
+ read32((u32 *)(DEFAULT_DMIBAR | 0x20)) & ~0x80);
+ write32((u32 *)(DEFAULT_RCBA | 0x20),
+ read32((u32 *)(DEFAULT_RCBA | 0x20)) & ~0x80);
+ write32((u32 *)(DEFAULT_DMIBAR | 0x2c),
+ read32((u32 *)(DEFAULT_DMIBAR | 0x2c)) & ~0x80);
+ write32((u32 *)(DEFAULT_RCBA | 0x30),
+ read32((u32 *)(DEFAULT_RCBA | 0x30)) & ~0x80);
+ write32((u32 *)(DEFAULT_DMIBAR | 0x38),
+ read32((u32 *)(DEFAULT_DMIBAR | 0x38)) & ~0x80);
+ write32((u32 *)(DEFAULT_RCBA | 0x40),
+ read32((u32 *)(DEFAULT_RCBA | 0x40)) & ~0x80);
+
+ write32((u32 *)(DEFAULT_RCBA | 0x40), 0x87000080); // OK
+ write32((u32 *)(DEFAULT_DMIBAR | 0x38), 0x87000080); // OK
+ while (read16((u16 *)(DEFAULT_RCBA | 0x46)) & 2
+ && read16((u16 *)(DEFAULT_DMIBAR | 0x3e)) & 2) ;
}
write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
@@ -2101,10 +2105,13 @@ static void write_testing(struct raminfo *info, int totalrank, int flip)
base = totalrank << 28;
for (offset = 0; offset < 9 * 480; offset += 2) {
- write32(base + offset * 8, get_etalon2(flip, offset));
- write32(base + offset * 8 + 4, get_etalon2(flip, offset));
- write32(base + offset * 8 + 8, get_etalon2(flip, offset + 1));
- write32(base + offset * 8 + 12, get_etalon2(flip, offset + 1));
+ write32((u32 *)(base + offset * 8), get_etalon2(flip, offset));
+ write32((u32 *)(base + offset * 8 + 4),
+ get_etalon2(flip, offset));
+ write32((u32 *)(base + offset * 8 + 8),
+ get_etalon2(flip, offset + 1));
+ write32((u32 *)(base + offset * 8 + 12),
+ get_etalon2(flip, offset + 1));
nwrites += 4;
if (nwrites >= 320) {
clear_errors();
@@ -2217,8 +2224,8 @@ write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
{
int i;
for (i = 0; i < 2048; i++)
- write32((totalrank << 28) | (region << 25) | (block << 16) |
- (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
+ write32((u32 *)((totalrank << 28) | (region << 25) | (block << 16) | (i << 2)),
+ get_etalon(flip, (block << 16) | (i << 2)));
}
static u8
@@ -2243,7 +2250,7 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
| (comp3 << 12) | (comp2 << 6) | (comp1 <<
2);
failxor[comp1 & 1] |=
- read32(addr) ^ get_etalon(flip, addr);
+ read32((u32 *)addr) ^ get_etalon(flip, addr);
}
for (i = 0; i < 8; i++)
if ((0xff << (8 * (i % 4))) & failxor[i / 4])
@@ -3779,13 +3786,14 @@ static void restore_274265(struct raminfo *info)
#if REAL
static void dmi_setup(void)
{
- gav(read8(DEFAULT_DMIBAR | 0x254));
- write8(DEFAULT_DMIBAR | 0x254, 0x1);
- write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+ gav(read8((u8 *)(DEFAULT_DMIBAR | 0x254)));
+ write8((u8 *)(DEFAULT_DMIBAR | 0x254), 0x1);
+ write16((u16 *)(DEFAULT_DMIBAR | 0x1b8), 0x18f2);
read_mchbar16(0x48);
write_mchbar16(0x48, 0x2);
- write32(DEFAULT_DMIBAR | 0xd68, read32(DEFAULT_DMIBAR | 0xd68) | 0x08000000);
+ write32((u32 *)(DEFAULT_DMIBAR | 0xd68),
+ read32((u32 *)(DEFAULT_DMIBAR | 0xd68)) | 0x08000000);
outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
DEFAULT_GPIOBASE | 0x38);
@@ -3847,18 +3855,18 @@ void chipset_init(const int s3resume)
write_mchbar32(0x2c44, 0x1053687);
pcie_read_config8(GMA, 0x62); // = 0x2
pcie_write_config8(GMA, 0x62, 0x2);
- read8(DEFAULT_RCBA | 0x2318);
- write8(DEFAULT_RCBA | 0x2318, 0x47);
- read8(DEFAULT_RCBA | 0x2320);
- write8(DEFAULT_RCBA | 0x2320, 0xfc);
+ read8((u8 *)(DEFAULT_RCBA | 0x2318));
+ write8((u8 *)(DEFAULT_RCBA | 0x2318), 0x47);
+ read8((u8 *)(DEFAULT_RCBA | 0x2320));
+ write8((u8 *)(DEFAULT_RCBA | 0x2320), 0xfc);
}
read_mchbar32(0x30);
write_mchbar32(0x30, 0x40);
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
- gav(read32(DEFAULT_RCBA | 0x3428));
- write32(DEFAULT_RCBA | 0x3428, 0x1d);
+ gav(read32((u32 *)(DEFAULT_RCBA | 0x3428)));
+ write32((u32 *)(DEFAULT_RCBA | 0x3428), 0x1d);
}
void raminit(const int s3resume, const u8 *spd_addrmap)
@@ -4818,17 +4826,17 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0xd40, IOMMU_BASE1 | 1);
write_mchbar32(0xdc0, IOMMU_BASE4 | 1);
- write32(IOMMU_BASE1 | 0xffc, 0x80000000);
- write32(IOMMU_BASE2 | 0xffc, 0xc0000000);
- write32(IOMMU_BASE4 | 0xffc, 0x80000000);
+ write32((u32 *)(IOMMU_BASE1 | 0xffc), 0x80000000);
+ write32((u32 *)(IOMMU_BASE2 | 0xffc), 0xc0000000);
+ write32((u32 *)(IOMMU_BASE4 | 0xffc), 0x80000000);
#else
{
u32 eax;
- eax = read32(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK
- eax = read32(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK
+ eax = read32((u32 *)(0xffc + (read_mchbar32(0xd00) & ~1))) | 0x08000000; // = 0xe911714b// OK
+ write32((u32 *)(0xffc + (read_mchbar32(0xd00) & ~1)), eax); // OK
+ eax = read32((u32 *)(0xffc + (read_mchbar32(0xdc0) & ~1))) | 0x40000000; // = 0xe911714b// OK
+ write32((u32 *)(0xffc + (read_mchbar32(0xdc0) & ~1)), eax); // OK
}
#endif
@@ -4875,9 +4883,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
}
u32 reg1c;
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- reg1c = read32(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
+ reg1c = read32((u32 *)(DEFAULT_EPBAR | 0x01c)); // = 0x8001 // OK
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- write32(DEFAULT_EPBAR | 0x01c, reg1c); // OK
+ write32((u32 *)(DEFAULT_EPBAR | 0x01c), reg1c); // OK
read_mchbar8(0xe08); // = 0x0
pcie_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 7a48696..71eb9df 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -121,7 +121,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 247c723..4af62dc 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -280,12 +280,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32((void *)(uintptr_t)(gtt_res->base + reg));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32((void *)(uintptr_t)(gtt_res->base + reg), data);
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -588,10 +588,10 @@ static void gma_func0_init(struct device *dev)
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* This should probably run before post VBIOS init. */
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
- u32 iobase, mmiobase, physbase, graphics_base;
+ u32 iobase, *mmiobase, physbase, graphics_base;
struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
iobase = dev->resource_list[2].base;
- mmiobase = dev->resource_list[0].base;
+ mmiobase = (u32 *)(uintptr_t)dev->resource_list[0].base;
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index 3a73e08..c729582 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -117,4 +117,4 @@ typedef struct {
struct i915_gpu_controller_info;
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 pio, u32 mmio, u32 lfb);
+ u32 physbase, u16 pio, u32 *mmio, u32 lfb);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index e3e1f4b..66f6678 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -36,153 +36,154 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void link_train(u32 mmio)
+static void link_train(u32 *mmio)
{
- write32(mmio+0xf000c,0x40);
- write32(mmio+0x60100,0x40000);
- write32(mmio+0xf0018,0x8ff);
- write32(mmio+0xf1018,0x8ff);
- write32(mmio+0xf000c,0x2040);
+ write32((mmio + (0xf000c / sizeof(u32))),0x40);
+ write32((mmio + (0x60100 / sizeof(u32))),0x40000);
+ write32((mmio + (0xf0018 / sizeof(u32))),0x8ff);
+ write32((mmio + (0xf1018 / sizeof(u32))),0x8ff);
+ write32((mmio + (0xf000c / sizeof(u32))),0x2040);
mdelay(1);
- write32(mmio+0xf000c,0x2050);
- write32(mmio+0x60100,0x44000);
+ write32((mmio + (0xf000c / sizeof(u32))),0x2050);
+ write32((mmio + (0x60100 / sizeof(u32))),0x44000);
mdelay(1);
- write32(mmio+0x70008,0x40);
- write32(mmio+0xe0300,0x60000418);
- write32(mmio+0xf000c,0x22050);
- write32(mmio+0x70008,0x50);
- write32(mmio+0x70008,0x80000050);
+ write32((mmio + (0x70008 / sizeof(u32))),0x40);
+ write32((mmio + (0xe0300 / sizeof(u32))),0x60000418);
+ write32((mmio + (0xf000c / sizeof(u32))),0x22050);
+ write32((mmio + (0x70008 / sizeof(u32))),0x50);
+ write32((mmio + (0x70008 / sizeof(u32))),0x80000050);
}
-static void link_normal_operation(u32 mmio)
+static void link_normal_operation(u32 *mmio)
{
- write32(mmio + FDI_TX_CTL(0), 0x80044f02);
- write32(mmio + FDI_RX_CTL(0),
+ write32((mmio + (FDI_TX_CTL(0) / sizeof(u32))), 0x80044f02);
+ write32((mmio + (FDI_RX_CTL(0) / sizeof(u32))),
FDI_RX_ENABLE | FDI_6BPC
| 0x2f50);
}
-static void enable_port(u32 mmio)
+static void enable_port(u32 *mmio)
{
- write32(mmio + 0xec008, 0x2c010000);
- write32(mmio + 0xec020, 0x2c010000);
- write32(mmio + 0xec038, 0x2c010000);
- write32(mmio + 0xec050, 0x2c010000);
- write32(mmio + 0xec408, 0x2c010000);
- write32(mmio + 0xec420, 0x2c010000);
- write32(mmio + 0xec438, 0x2c010000);
- write32(mmio + 0xec450, 0x2c010000);
- write32(mmio + 0xf0010, 0x200090);
- write32(mmio + 0xf1010, 0x200090);
- write32(mmio + 0xf2010, 0x200090);
- write32(mmio + 0xfd034, 0x8420000);
- write32(mmio + 0x45010, 0x3);
- write32(mmio + 0xf0060, 0x10);
- write32(mmio + 0xf1060, 0x10);
- write32(mmio + 0xf2060, 0x10);
- write32(mmio + 0x9840, 0x0);
- write32(mmio + 0x42000, 0xa0000000);
- write32(mmio + 0xe4f00, 0x100030c);
- write32(mmio + 0xe4f04, 0xb8230c);
- write32(mmio + 0xe4f08, 0x6f8930c);
- write32(mmio + 0xe4f0c, 0x5f8e38e);
- write32(mmio + 0xe4f10, 0xb8030c);
- write32(mmio + 0xe4f14, 0xb78830c);
- write32(mmio + 0xe4f18, 0x9f8d3cf);
- write32(mmio + 0xe4f1c, 0x1e8030c);
- write32(mmio + 0xe4f20, 0x9f863cf);
- write32(mmio + 0xe4f24, 0xff803cf);
- read32(mmio + 0xe4100);
- write32(mmio + 0xc4030, 0x10);
- write32(mmio + 0xe4110, 0x8004003e);
- write32(mmio + 0xe4114, 0x80060000);
- write32(mmio + 0xe4118, 0x1000000);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x8054003e);
- read32(mmio + 0xe4110);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
+ write32((mmio + (0xec008 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xec020 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xec038 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xec050 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xec408 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xec420 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xec438 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xec450 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0xf0010 / sizeof(u32))), 0x200090);
+ write32((mmio + (0xf1010 / sizeof(u32))), 0x200090);
+ write32((mmio + (0xf2010 / sizeof(u32))), 0x200090);
+ write32((mmio + (0xfd034 / sizeof(u32))), 0x8420000);
+ write32((mmio + (0x45010 / sizeof(u32))), 0x3);
+ write32((mmio + (0xf0060 / sizeof(u32))), 0x10);
+ write32((mmio + (0xf1060 / sizeof(u32))), 0x10);
+ write32((mmio + (0xf2060 / sizeof(u32))), 0x10);
+ write32((mmio + (0x9840 / sizeof(u32))), 0x0);
+ write32((mmio + (0x42000 / sizeof(u32))), 0xa0000000);
+ write32((mmio + (0xe4f00 / sizeof(u32))), 0x100030c);
+ write32((mmio + (0xe4f04 / sizeof(u32))), 0xb8230c);
+ write32((mmio + (0xe4f08 / sizeof(u32))), 0x6f8930c);
+ write32((mmio + (0xe4f0c / sizeof(u32))), 0x5f8e38e);
+ write32((mmio + (0xe4f10 / sizeof(u32))), 0xb8030c);
+ write32((mmio + (0xe4f14 / sizeof(u32))), 0xb78830c);
+ write32((mmio + (0xe4f18 / sizeof(u32))), 0x9f8d3cf);
+ write32((mmio + (0xe4f1c / sizeof(u32))), 0x1e8030c);
+ write32((mmio + (0xe4f20 / sizeof(u32))), 0x9f863cf);
+ write32((mmio + (0xe4f24 / sizeof(u32))), 0xff803cf);
+ read32((mmio + (0xe4100 / sizeof(u32))));
+ write32((mmio + (0xc4030 / sizeof(u32))), 0x10);
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x8004003e);
+ write32((mmio + (0xe4114 / sizeof(u32))), 0x80060000);
+ write32((mmio + (0xe4118 / sizeof(u32))), 0x1000000);
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x5344003e);
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x8054003e);
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x5344003e);
mdelay(1);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x8054003e);
- read32(mmio + 0xe4110);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x8054003e);
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x5344003e);
mdelay(1);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x8054003e);
- read32(mmio + 0xe4110);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x8054003e);
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ read32((mmio + (0xe4110 / sizeof(u32))));
+ write32((mmio + (0xe4110 / sizeof(u32))), 0x5344003e);
mdelay(1);
- read32(mmio + 0xc4000);
- read32(mmio + 0xe1140);
- write32(mmio + 0xc4030, 0x10);
- read32(mmio + 0xc4000);
- write32(mmio + 0xe4f00, 0x100030c);
- write32(mmio + 0xe4f04, 0xb8230c);
- write32(mmio + 0xe4f08, 0x6f8930c);
- write32(mmio + 0xe4f0c, 0x5f8e38e);
- write32(mmio + 0xe4f10, 0xb8030c);
- write32(mmio + 0xe4f14, 0xb78830c);
- write32(mmio + 0xe4f18, 0x9f8d3cf);
- write32(mmio + 0xe4f1c, 0x1e8030c);
- write32(mmio + 0xe4f20, 0x9f863cf);
- write32(mmio + 0xe4f24, 0xff803cf);
- read32(mmio + 0xe4200);
- write32(mmio + 0xc4030, 0x1010);
- write32(mmio + 0xe4210, 0x8004003e);
- write32(mmio + 0xe4214, 0x80060000);
- write32(mmio + 0xe4218, 0x1002000);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x8054003e);
- read32(mmio + 0xe4210);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
+ read32((mmio + (0xc4000 / sizeof(u32))));
+ read32((mmio + (0xe1140 / sizeof(u32))));
+ write32((mmio + (0xc4030 / sizeof(u32))), 0x10);
+ read32((mmio + (0xc4000 / sizeof(u32))));
+ write32((mmio + (0xe4f00 / sizeof(u32))), 0x100030c);
+ write32((mmio + (0xe4f04 / sizeof(u32))), 0xb8230c);
+ write32((mmio + (0xe4f08 / sizeof(u32))), 0x6f8930c);
+ write32((mmio + (0xe4f0c / sizeof(u32))), 0x5f8e38e);
+ write32((mmio + (0xe4f10 / sizeof(u32))), 0xb8030c);
+ write32((mmio + (0xe4f14 / sizeof(u32))), 0xb78830c);
+ write32((mmio + (0xe4f18 / sizeof(u32))), 0x9f8d3cf);
+ write32((mmio + (0xe4f1c / sizeof(u32))), 0x1e8030c);
+ write32((mmio + (0xe4f20 / sizeof(u32))), 0x9f863cf);
+ write32((mmio + (0xe4f24 / sizeof(u32))), 0xff803cf);
+ read32((mmio + (0xe4200 / sizeof(u32))));
+ write32((mmio + (0xc4030 / sizeof(u32))), 0x1010);
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x8004003e);
+ write32((mmio + (0xe4214 / sizeof(u32))), 0x80060000);
+ write32((mmio + (0xe4218 / sizeof(u32))), 0x1002000);
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x5344003e);
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x8054003e);
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x5344003e);
mdelay(1);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x8054003e);
- read32(mmio + 0xe4210);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x8054003e);
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x5344003e);
mdelay(1);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x8054003e);
- read32(mmio + 0xe4210);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x8054003e);
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ read32((mmio + (0xe4210 / sizeof(u32))));
+ write32((mmio + (0xe4210 / sizeof(u32))), 0x5344003e);
mdelay(1);
- read32(mmio + 0xc4000);
+ read32((mmio + (0xc4000 / sizeof(u32))));
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u32 mmio, u32 lfb)
+ u32 physbase, u16 piobase, u32 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
struct edid edid;
- write32(mmio + 0x00070080, 0x00000000);
- write32(mmio + DSPCNTR(0), 0x00000000);
- write32(mmio + 0x00071180, 0x00000000);
- write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
- write32(mmio + 0x0007019c, 0x00000000);
- write32(mmio + 0x0007119c, 0x00000000);
- write32(mmio + 0x000fc008, 0x2c010000);
- write32(mmio + 0x000fc020, 0x2c010000);
- write32(mmio + 0x000fc038, 0x2c010000);
- write32(mmio + 0x000fc050, 0x2c010000);
- write32(mmio + 0x000fc408, 0x2c010000);
- write32(mmio + 0x000fc420, 0x2c010000);
- write32(mmio + 0x000fc438, 0x2c010000);
- write32(mmio + 0x000fc450, 0x2c010000);
+ write32((mmio + (0x00070080 / sizeof(u32))), 0x00000000);
+ write32((mmio + (DSPCNTR(0) / sizeof(u32))), 0x00000000);
+ write32((mmio + (0x00071180 / sizeof(u32))), 0x00000000);
+ write32((mmio + (CPU_VGACNTRL / sizeof(u32))),
+ 0x0000298e | VGA_DISP_DISABLE);
+ write32((mmio + (0x0007019c / sizeof(u32))), 0x00000000);
+ write32((mmio + (0x0007119c / sizeof(u32))), 0x00000000);
+ write32((mmio + (0x000fc008 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0x000fc020 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0x000fc038 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0x000fc050 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0x000fc408 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0x000fc420 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0x000fc438 / sizeof(u32))), 0x2c010000);
+ write32((mmio + (0x000fc450 / sizeof(u32))), 0x2c010000);
vga_gr_write(0x18, 0);
- write32(mmio + 0x00042004, 0x02000000);
- write32(mmio + 0x000fd034, 0x8421ffe0);
+ write32((mmio + (0x00042004 / sizeof(u32))), 0x02000000);
+ write32((mmio + (0x000fd034 / sizeof(u32))), 0x8421ffe0);
/* Setup GTT. */
for (i = 0; i < 0x2000; i++)
@@ -205,7 +206,8 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
enable_port(mmio);
- intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
+ intel_gmbus_read_edid((mmio + (PCH_GMBUS0 / sizeof(u32))), 3, 0x50,
+ edid_data, 128);
decode_edid(edid_data,
sizeof(edid_data), &edid);
@@ -256,12 +258,13 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32((mmio + (DSPCNTR(0) / sizeof(u32))), DISPPLANE_BGRX888);
+ write32((mmio + (DSPADDR(0) / sizeof(u32))), 0);
+ write32((mmio + (DSPSTRIDE(0) / sizeof(u32))), edid.bytes_per_line);
+ write32((mmio + (DSPSURF(0) / sizeof(u32))), 0);
for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ write32((mmio + (LGC_PALETTE(0) / sizeof(u32))) + i,
+ i * 0x010101);
#endif
/* Find suitable divisors. */
@@ -341,22 +344,22 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + PCH_LVDS,
+ write32((mmio + (PCH_LVDS / sizeof(u32))),
(hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
- write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
- write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
+ write32((mmio + (BLC_PWM_CPU_CTL2 / sizeof(u32))), (1 << 31));
+ write32((mmio + (PCH_DREF_CONTROL / sizeof(u32))), (info->use_spread_spectrum_clock
? 0x1002 : 0x400));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + _PCH_FP0(0),
+ write32((mmio + (PCH_PP_CONTROL / sizeof(u32))), PANEL_UNLOCK_REGS
+ | (read32((mmio + (PCH_PP_CONTROL / sizeof(u32)))) & ~PANEL_UNLOCK_MASK));
+ write32((mmio + (_PCH_FP0(0) / sizeof(u32))),
((pixel_n - 2) << 16)
| ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + _PCH_DPLL(0),
+ write32((mmio + (_PCH_DPLL(0) / sizeof(u32))),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
@@ -365,10 +368,10 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
| (0x1 << (pixel_p1 - 1)));
mdelay(1);
- write32(mmio + 0xc7000, 0x8);
+ write32((mmio + (0xc7000 / sizeof(u32))), 0x8);
mdelay(1);
- write32(mmio + _PCH_DPLL(0),
+ write32((mmio + (_PCH_DPLL(0) / sizeof(u32))),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
@@ -376,106 +379,111 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */
- write32(mmio + PCH_PP_CONTROL,
- (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
+ write32((mmio + (PCH_PP_CONTROL / sizeof(u32))),
+ (read32((mmio + (PCH_PP_CONTROL / sizeof(u32)))) & ~PANEL_UNLOCK_MASK));
- write32(mmio + PCH_LVDS,
+ write32((mmio + (PCH_LVDS / sizeof(u32))),
(hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
- write32(mmio + HTOTAL(0),
+ write32((mmio + (HTOTAL(0) / sizeof(u32))),
((hactive + right_border + hblank - 1) << 16)
| (hactive - 1));
- write32(mmio + HBLANK(0),
+ write32((mmio + (HBLANK(0) / sizeof(u32))),
((hactive + right_border + hblank - 1) << 16)
| (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
+ write32((mmio + (HSYNC(0) / sizeof(u32))),
((hactive + right_border + hfront_porch + hsync - 1) << 16)
| (hactive + right_border + hfront_porch - 1));
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
+ write32((mmio + (VTOTAL(0) / sizeof(u32))), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
+ write32((mmio + (VBLANK(0) / sizeof(u32))), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
+ write32((mmio + (VSYNC(0) / sizeof(u32))),
(vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
+ | (vactive + bottom_border + vfront_porch - 1));
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
+ write32((mmio + (PIPECONF(0) / sizeof(u32))), PIPECONF_DISABLE);
- write32(mmio + 0xf0008, 0);
+ write32((mmio + (0xf0008 / sizeof(u32))), 0);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
- write32(mmio + PF_WIN_POS(0), 0);
+ write32((mmio + (PIPESRC(0) / sizeof(u32))),
+ ((hactive - 1) << 16) | (vactive - 1));
+ write32((mmio + (PF_CTL(0) / sizeof(u32))),0);
+ write32((mmio + (PF_WIN_SZ(0) / sizeof(u32))), 0);
+ write32((mmio + (PF_WIN_POS(0) / sizeof(u32))), 0);
#else
- write32(mmio + PIPESRC(0), (719 << 16) | 399);
- write32(mmio + PF_WIN_POS(0), 0);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32((mmio + (PIPESRC(0) / sizeof(u32))), (719 << 16) | 399);
+ write32((mmio + (PF_WIN_POS(0) / sizeof(u32))), 0);
+ write32((mmio + (PF_CTL(0) / sizeof(u32))),PF_ENABLE | PF_FILTER_MED_3x3);
+ write32((mmio + (PF_WIN_SZ(0) / sizeof(u32))),
+ vactive | (hactive << 16));
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32((mmio + (PIPE_DATA_M1(0) / sizeof(u32))),
+ 0x7e000000 | data_m1);
+ write32((mmio + (PIPE_DATA_N1(0) / sizeof(u32))), data_n1);
+ write32((mmio + (PIPE_LINK_M1(0) / sizeof(u32))), link_m1);
+ write32((mmio + (PIPE_LINK_N1(0) / sizeof(u32))), link_n1);
link_train(mmio);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
+ write32((mmio + (CPU_VGACNTRL / sizeof(u32))),0x298e | VGA_DISP_DISABLE);
#else
- write32(mmio+CPU_VGACNTRL,0x298e);
+ write32((mmio + (CPU_VGACNTRL / sizeof(u32))),0x298e);
#endif
- write32(mmio+0x60100,0x44300);
- write32(mmio+0x60100,0x80044f00);
+ write32((mmio + (0x60100 / sizeof(u32))),0x44300);
+ write32((mmio + (0x60100 / sizeof(u32))),0x80044f00);
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000600
+ read32((mmio + (0x000f0014 / sizeof(u32)))); // = 0x00000600
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32((mmio + (DSPCNTR(0) / sizeof(u32))),
+ DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
#endif
- write32(mmio + TRANS_HTOTAL(0),
+ write32(mmio + (TRANS_HTOTAL(0) / sizeof(u32)),
((hactive + right_border + hblank - 1) << 16)
| (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
+ write32(mmio + (TRANS_HBLANK(0) / sizeof(u32)),
((hactive + right_border + hblank - 1) << 16)
| (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
+ write32((mmio + (TRANS_HSYNC(0) / sizeof(u32))),
((hactive + right_border + hfront_porch + hsync - 1) << 16)
| (hactive + right_border + hfront_porch - 1));
- write32(mmio + TRANS_VTOTAL(0),
+ write32((mmio + (TRANS_VTOTAL(0) / sizeof(u32))),
((vactive + bottom_border + vblank - 1) << 16)
| (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
+ write32((mmio + (TRANS_VBLANK(0) / sizeof(u32))),
((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
+ write32((mmio + (TRANS_VSYNC(0) / sizeof(u32))),
+ (vactive + bottom_border + vfront_porch - 1)
| (vactive + bottom_border + vfront_porch - 1));
link_normal_operation(mmio);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ write32((mmio + (PCH_PP_CONTROL / sizeof(u32))),
+ PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
mdelay(1);
- write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32((mmio + (PCH_TRANSCONF(0) / sizeof(u32))), TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
| TRANS_STATE_MASK
#endif
);
- write32(mmio + PCH_LVDS,
+ write32((mmio + (PCH_LVDS / sizeof(u32))),
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
@@ -483,30 +491,33 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+ write32((mmio + (PCH_PP_CONTROL / sizeof(u32))),
+ PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ write32((mmio + (PCH_PP_CONTROL / sizeof(u32))),
+ PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
+ write32((mmio + (PCH_PP_CONTROL / sizeof(u32))), PANEL_UNLOCK_REGS
| PANEL_POWER_ON | PANEL_POWER_RESET);
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1)
{
u32 reg32;
- reg32 = read32(mmio + PCH_PP_STATUS);
+ reg32 = read32((mmio + (PCH_PP_STATUS / sizeof(u32))));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32((mmio + (PCH_PP_CONTROL / sizeof(u32))),
+ PANEL_POWER_ON | PANEL_POWER_RESET);
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32((mmio + (DEIIR / sizeof(u32))), 0xffffffff);
+ write32((mmio + (SDEIIR / sizeof(u32))), 0xffffffff);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 08cceea..a3b0589 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -35,95 +35,95 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void train_link(u32 mmio)
+static void train_link(u32 *mmio)
{
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
+ write32(mmio + (DEIIR / sizeof(u32)), 0xffffffff);
- write32(mmio + 0xf000c, 0x2040);
- write32(mmio + 0xf000c, 0x2050);
- write32(mmio + 0x60100, 0x44000);
- write32(mmio + 0xf000c, 0x22050);
+ write32(mmio + (0xf000c / sizeof(u32)), 0x2040);
+ write32(mmio + (0xf000c / sizeof(u32)), 0x2050);
+ write32(mmio + (0x60100 / sizeof(u32)), 0x44000);
+ write32(mmio + (0xf000c / sizeof(u32)), 0x22050);
mdelay(1);
- write32(mmio + 0x000f0018, 0x0000008ff);
- write32(mmio + 0x000f1018, 0x0000008ff);
+ write32(mmio + (0x000f0018 / sizeof(u32)), 0x0000008ff);
+ write32(mmio + (0x000f1018 / sizeof(u32)), 0x0000008ff);
- write32(mmio + 0x000f000c, 0x001a2050);
- write32(mmio + 0x00060100, 0x001c4000);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x001a2050);
+ write32(mmio + (0x00060100 / sizeof(u32)), 0x001c4000);
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
+ write32(mmio + (0x00060100 / sizeof(u32)), 0x801c4000);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x801a2050);
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
+ write32(mmio + (0x00060100 / sizeof(u32)), 0x801c4000);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x801a2050);
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000100
- write32(mmio + 0x000f0014, 0x00000100);
- write32(mmio + 0x00060100, 0x901c4000);
- write32(mmio + 0x000f000c, 0x801a2150);
+ read32(mmio + (0x000f0014 / sizeof(u32))); // = 0x00000100
+ write32(mmio + (0x000f0014 / sizeof(u32)), 0x00000100);
+ write32(mmio + (0x00060100 / sizeof(u32)), 0x901c4000);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x801a2150);
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000600
+ read32(mmio + (0x000f0014 / sizeof(u32))); // = 0x00000600
}
-static void power_port(u32 mmio)
+static void power_port(u32 *mmio)
{
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- write32(mmio + 0x000e1100, 0x00010000);
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- read32(mmio + 0x000e1100); // = 0x00000000
- read32(mmio + 0x000e4200); // = 0x0000001c
- write32(mmio + 0x000e4210, 0x8004003e);
- write32(mmio + 0x000e4214, 0x80060002);
- write32(mmio + 0x000e4218, 0x01000000);
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- write32(mmio + 0x000e4f00, 0x0100030c);
- write32(mmio + 0x000e4f04, 0x00b8230c);
- write32(mmio + 0x000e4f08, 0x06f8930c);
- write32(mmio + 0x000e4f0c, 0x09f8e38e);
- write32(mmio + 0x000e4f10, 0x00b8030c);
- write32(mmio + 0x000e4f14, 0x0b78830c);
- write32(mmio + 0x000e4f18, 0x0ff8d3cf);
- write32(mmio + 0x000e4f1c, 0x01e8030c);
- write32(mmio + 0x000e4f20, 0x0ff863cf);
- write32(mmio + 0x000e4f24, 0x0ff803cf);
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000c4000); // = 0x00000000
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000e1150); // = 0x0000001c
- write32(mmio + 0x000e1150, 0x0000089c);
- write32(mmio + 0x000fcc00, 0x01986f00);
- write32(mmio + 0x000fcc0c, 0x01986f00);
- write32(mmio + 0x000fcc18, 0x01986f00);
- write32(mmio + 0x000fcc24, 0x01986f00);
- read32(mmio + 0x000c4000); // = 0x00000000
- read32(mmio + 0x000e1180); // = 0x40000002
+ read32(mmio + (0x000e1100 / sizeof(u32))); // = 0x00000000
+ write32(mmio + (0x000e1100 / sizeof(u32)), 0x00000000);
+ write32(mmio + (0x000e1100 / sizeof(u32)), 0x00010000);
+ read32(mmio + (0x000e1100 / sizeof(u32))); // = 0x00010000
+ read32(mmio + (0x000e1100 / sizeof(u32))); // = 0x00010000
+ read32(mmio + (0x000e1100 / sizeof(u32))); // = 0x00000000
+ write32(mmio + (0x000e1100 / sizeof(u32)), 0x00000000);
+ read32(mmio + (0x000e1100 / sizeof(u32))); // = 0x00000000
+ read32(mmio + (0x000e4200 / sizeof(u32))); // = 0x0000001c
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x8004003e);
+ write32(mmio + (0x000e4214 / sizeof(u32)), 0x80060002);
+ write32(mmio + (0x000e4218 / sizeof(u32)), 0x01000000);
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x5144003e
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x5344003e);
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x0144003e
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x8074003e);
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x5144003e
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x5144003e
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x5344003e);
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x0144003e
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x8074003e);
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x5144003e
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x5144003e
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x5344003e);
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x0144003e
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x8074003e);
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x5144003e
+ read32(mmio + (0x000e4210 / sizeof(u32))); // = 0x5144003e
+ write32(mmio + (0x000e4210 / sizeof(u32)), 0x5344003e);
+ write32(mmio + (0x000e4f00 / sizeof(u32)), 0x0100030c);
+ write32(mmio + (0x000e4f04 / sizeof(u32)), 0x00b8230c);
+ write32(mmio + (0x000e4f08 / sizeof(u32)), 0x06f8930c);
+ write32(mmio + (0x000e4f0c / sizeof(u32)), 0x09f8e38e);
+ write32(mmio + (0x000e4f10 / sizeof(u32)), 0x00b8030c);
+ write32(mmio + (0x000e4f14 / sizeof(u32)), 0x0b78830c);
+ write32(mmio + (0x000e4f18 / sizeof(u32)), 0x0ff8d3cf);
+ write32(mmio + (0x000e4f1c / sizeof(u32)), 0x01e8030c);
+ write32(mmio + (0x000e4f20 / sizeof(u32)), 0x0ff863cf);
+ write32(mmio + (0x000e4f24 / sizeof(u32)), 0x0ff803cf);
+ write32(mmio + (0x000c4030 / sizeof(u32)), 0x00001000);
+ read32(mmio + (0x000c4000 / sizeof(u32))); // = 0x00000000
+ write32(mmio + (0x000c4030 / sizeof(u32)), 0x00001000);
+ read32(mmio + (0x000e1150 / sizeof(u32))); // = 0x0000001c
+ write32(mmio + (0x000e1150 / sizeof(u32)), 0x0000089c);
+ write32(mmio + (0x000fcc00 / sizeof(u32)), 0x01986f00);
+ write32(mmio + (0x000fcc0c / sizeof(u32)), 0x01986f00);
+ write32(mmio + (0x000fcc18 / sizeof(u32)), 0x01986f00);
+ write32(mmio + (0x000fcc24 / sizeof(u32)), 0x01986f00);
+ read32(mmio + (0x000c4000 / sizeof(u32))); // = 0x00000000
+ read32(mmio + (0x000e1180 / sizeof(u32))); // = 0x40000002
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u32 mmio, u32 lfb)
+ u32 physbase, u16 piobase, u32 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
@@ -144,23 +144,24 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 link_m1;
u32 link_n1 = 0x00080000;
- write32(mmio + 0x00070080, 0x00000000);
- write32(mmio + DSPCNTR(0), 0x00000000);
- write32(mmio + 0x00071180, 0x00000000);
- write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
- write32(mmio + 0x0007019c, 0x00000000);
- write32(mmio + 0x0007119c, 0x00000000);
- write32(mmio + 0x000ec008, 0x2c010000);
- write32(mmio + 0x000ec020, 0x2c010000);
- write32(mmio + 0x000ec038, 0x2c010000);
- write32(mmio + 0x000ec050, 0x2c010000);
- write32(mmio + 0x000ec408, 0x2c010000);
- write32(mmio + 0x000ec420, 0x2c010000);
- write32(mmio + 0x000ec438, 0x2c010000);
- write32(mmio + 0x000ec450, 0x2c010000);
+ write32(mmio + (0x00070080 / sizeof(u32)), 0x00000000);
+ write32(mmio + (DSPCNTR(0) / sizeof(u32)), 0x00000000);
+ write32(mmio + (0x00071180 / sizeof(u32)), 0x00000000);
+ write32(mmio + (CPU_VGACNTRL / sizeof(u32)),
+ 0x0000298e | VGA_DISP_DISABLE);
+ write32(mmio + (0x0007019c / sizeof(u32)), 0x00000000);
+ write32(mmio + (0x0007119c / sizeof(u32)), 0x00000000);
+ write32(mmio + (0x000ec008 / sizeof(u32)), 0x2c010000);
+ write32(mmio + (0x000ec020 / sizeof(u32)), 0x2c010000);
+ write32(mmio + (0x000ec038 / sizeof(u32)), 0x2c010000);
+ write32(mmio + (0x000ec050 / sizeof(u32)), 0x2c010000);
+ write32(mmio + (0x000ec408 / sizeof(u32)), 0x2c010000);
+ write32(mmio + (0x000ec420 / sizeof(u32)), 0x2c010000);
+ write32(mmio + (0x000ec438 / sizeof(u32)), 0x2c010000);
+ write32(mmio + (0x000ec450 / sizeof(u32)), 0x2c010000);
vga_gr_write(0x18, 0);
- write32(mmio + 0x00042004, 0x02000000);
- write32(mmio + 0x000fd034, 0x8421ffe0);
+ write32(mmio + (0x00042004 / sizeof(u32)), 0x02000000);
+ write32(mmio + (0x000fd034 / sizeof(u32)), 0x8421ffe0);
/* Setup GTT. */
for (i = 0; i < 0x2000; i++)
@@ -183,7 +184,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
power_port(mmio);
- intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
+ intel_gmbus_read_edid(mmio + (PCH_GMBUS0/sizeof(u32)), 3, 0x50, edid_data, 128);
decode_edid(edid_data,
sizeof(edid_data), &edid);
@@ -226,10 +227,10 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32(mmio + (DSPCNTR(0) / sizeof(u32)), DISPPLANE_BGRX888);
+ write32(mmio + (DSPADDR(0) / sizeof(u32)), 0);
+ write32(mmio + (DSPSTRIDE(0) / sizeof(u32)), edid.bytes_per_line);
+ write32(mmio + (DSPSURF(0) / sizeof(u32)), 0);
for (i = 0; i < 0x100; i++)
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
#endif
@@ -304,168 +305,145 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
- write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
- write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
- ? 0x1002 : 0x400));
+ write32(mmio + (PCH_LVDS / sizeof(u32)),
+ (hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED);
+ write32(mmio + (BLC_PWM_CPU_CTL2 / sizeof(u32)), (1 << 31));
+ write32(mmio + (PCH_DREF_CONTROL / sizeof(u32)),
+ (info->use_spread_spectrum_clock ? 0x1002 : 0x400));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + _PCH_FP0(0),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + PCH_DPLL_SEL, 8);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(mmio + (PCH_PP_CONTROL / sizeof(u32)),
+ PANEL_UNLOCK_REGS | (read32(mmio + (PCH_PP_CONTROL / sizeof(u32))) & ~PANEL_UNLOCK_MASK));
+ write32(mmio + (_PCH_FP0(0) / sizeof(u32)),
+ ((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2);
+ write32(mmio + (PCH_DPLL_SEL / sizeof(u32)), 8);
+ write32(mmio + (_PCH_DPLL(0) / sizeof(u32)),
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)));
mdelay(1);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(mmio + (_PCH_DPLL(0) / sizeof(u32)),
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */
- write32(mmio + PCH_PP_CONTROL,
- (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
- write32(mmio + PF_WIN_POS(0), 0);
+ write32(mmio + (PCH_PP_CONTROL / sizeof(u32)),
+ (read32(mmio + (PCH_PP_CONTROL / sizeof(u32))) & ~PANEL_UNLOCK_MASK));
+
+ write32(mmio + (PCH_LVDS / sizeof(u32)),
+ (hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED);
+
+ write32(mmio + (HTOTAL(0) / sizeof(u32)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive - 1));
+ write32(mmio + (HBLANK(0) / sizeof(u32)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1));
+ write32(mmio + (HSYNC(0) / sizeof(u32)),
+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1));
+
+ write32(mmio + (VTOTAL(0) / sizeof(u32)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1));
+ write32(mmio + (VBLANK(0) / sizeof(u32)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1));
+ write32(mmio + (VSYNC(0) / sizeof(u32)),
+ (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1));
+
+ write32(mmio + (PIPECONF(0) / sizeof(u32)), PIPECONF_DISABLE);
+
+ write32(mmio + (PF_WIN_POS(0) / sizeof(u32)), 0);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
+ write32(mmio + (PIPESRC(0) / sizeof(u32)),
+ ((hactive - 1) << 16) | (vactive - 1));
+ write32(mmio + (PF_CTL(0) / sizeof(u32)), 0);
+ write32(mmio + (PF_WIN_SZ(0) / sizeof(u32)), 0);
#else
- write32(mmio + PIPESRC(0), (639 << 16) | 399);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32(mmio + (PIPESRC(0) / sizeof(u32)), (639 << 16) | 399);
+ write32(mmio + (PF_CTL(0) / sizeof(u32)),
+ PF_ENABLE | PF_FILTER_MED_3x3);
+ write32(mmio + (PF_WIN_SZ(0) / sizeof(u32)),
+ vactive | (hactive << 16));
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32(mmio + (PIPE_DATA_M1(0) / sizeof(u32)), 0x7e000000 | data_m1);
+ write32(mmio + (PIPE_DATA_N1(0) / sizeof(u32)), data_n1);
+ write32(mmio + (PIPE_LINK_M1(0) / sizeof(u32)), link_m1);
+ write32(mmio + (PIPE_LINK_N1(0) / sizeof(u32)), link_n1);
- write32(mmio + 0x000f000c, 0x00002040);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x00002040);
mdelay(1);
- write32(mmio + 0x000f000c, 0x00002050);
- write32(mmio + 0x00060100, 0x00044000);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x00002050);
+ write32(mmio + (0x00060100 / sizeof(u32)), 0x00044000);
mdelay(1);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
- write32(mmio + 0x000f000c, 0x00022050);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32(mmio + (PIPECONF(0) / sizeof(u32)), PIPECONF_BPP_6);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x00022050);
+ write32(mmio + (PIPECONF(0) / sizeof(u32)),
+ PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32(mmio + (PIPECONF(0) / sizeof(u32)),
+ PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
+ write32(mmio + (CPU_VGACNTRL / sizeof(u32)),
+ 0x20298e | VGA_DISP_DISABLE);
#else
- write32(mmio + CPU_VGACNTRL, 0x20298e);
+ write32(mmio + (CPU_VGACNTRL / sizeof(u32)), 0x20298e);
#endif
train_link(mmio);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32(mmio + (DSPCNTR(0) / sizeof(u32)),
+ DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
#endif
- write32(mmio + TRANS_HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + TRANS_VTOTAL(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + 0x00060100, 0xb01c4000);
- write32(mmio + 0x000f000c, 0x801a2350);
+ write32(mmio + (TRANS_HTOTAL(0) / sizeof(u32)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive - 1));
+ write32(mmio + (TRANS_HBLANK(0) / sizeof(u32)),
+ ((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1));
+ write32(mmio + (TRANS_HSYNC(0) / sizeof(u32)),
+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1));
+
+ write32(mmio + (TRANS_VTOTAL(0) / sizeof(u32)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1));
+ write32(mmio + (TRANS_VBLANK(0) / sizeof(u32)),
+ ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1));
+ write32(mmio + (TRANS_VSYNC(0) / sizeof(u32)),
+ (vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1));
+
+ write32(mmio + (0x00060100 / sizeof(u32)), 0xb01c4000);
+ write32(mmio + (0x000f000c / sizeof(u32)), 0x801a2350);
mdelay(1);
- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32(mmio + (TRANSCONF(0) / sizeof(u32)), TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
+
+ | TRANS_STATE_MASK
#endif
- );
-
- write32(mmio + PCH_LVDS,
- LVDS_PORT_ENABLE
- | (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+);
+
+ write32(mmio + (PCH_LVDS / sizeof(u32)),
+ LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED);
+
+ write32(mmio + (PCH_PP_CONTROL / sizeof(u32)),
+ PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ write32(mmio + (PCH_PP_CONTROL / sizeof(u32)),
+ PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(mmio + (PCH_PP_CONTROL / sizeof(u32)),
+ PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET);
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
- reg32 = read32(mmio + PCH_PP_STATUS);
+ reg32 = read32(mmio + (PCH_PP_STATUS / sizeof(u32)));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(mmio + (PCH_PP_CONTROL / sizeof(u32)),
+ PANEL_POWER_ON | PANEL_POWER_RESET);
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32(mmio + (DEIIR / sizeof(u32)), 0xffffffff);
+ write32(mmio + (SDEIIR / sizeof(u32)), 0xffffffff);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index de6dac7..342f53f 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -181,10 +181,10 @@ static void wait_txt_clear(void)
if (!(cp.ecx & 0x40))
return;
/* Some TXT public bit. */
- if (!(read32(0xfed30010) & 1))
+ if (!(read32((void *)0xfed30010) & 1))
return;
/* Wait for TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((void *)0xfed40000) & (1 << 7))) ;
}
static void sfence(void)
@@ -1105,7 +1105,7 @@ static void dram_ioregs(ramctr_timing * ctrl)
static void wait_428c(int channel)
{
while (1) {
- if (read32(DEFAULT_MCHBAR | 0x428c | (channel << 10)) & 0x50)
+ if (read32((void *)(DEFAULT_MCHBAR | 0x428c | (channel << 10))) & 0x50)
return;
}
}
@@ -1122,15 +1122,15 @@ static void write_reset(ramctr_timing * ctrl)
/* choose a populated rank. */
slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01);
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x0f003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel), 0x80c01);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x400001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 0x400001);
wait_428c(channel);
}
@@ -1229,25 +1229,25 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank,
printram("MRd: %x <= %x\n", reg, val);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x0f000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel), 0x41001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | (reg << 20) | val | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel), 0x1f000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel), 0x41001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | (reg << 20) | val | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel), 0x0f000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x1001 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | (reg << 20) | val | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel), 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 0x80001);
}
static u32 make_mr0(ramctr_timing * ctrl, u8 rank)
@@ -1385,15 +1385,15 @@ static void dram_mrscommands(ramctr_timing * ctrl)
printram("done\n");
}
- write32(DEFAULT_MCHBAR + 0x4e20, 0x7);
- write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001);
- write32(DEFAULT_MCHBAR + 0x4e00, 0x60002);
- write32(DEFAULT_MCHBAR + 0x4e10, 0);
- write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003);
- write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001);
- write32(DEFAULT_MCHBAR + 0x4e04, 0x60400);
- write32(DEFAULT_MCHBAR + 0x4e14, 0x288);
- write32(DEFAULT_MCHBAR + 0x4e84, 0x40004);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e20), 0x7);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e30), 0xf1001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e00), 0x60002);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e10), 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e24), 0x1f003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e34), 0x1901001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e04), 0x60400);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e14), 0x288);
+ write32((void *)(DEFAULT_MCHBAR + 0x4e84), 0x40004);
// Drain
FOR_ALL_CHANNELS {
@@ -1417,12 +1417,16 @@ static void dram_mrscommands(ramctr_timing * ctrl)
// Drain
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x0f003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ 0x659001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(rank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0x3e0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 0x1);
// Drain
wait_428c(channel);
@@ -1593,33 +1597,35 @@ static void test_timA(ramctr_timing * ctrl, int channel, int slotrank)
{
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x1f000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
(0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel), 0x1f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
+ 0x4040c01);
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
+ (slotrank << 24));
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel), 0x1f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x100f | ((ctrl->CAS + 36) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel), 0x1f000);
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
(0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 0xc0001);
wait_428c(channel);
}
@@ -1628,9 +1634,7 @@ static int does_lane_work(ramctr_timing * ctrl, int channel, int slotrank,
int lane)
{
u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA;
- return ((read32
- (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 +
- ((timA / 32) & 1) * 4)
+ return ((read32((void *)(DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timA / 32) & 1) * 4))
>> (timA % 32)) & 1);
}
@@ -1854,15 +1858,19 @@ static void read_training(ramctr_timing * ctrl)
struct timA_minmax mnmx;
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x1f002);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 1);
- write32(DEFAULT_MCHBAR + 0x3400, (slotrank << 2) | 0x8001);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400),
+ (slotrank << 2) | 0x8001);
ctrl->timings[channel][slotrank].val_4028 = 4;
ctrl->timings[channel][slotrank].val_4024 = 55;
@@ -1927,13 +1935,13 @@ static void read_training(ramctr_timing * ctrl)
lane,
ctrl->timings[channel][slotrank].lanes[lane].timA);
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0);
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(DEFAULT_MCHBAR + 0x5030));
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 | 0x20);
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 & ~0x20);
udelay(1);
}
@@ -1942,8 +1950,8 @@ static void read_training(ramctr_timing * ctrl)
program_timings(ctrl, channel);
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel
- + 4 * lane, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane),
+ 0);
}
}
@@ -1952,74 +1960,77 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
int lane;
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane, 0);
- read32(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane);
+ write32((void *)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane),
+ 0);
+ read32((void *)(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane));
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
- | 4 | (ctrl->tRCD << 16));
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x1f006);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | (6 << 16));
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0x244);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel), 0x1f207);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
+ 0x8041001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 8);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel), 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4);
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel), 0x1f201);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
+ 0x80411f4);
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
+ (slotrank << 24));
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel), 0x242);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel), 0x1f207);
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 8);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel), 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 0xc0001);
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x1f002);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0x240);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
- | 8 | (ctrl->CAS << 16));
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel), 0x1f006);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
+ (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel), 0x244);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel), 0x1f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x40011f4 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
+ (slotrank << 24));
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel), 0x242);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel), 0x1f002);
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel), 0x240);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 0xc0001);
wait_428c(channel);
}
@@ -2031,13 +2042,13 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank)
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x1f002);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0x240);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 1);
for (timC = 0; timC <= MAX_TIMC; timC++) {
FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
@@ -2048,8 +2059,7 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank)
FOR_ALL_LANES {
statistics[lane][timC] =
- read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +
- 0x400 * channel);
+ read32((void *)(DEFAULT_MCHBAR + 0x4340 + 4 * lane + 0x400 * channel));
printram("Cstat: %d, %d, %d, %x, %x\n",
channel, slotrank, lane, timC,
statistics[lane][timC]);
@@ -2081,7 +2091,8 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b)
get_precedening_channels(ctrl, channel) * 0x40;
printram("channel_offset=%x\n", channel_offset);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + 4 * j, j & 2 ? b : a);
+ write32((void *)(0x04000000 + channel_offset + 4 * j),
+ j & 2 ? b : a);
sfence();
}
@@ -2100,9 +2111,11 @@ static void fill_pattern1(ramctr_timing * ctrl, int channel)
get_precedening_channels(ctrl, channel) * 0x40;
unsigned channel_step = 0x40 * num_of_channels(ctrl);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + j * 4, 0xffffffff);
+ write32((void *)(0x04000000 + channel_offset + j * 4),
+ 0xffffffff);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + channel_step + j * 4, 0);
+ write32((void *)(0x04000000 + channel_offset + channel_step + j * 4),
+ 0);
sfence();
}
@@ -2121,38 +2134,42 @@ static void precharge(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
0xc0001);
wait_428c(channel);
@@ -2170,40 +2187,44 @@ static void precharge(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
0xc0001);
wait_428c(channel);
}
@@ -2216,21 +2237,21 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank)
0x80 | make_mr1(ctrl, slotrank));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x1f207);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
8 | (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel), 0x1f107);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
0x4000c01 | ((ctrl->CAS + 38) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 4);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001);
+ write32((void *)(DEFAULT_MCHBAR + 0x400 * channel + 0x4284), 0x40001);
wait_428c(channel);
write_mrreg(ctrl, channel, slotrank, 1,
@@ -2243,7 +2264,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
int statistics[NUM_LANES][128];
int lane;
- write32(DEFAULT_MCHBAR + 0x3400, 0x108052 | (slotrank << 2));
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0x108052 | (slotrank << 2));
for (timB = 0; timB < 128; timB++) {
FOR_ALL_LANES {
@@ -2255,9 +2276,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
FOR_ALL_LANES {
statistics[lane][timB] =
- !((read32
- (DEFAULT_MCHBAR + lane_registers[lane] +
- channel * 0x100 + 4 + ((timB / 32) & 1) * 4)
+ !((read32((void *)(DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4))
>> (timB % 32)) & 1);
printram("Bstat: %d, %d, %d, %x, %x\n",
channel, slotrank, lane, timB,
@@ -2295,80 +2314,95 @@ static int get_timB_high_adjust(u64 val)
static void adjust_high_timB(ramctr_timing * ctrl)
{
int channel, slotrank, lane;
- write32(DEFAULT_MCHBAR + 0x3400, 0x200);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0x200);
FOR_ALL_POPULATED_CHANNELS {
fill_pattern1(ctrl, channel);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 1);
+ write32((void *)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)),
+ 1);
}
FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x10001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel),
+ 0x10001);
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x1f006);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tRCD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
+ 0x1f207);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
+ 0x8040c01);
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 0x8);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003);
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0x3e0);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
+ 0x1f201);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
+ 0x8041003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0x3e2);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
+ 0x1f207);
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x8);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 0xc0001);
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x1f002);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | ((ctrl->tRP) << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0x240);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
+ 0x1f006);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
0xc01 | ((ctrl->tRCD) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x4000c01 |
- ((ctrl->tRP +
- ctrl->timings[channel][slotrank].val_4024 +
- ctrl->timings[channel][slotrank].val_4028) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
+ 0x3f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
+ 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + ctrl->timings[channel][slotrank].val_4028) << 16));
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | 0x60008);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 0x80001);
wait_428c(channel);
FOR_ALL_LANES {
u64 res =
- read32(DEFAULT_MCHBAR + lane_registers[lane] +
- 0x100 * channel + 4);
+ read32((void *)(DEFAULT_MCHBAR + lane_registers[lane] + 0x100 * channel + 4));
res |=
- ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] +
- 0x100 * channel + 8)) << 32;
+ ((u64) read32((void *)(DEFAULT_MCHBAR + lane_registers[lane] + 0x100 * channel + 8))) << 32;
ctrl->timings[channel][slotrank].lanes[lane].timB +=
get_timB_high_adjust(res) * 64;
@@ -2379,7 +2413,7 @@ static void adjust_high_timB(ramctr_timing * ctrl)
timB);
}
}
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0);
}
static void write_op(ramctr_timing * ctrl, int channel)
@@ -2391,15 +2425,15 @@ static void write_op(ramctr_timing * ctrl, int channel)
/* choose an existing rank. */
slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x0f003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel), 0x41001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 1);
wait_428c(channel);
}
@@ -2409,17 +2443,16 @@ static void write_training(ramctr_timing * ctrl)
u32 r32;
FOR_ALL_POPULATED_CHANNELS
- write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4008 +
- 0x400 * channel) | 0x8000000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel),
+ read32((void *)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel)) | 0x8000000);
FOR_ALL_POPULATED_CHANNELS {
write_op(ctrl, channel);
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel) | 0x200000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel),
+ read32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)) | 0x200000);
}
- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030),
+ read32((void *)(DEFAULT_MCHBAR + 0x5030)) & ~8);
FOR_ALL_POPULATED_CHANNELS {
write_op(ctrl, channel);
}
@@ -2429,13 +2462,13 @@ static void write_training(ramctr_timing * ctrl)
write_mrreg(ctrl, channel, slotrank, 1,
make_mr1(ctrl, slotrank) | 0x1080);
- write32(DEFAULT_MCHBAR + 0x3400, 0x108052);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0x108052);
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(DEFAULT_MCHBAR + 0x5030));
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 | 0x20);
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 & ~0x20);
udelay(1);
@@ -2446,34 +2479,39 @@ static void write_training(ramctr_timing * ctrl)
write_mrreg(ctrl, channel,
slotrank, 1, make_mr1(ctrl, slotrank));
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0);
FOR_ALL_POPULATED_CHANNELS
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030),
+ read32((void *)(DEFAULT_MCHBAR + 0x5030)) | 8);
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- ~0x00200000 & read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel));
- read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel);
+ write32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel),
+ ~0x00200000 & read32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)));
+ read32((void *)(DEFAULT_MCHBAR + 0x428c + 0x400 * channel));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x0f003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ 0x659001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
+ 0x60000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0x3e0);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 1);
wait_428c(channel);
}
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(DEFAULT_MCHBAR + 0x5030));
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 | 0x20);
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 & ~0x20);
udelay(1);
@@ -2482,14 +2520,15 @@ static void write_training(ramctr_timing * ctrl)
printram("CPF\n");
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ read32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
+ write32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane),
0);
}
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32((void *)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)),
+ 0);
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
@@ -2504,8 +2543,8 @@ static void write_training(ramctr_timing * ctrl)
program_timings(ctrl, channel);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ read32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
+ write32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane),
0);
}
}
@@ -2525,51 +2564,63 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
}
program_timings(ctrl, channel);
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 4 * lane + 0x4f40, 0);
+ write32((void *)(DEFAULT_MCHBAR + 4 * lane + 0x4f40),
+ 0);
}
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32((void *)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel),
+ 0x1f);
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
- | 8 | (ctrl->tRCD << 16));
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x1f006);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | ctr | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0x244);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
+ 0x1f201);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel),
+ 0x389abcd);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0x20e42);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
+ 0x1f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x4001020 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001);
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel),
+ 0x389abcd);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0x20e42);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
+ 0x1f002);
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
+ 0xf1001);
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0x240);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 0xc0001);
wait_428c(channel);
FOR_ALL_LANES {
u32 r32 =
- read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +
- 0x400 * channel);
+ read32((void *)(DEFAULT_MCHBAR + 0x4340 + 4 * lane + 0x400 * channel));
if (r32 == 0)
lanes_ok |= 1 << lane;
@@ -2602,16 +2653,16 @@ static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno)
u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0;
if (invert[patno - 1][i] & (1 << (j / 2)))
val = ~val;
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, val);
+ write32((void *)(0x04000000 + channel_offset + i * channel_step + j * 4),
+ val);
}
}
} else {
for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) {
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, pattern[i][j]);
+ write32((void *)(0x04000000 + channel_offset + i * channel_step + j * 4),
+ pattern[i][j]);
}
sfence();
}
@@ -2628,36 +2679,44 @@ static void reprogram_320c(ramctr_timing * ctrl)
/* choose an existing rank. */
slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x0f003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ 0x41001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 1);
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel) | 0x200000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel),
+ read32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)) | 0x200000);
}
- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030),
+ read32((void *)(DEFAULT_MCHBAR + 0x5030)) & ~8);
FOR_ALL_POPULATED_CHANNELS {
wait_428c(channel);
/* choose an existing rank. */
slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x0f003);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ 0x41001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 1);
wait_428c(channel);
}
@@ -2666,11 +2725,11 @@ static void reprogram_320c(ramctr_timing * ctrl)
/* mrs commands. */
dram_mrscommands(ctrl);
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(DEFAULT_MCHBAR + 0x5030));
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 | 0x20);
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 & ~0x20);
udelay(1);
}
@@ -2755,7 +2814,8 @@ static void command_training(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS {
fill_pattern5(ctrl, channel, 0);
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32((void *)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel),
+ 0x1f);
}
if (!try_reg_4004_b30(ctrl, 0) && !try_reg_4004_b30(ctrl, 2))
@@ -2786,49 +2846,57 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank,
program_timings(ctrl, channel);
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +
- 4 * lane, 0);
- read32(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane +
- 0x4140);
+ write32((void *)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane),
+ 0);
+ read32((void *)(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane + 0x4140));
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
+ 0x1f000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
(0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
+ 0x1f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
+ 0x40411f4);
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
+ 0x1f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
+ 0x1f000);
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
(0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
+ 0xc0001);
wait_428c(channel);
FOR_ALL_LANES {
statistics[lane][edge] =
- read32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +
- lane * 4);
+ read32((void *)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + lane * 4));
}
}
FOR_ALL_LANES {
@@ -2849,27 +2917,27 @@ static void discover_edges(ramctr_timing * ctrl)
int channel, slotrank, lane;
u32 r32;
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0);
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(DEFAULT_MCHBAR + 0x5030));
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 | 0x20);
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32((void *)(DEFAULT_MCHBAR + 0x5030), r32 & ~0x20);
udelay(1);
FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 4 * lane +
- 0x400 * channel + 0x4080, 0);
+ write32((void *)(DEFAULT_MCHBAR + 4 * lane + 0x400 * channel + 0x4080),
+ 0);
}
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0, 0);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32((void *)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)),
+ 0);
FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x400 * channel +
- lane * 4 + 0x4140);
+ read32((void *)(DEFAULT_MCHBAR + 0x400 * channel + lane * 4 + 0x4140));
}
FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
@@ -2884,38 +2952,42 @@ static void discover_edges(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
0xc0001);
wait_428c(channel);
@@ -2933,70 +3005,73 @@ static void discover_edges(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
0xc0001);
wait_428c(channel);
}
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel +
- lane * 4,
- ~read32(DEFAULT_MCHBAR + 0x4040 +
- 0x400 * channel + lane * 4) & 0xff);
+ write32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + lane * 4),
+ ~read32((void *)(DEFAULT_MCHBAR + 0x4040 + 0x400 * channel + lane * 4)) & 0xff);
}
fill_pattern0(ctrl, channel, 0, 0xffffffff);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32((void *)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)),
+ 0);
}
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);
+ write32((void *)(DEFAULT_MCHBAR + 0x4eb0), 0x300);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_real(ctrl, channel, slotrank,
falling_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
+ write32((void *)(DEFAULT_MCHBAR + 0x4eb0), 0x200);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_real(ctrl, channel, slotrank,
rising_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4eb0), 0);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].falling =
@@ -3010,7 +3085,7 @@ static void discover_edges(ramctr_timing * ctrl)
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ write32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane),
0);
}
}
@@ -3033,11 +3108,12 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
}
for (i = 0; i < 3; i++) {
- write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel),
reg3000b24[i] << 24);
for (pat = 0; pat < NUM_PATTERNS; pat++) {
fill_pattern5(ctrl, channel, pat);
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32((void *)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel),
+ 0x1f);
printram("patterned\n");
printram("[%x] = 0x%08x\n(%d, %d)\n",
0x3000 + 0x100 * channel, reg3000b24[i] << 24, channel,
@@ -3052,57 +3128,53 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
program_timings(ctrl, channel);
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4340 +
- 0x400 * channel + 4 * lane, 0);
- read32(DEFAULT_MCHBAR + 0x400 * channel +
- 4 * lane + 0x4140);
+ write32((void *)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane),
+ 0);
+ read32((void *)(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane + 0x4140));
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel),
0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0x4 | (ctrl->tRCD << 16)
- | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) <<
- 10));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ 0x4 | (ctrl->tRCD << 16) | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10));
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel),
0x240);
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel),
0x1f201);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) <<
- 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
+ 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16));
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
(slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel),
0x242);
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel),
0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x4005020 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
(slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel),
0x242);
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel),
0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel),
+ 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel),
0xc0001);
wait_428c(channel);
FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x4340 +
- 0x400 * channel + lane * 4);
+ read32((void *)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + lane * 4));
}
raw_statistics[edge] =
@@ -3129,7 +3201,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
}
}
- write32(DEFAULT_MCHBAR + 0x3000, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x3000), 0);
printram("CPA\n");
}
@@ -3140,21 +3212,21 @@ static void discover_edges_write(ramctr_timing * ctrl)
int channel, slotrank, lane;
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);
+ write32((void *)(DEFAULT_MCHBAR + 0x4eb0), 0x300);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_write_real(ctrl, channel, slotrank,
falling_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
+ write32((void *)(DEFAULT_MCHBAR + 0x4eb0), 0x200);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_write_real(ctrl, channel, slotrank,
rising_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4eb0), 0);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].falling =
@@ -3167,7 +3239,7 @@ static void discover_edges_write(ramctr_timing * ctrl)
program_timings(ctrl, channel);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
+ write32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane),
0);
}
}
@@ -3175,46 +3247,35 @@ static void discover_edges_write(ramctr_timing * ctrl)
static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
{
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD)
- << 10) | (ctrl->tRCD << 16) | 4);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel), 0x1f006);
+ write32((void *)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel),
+ (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4);
+ write32((void *)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel),
(slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x80011e0 |
- ((ctrl->tWTR + ctrl->CWL + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 +
- 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 +
- 0x400 * channel, 0x242);
-
- write32(DEFAULT_MCHBAR + 0x4228 +
- 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 +
- 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel), 0x244);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel), 0x1f201);
+ write32((void *)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel),
+ 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16));
+ write32((void *)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel),
+ (slotrank << 24));
+ write32((void *)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel), 0x242);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel), 0x1f105);
+ write32((void *)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel),
0x40011e0 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 +
- 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 +
- 0x400 * channel, 0x242);
-
- write32(DEFAULT_MCHBAR + 0x422c +
- 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c +
- 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel),
+ (slotrank << 24));
+ write32((void *)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel), 0x242);
+
+ write32((void *)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel), 0x1f002);
+ write32((void *)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel),
0x1001 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x420c +
- 0x400 * channel,
+ write32((void *)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel),
(slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c +
- 0x400 * channel, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel), 0);
- write32(DEFAULT_MCHBAR + 0x4284 +
- 0x400 * channel, 0xc0001);
+ write32((void *)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel), 0xc0001);
wait_428c(channel);
}
@@ -3232,14 +3293,12 @@ static void discover_timC_write(ramctr_timing * ctrl)
upper[channel][slotrank][lane] = MAX_TIMC;
}
- write32(DEFAULT_MCHBAR + 0x4ea8, 1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4ea8), 1);
for (i = 0; i < 3; i++)
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100),
- (rege3c_b24[i] << 24)
- | (read32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100))
- & ~0x3f000000));
+ write32((void *)(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100)),
+ (rege3c_b24[i] << 24) | (read32((void *)(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100))) & ~0x3f000000));
udelay(2);
for (pat = 0; pat < NUM_PATTERNS; pat++) {
FOR_ALL_POPULATED_RANKS {
@@ -3248,7 +3307,8 @@ static void discover_timC_write(ramctr_timing * ctrl)
int statistics[MAX_TIMC + 1];
fill_pattern5(ctrl, channel, pat);
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32((void *)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel),
+ 0x1f);
for (timC = 0; timC < MAX_TIMC + 1; timC++) {
FOR_ALL_LANES
ctrl->timings[channel][slotrank].lanes[lane].timC = timC;
@@ -3287,13 +3347,12 @@ static void discover_timC_write(ramctr_timing * ctrl)
}
FOR_ALL_CHANNELS {
- write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c,
- 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) &
- ~0x3f000000));
+ write32((void *)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c),
+ 0 | (read32((void *)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c)) & ~0x3f000000));
udelay(2);
}
- write32(DEFAULT_MCHBAR + 0x4ea8, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4ea8), 0);
printram("CPB\n");
@@ -3335,10 +3394,10 @@ static void write_controller_mr(ramctr_timing * ctrl)
int channel, slotrank;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
- write32(DEFAULT_MCHBAR | 0x0004 | (channel << 8) |
- lane_registers[slotrank], make_mr0(ctrl, slotrank));
- write32(DEFAULT_MCHBAR | 0x0008 | (channel << 8) |
- lane_registers[slotrank], make_mr1(ctrl, slotrank));
+ write32((void *)(DEFAULT_MCHBAR | 0x0004 | (channel << 8) | lane_registers[slotrank]),
+ make_mr0(ctrl, slotrank));
+ write32((void *)(DEFAULT_MCHBAR | 0x0008 | (channel << 8) | lane_registers[slotrank]),
+ make_mr1(ctrl, slotrank));
}
}
@@ -3347,46 +3406,62 @@ static void channel_test(ramctr_timing * ctrl)
int channel, slotrank, lane;
FOR_ALL_POPULATED_CHANNELS
- if (read32(DEFAULT_MCHBAR | 0x42a0 | (channel << 10)) & 0xa000)
+ if (read32((void *)(DEFAULT_MCHBAR | 0x42a0 | (channel << 10))) & 0xa000)
die("Mini channel test failed (1)\n");
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32((void *)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)),
+ 0);
}
for (slotrank = 0; slotrank < 4; slotrank++)
FOR_ALL_CHANNELS
if (ctrl->rankmap[channel] & (1 << slotrank)) {
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR | (0x4f40 + 4 * lane), 0);
- write32(DEFAULT_MCHBAR | (0x4d40 + 4 * lane), 0);
+ write32((void *)(DEFAULT_MCHBAR | (0x4f40 + 4 * lane)),
+ 0);
+ write32((void *)(DEFAULT_MCHBAR | (0x4d40 + 4 * lane)),
+ 0);
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR | 0x4220 | (channel << 10), 0x0001f006);
- write32(DEFAULT_MCHBAR | 0x4230 | (channel << 10), 0x0028a004);
- write32(DEFAULT_MCHBAR | 0x4200 | (channel << 10),
+ write32((void *)(DEFAULT_MCHBAR | 0x4220 | (channel << 10)),
+ 0x0001f006);
+ write32((void *)(DEFAULT_MCHBAR | 0x4230 | (channel << 10)),
+ 0x0028a004);
+ write32((void *)(DEFAULT_MCHBAR | 0x4200 | (channel << 10)),
0x00060000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4210 | (channel << 10), 0x00000244);
- write32(DEFAULT_MCHBAR | 0x4224 | (channel << 10), 0x0001f201);
- write32(DEFAULT_MCHBAR | 0x4234 | (channel << 10), 0x08281064);
- write32(DEFAULT_MCHBAR | 0x4204 | (channel << 10),
+ write32((void *)(DEFAULT_MCHBAR | 0x4210 | (channel << 10)),
+ 0x00000244);
+ write32((void *)(DEFAULT_MCHBAR | 0x4224 | (channel << 10)),
+ 0x0001f201);
+ write32((void *)(DEFAULT_MCHBAR | 0x4234 | (channel << 10)),
+ 0x08281064);
+ write32((void *)(DEFAULT_MCHBAR | 0x4204 | (channel << 10)),
0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4214 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x4228 | (channel << 10), 0x0001f105);
- write32(DEFAULT_MCHBAR | 0x4238 | (channel << 10), 0x04281064);
- write32(DEFAULT_MCHBAR | 0x4208 | (channel << 10),
+ write32((void *)(DEFAULT_MCHBAR | 0x4214 | (channel << 10)),
+ 0x00000242);
+ write32((void *)(DEFAULT_MCHBAR | 0x4228 | (channel << 10)),
+ 0x0001f105);
+ write32((void *)(DEFAULT_MCHBAR | 0x4238 | (channel << 10)),
+ 0x04281064);
+ write32((void *)(DEFAULT_MCHBAR | 0x4208 | (channel << 10)),
0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4218 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x422c | (channel << 10), 0x0001f002);
- write32(DEFAULT_MCHBAR | 0x423c | (channel << 10), 0x00280c01);
- write32(DEFAULT_MCHBAR | 0x420c | (channel << 10),
+ write32((void *)(DEFAULT_MCHBAR | 0x4218 | (channel << 10)),
+ 0x00000242);
+ write32((void *)(DEFAULT_MCHBAR | 0x422c | (channel << 10)),
+ 0x0001f002);
+ write32((void *)(DEFAULT_MCHBAR | 0x423c | (channel << 10)),
+ 0x00280c01);
+ write32((void *)(DEFAULT_MCHBAR | 0x420c | (channel << 10)),
0x00060400 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x421c | (channel << 10), 0x00000240);
- write32(DEFAULT_MCHBAR | 0x4284 | (channel << 10), 0x000c0001);
+ write32((void *)(DEFAULT_MCHBAR | 0x421c | (channel << 10)),
+ 0x00000240);
+ write32((void *)(DEFAULT_MCHBAR | 0x4284 | (channel << 10)),
+ 0x000c0001);
wait_428c(channel);
FOR_ALL_LANES
- if (read32(DEFAULT_MCHBAR | 0x4340 | (channel << 10)))
+ if (read32((void *)(DEFAULT_MCHBAR | 0x4340 | (channel << 10))))
die("Mini channel test failed (2)\n");
}
}
@@ -3403,9 +3478,9 @@ static void set_scrambling_seed(ramctr_timing * ctrl)
};
FOR_ALL_POPULATED_CHANNELS {
MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000;
- write32(DEFAULT_MCHBAR | 0x4034, seeds[channel][0]);
- write32(DEFAULT_MCHBAR | 0x403c, seeds[channel][1]);
- write32(DEFAULT_MCHBAR | 0x4038, seeds[channel][2]);
+ write32((void *)(DEFAULT_MCHBAR | 0x4034), seeds[channel][0]);
+ write32((void *)(DEFAULT_MCHBAR | 0x403c), seeds[channel][1]);
+ write32((void *)(DEFAULT_MCHBAR | 0x4038), seeds[channel][2]);
}
}
@@ -3463,16 +3538,11 @@ static void set_4008c(ramctr_timing * ctrl)
else
b4_8_12 = 0x2220;
- reg = read32(DEFAULT_MCHBAR | 0x400c | (channel << 10));
- write32(DEFAULT_MCHBAR | 0x400c | (channel << 10),
- (reg & 0xFFF0FFFF)
- | (ctrl->ref_card_offset[channel] << 16)
- | (ctrl->ref_card_offset[channel] << 18));
- write32(DEFAULT_MCHBAR | 0x4008 | (channel << 10),
- 0x0a000000
- | (b20 << 20)
- | ((ctrl->ref_card_offset[channel] + 2) << 16)
- | b4_8_12);
+ reg = read32((void *)(DEFAULT_MCHBAR | 0x400c | (channel << 10)));
+ write32((void *)(DEFAULT_MCHBAR | 0x400c | (channel << 10)),
+ (reg & 0xFFF0FFFF) | (ctrl->ref_card_offset[channel] << 16) | (ctrl->ref_card_offset[channel] << 18));
+ write32((void *)(DEFAULT_MCHBAR | 0x4008 | (channel << 10)),
+ 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12);
}
}
@@ -3480,7 +3550,7 @@ static void set_42a0(ramctr_timing * ctrl)
{
int channel;
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR | (0x42a0 + 0x400 * channel),
+ write32((void *)(DEFAULT_MCHBAR | (0x42a0 + 0x400 * channel)),
0x00001000 | ctrl->rankmap[channel]);
MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK
}
@@ -3499,45 +3569,50 @@ static void final_registers(ramctr_timing * ctrl)
int t3_ns;
u32 r32;
- write32(DEFAULT_MCHBAR | 0x4cd4, 0x00000046);
+ write32((void *)(DEFAULT_MCHBAR | 0x4cd4), 0x00000046);
- write32(DEFAULT_MCHBAR | 0x400c, (read32(DEFAULT_MCHBAR | 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x440c, (read32(DEFAULT_MCHBAR | 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x4cb0, 0x00000740);
- write32(DEFAULT_MCHBAR | 0x4380, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4780, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4f88, 0x5f7003ff); // OK
- write32(DEFAULT_MCHBAR | 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK
+ write32((void *)(DEFAULT_MCHBAR | 0x400c),
+ (read32((void *)(DEFAULT_MCHBAR | 0x400c)) & 0xFFFFCFFF) | 0x1000); // OK
+ write32((void *)(DEFAULT_MCHBAR | 0x440c),
+ (read32((void *)(DEFAULT_MCHBAR | 0x440c)) & 0xFFFFCFFF) | 0x1000); // OK
+ write32((void *)(DEFAULT_MCHBAR | 0x4cb0), 0x00000740);
+ write32((void *)(DEFAULT_MCHBAR | 0x4380), 0x00000aaa); // OK
+ write32((void *)(DEFAULT_MCHBAR | 0x4780), 0x00000aaa); // OK
+ write32((void *)(DEFAULT_MCHBAR | 0x4f88), 0x5f7003ff); // OK
+ write32((void *)(DEFAULT_MCHBAR | 0x5064),
+ 0x00073000 | ctrl->reg_5064b0); // OK
FOR_ALL_CHANNELS {
switch (ctrl->rankmap[channel]) {
/* Unpopulated channel. */
case 0:
- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4384 + channel * 0x400),
+ 0);
break;
/* Only single-ranked dimms. */
case 1:
case 4:
case 5:
- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x373131);
+ write32((void *)(DEFAULT_MCHBAR + 0x4384 + channel * 0x400),
+ 0x373131);
break;
/* Dual-ranked dimms present. */
default:
- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x9b6ea1);
+ write32((void *)(DEFAULT_MCHBAR + 0x4384 + channel * 0x400),
+ 0x9b6ea1);
break;
}
}
- write32 (DEFAULT_MCHBAR | 0x5880, 0xca9171e5);
- write32 (DEFAULT_MCHBAR | 0x5888,
- (read32 (DEFAULT_MCHBAR | 0x5888) & ~0xffffff) | 0xe4d5d0);
- write32 (DEFAULT_MCHBAR | 0x58a8, read32 (DEFAULT_MCHBAR | 0x58a8) & ~0x1f);
- write32 (DEFAULT_MCHBAR | 0x4294,
- (read32 (DEFAULT_MCHBAR | 0x4294) & ~0x30000)
- | (1 << 16));
- write32 (DEFAULT_MCHBAR | 0x4694,
- (read32 (DEFAULT_MCHBAR | 0x4694) & ~0x30000)
- | (1 << 16));
+ write32((void *)(DEFAULT_MCHBAR | 0x5880), 0xca9171e5);
+ write32((void *)(DEFAULT_MCHBAR | 0x5888),
+ (read32((void *)(DEFAULT_MCHBAR | 0x5888)) & ~0xffffff) | 0xe4d5d0);
+ write32((void *)(DEFAULT_MCHBAR | 0x58a8),
+ read32((void *)(DEFAULT_MCHBAR | 0x58a8)) & ~0x1f);
+ write32((void *)(DEFAULT_MCHBAR | 0x4294),
+ (read32((void *)(DEFAULT_MCHBAR | 0x4294)) & ~0x30000) | (1 << 16));
+ write32((void *)(DEFAULT_MCHBAR | 0x4694),
+ (read32((void *)(DEFAULT_MCHBAR | 0x4694)) & ~0x30000) | (1 << 16));
MCHBAR32(0x5030) |= 1; // OK
MCHBAR32(0x5030) |= 0x80; // OK
@@ -3547,20 +3622,20 @@ static void final_registers(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS
break;
- t1_cycles = ((read32(DEFAULT_MCHBAR + 0x4290 + channel * 0x400) >> 8) & 0xff);
- r32 = read32(DEFAULT_MCHBAR + 0x5064);
+ t1_cycles = ((read32((void *)(DEFAULT_MCHBAR + 0x4290 + channel * 0x400)) >> 8) & 0xff);
+ r32 = read32((void *)(DEFAULT_MCHBAR + 0x5064));
if (r32 & 0x20000)
t1_cycles += (r32 & 0xfff);
- t1_cycles += (read32(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4) & 0xfff);
+ t1_cycles += (read32((void *)(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4)) & 0xfff);
t1_ns = t1_cycles * ctrl->tCK / 256 + 544;
if (!(r32 & 0x20000))
t1_ns += 500;
- t2_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f10) >> 8) & 0xfff);
- if ( read32(DEFAULT_MCHBAR + 0x5f00) & 8 )
+ t2_ns = 10 * ((read32((void *)(DEFAULT_MCHBAR + 0x5f10)) >> 8) & 0xfff);
+ if (read32((void *)(DEFAULT_MCHBAR + 0x5f00)) & 8 )
{
- t3_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f20) >> 8) & 0xfff);
- t3_ns += 10 * (read32(DEFAULT_MCHBAR + 0x5f18) & 0xff);
+ t3_ns = 10 * ((read32((void *)(DEFAULT_MCHBAR + 0x5f20)) >> 8) & 0xfff);
+ t3_ns += 10 * (read32((void *)(DEFAULT_MCHBAR + 0x5f18)) & 0xff);
}
else
{
@@ -3568,12 +3643,8 @@ static void final_registers(ramctr_timing * ctrl)
}
printk(BIOS_DEBUG, "t123: %d, %d, %d\n",
t1_ns, t2_ns, t3_ns);
- write32 (DEFAULT_MCHBAR + 0x5d10,
- ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16)
- | (encode_5d10(t1_ns) << 8)
- | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24)
- | (read32(DEFAULT_MCHBAR + 0x5d10) & 0xC0C0C0C0)
- | 0xc);
+ write32((void *)(DEFAULT_MCHBAR + 0x5d10),
+ ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | (read32((void *)(DEFAULT_MCHBAR + 0x5d10)) & 0xC0C0C0C0) | 0xc);
}
static void save_timings(ramctr_timing * ctrl)
@@ -3624,26 +3695,24 @@ static void restore_timings(ramctr_timing * ctrl)
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel
- + 4 * lane, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane),
+ 0);
}
FOR_ALL_POPULATED_CHANNELS
- write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4008 +
- 0x400 * channel) | 0x8000000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel),
+ read32((void *)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel)) | 0x8000000);
FOR_ALL_POPULATED_CHANNELS {
udelay (1);
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel) | 0x200000);
+ write32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel),
+ read32((void *)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)) | 0x200000);
}
printram("CPE\n");
- write32(DEFAULT_MCHBAR + 0x3400, 0);
- write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x3400), 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4eb0), 0);
printram("CP5b\n");
@@ -3687,16 +3756,15 @@ static void restore_timings(ramctr_timing * ctrl)
printram("CP5c\n");
- write32(DEFAULT_MCHBAR + 0x3000, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x3000), 0);
FOR_ALL_CHANNELS {
- write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c,
- 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) &
- ~0x3f000000));
+ write32((void *)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c),
+ 0 | (read32((void *)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c)) & ~0x3f000000));
udelay(2);
}
- write32(DEFAULT_MCHBAR + 0x4ea8, 0);
+ write32((void *)(DEFAULT_MCHBAR + 0x4ea8), 0);
}
void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
@@ -3721,10 +3789,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
- reg_5d10 = read32(DEFAULT_MCHBAR | 0x5d10); // !!! = 0x00000000
+ reg_5d10 = read32((void *)(DEFAULT_MCHBAR | 0x5d10)); // !!! = 0x00000000
if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
&& reg_5d10 && !s3resume) {
- write32(DEFAULT_MCHBAR | 0x5d10, 0);
+ write32((void *)(DEFAULT_MCHBAR | 0x5d10), 0);
/* Need reset. */
outb(0x6, 0xcf9);
@@ -3858,7 +3926,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
}
/* FIXME: should be hardware revision-dependent. */
- write32(DEFAULT_MCHBAR | 0x5024, 0x00a030ce);
+ write32((void *)(DEFAULT_MCHBAR | 0x5024), 0x00a030ce);
set_scrambling_seed(&ctrl);
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 0103c4f..1d58702 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -393,7 +393,7 @@ static void sdram_set_post(const struct mem_controller *ctrl)
pci_write_config16(dev, 0xa4, 0x0010);
}
-static void sdram_enable(device_t dev, unsigned long rank_address)
+static void sdram_enable(device_t dev, u32 *rank_address)
{
u8 i;
@@ -401,30 +401,30 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
do_ram_command(dev, RAM_COMMAND_NOP);
udelay(100);
- read32(rank_address + 0x10);
+ read32(rank_address + (0x10/sizeof(u32)));
/* 2. Precharge all. */
udelay(400);
PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
- read32(rank_address + 0x10);
+ read32(rank_address + (0x10/sizeof(u32)));
/* 3. Mode register set. */
PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS);
- read32(rank_address + 0x120000); /* EMRS DLL Enable */
- read32(rank_address + 0x800); /* MRS DLL Reset */
+ read32(rank_address + (0x120000/sizeof(u32))); /* EMRS DLL Enable */
+ read32(rank_address + (0x800/sizeof(u32))); /* MRS DLL Reset */
/* 4. Precharge all again. */
PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
- read32(rank_address + 0x0);
+ read32(rank_address + (0x0/sizeof(u32)));
/* 5. Perform 8 refresh cycles. Wait tRC each time. */
PRINT_DEBUG_MEM("RAM Enable 5: CBR\n");
do_ram_command(dev, RAM_COMMAND_CBR);
for (i = 0; i < 8; i++) {
- read32(rank_address + 0x20);
+ read32(rank_address + (0x20/sizeof(u32)));
udelay(100);
}
@@ -437,14 +437,14 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
* (JESD79-2C).
*/
do_ram_command(dev, RAM_COMMAND_MRS);
- read32(rank_address + 0x002258); /* MRS command */
- read32(rank_address + 0x121c20); /* EMRS OCD Default */
- read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
+ read32(rank_address + (0x002258/sizeof(u32))); /* MRS command */
+ read32(rank_address + (0x121c20/sizeof(u32))); /* EMRS OCD Default */
+ read32(rank_address + (0x120020/sizeof(u32))); /* EMRS OCD Calibration Mode Exit */
/* 8. Normal operation */
PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n");
do_ram_command(dev, RAM_COMMAND_NORMAL);
- read32(rank_address + 0x30);
+ read32(rank_address + (0x30/sizeof(u32)));
}
/*
@@ -457,10 +457,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
c7_cpu_setup(ctrl->d0f2);
sdram_set_registers(ctrl);
sdram_set_size(ctrl);
- sdram_enable(ctrl->d0f3, 0);
+ sdram_enable(ctrl->d0f3, (u32 *)0);
reg = pci_read_config8(ctrl->d0f3, 0x41);
if (reg != 0)
sdram_enable(ctrl->d0f3,
- pci_read_config8(ctrl->d0f3, 0x40) << 26);
+ (u32 *)(pci_read_config8(ctrl->d0f3, 0x40) << 26));
sdram_set_post(ctrl);
}
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index 1e6d2ce..c25e00e 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -274,7 +274,7 @@ static void cx700_lpc_init(struct device *dev)
#if CONFIG_IOAPIC
#define IO_APIC_ID 2
- setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
+ setup_ioapic((void *)IO_APIC_ADDR, IO_APIC_ID);
#endif
/* Initialize interrupts */
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index a2e6dad..a08df20 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -967,9 +967,9 @@ static void step_20_21(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200);
+ read32((void *)0x102200);
else
- read32(0x102020);
+ read32((void *)0x102020);
/* Step 21. Normal operation */
print_spew("RAM Enable 5: Normal operation\n");
@@ -995,7 +995,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 4
print_spew("SEND: ");
- read32(0);
+ read32((void *)0);
print_spew("OK\n");
// Step 5
@@ -1007,7 +1007,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 7
print_spew("SEND: ");
- read32(0);
+ read32((void *)0);
print_spew("OK\n");
/* Step 8. Mode register set. */
@@ -1019,14 +1019,14 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200); //DDR2_ODT_150ohm
+ read32((void *)0x102200); //DDR2_ODT_150ohm
else
- read32(0x102020);
+ read32((void *)0x102020);
print_spew("OK\n");
// Step 10
print_spew("SEND: ");
- read32(0x800);
+ read32((void *)0x800);
print_spew("OK\n");
/* Step 11. Precharge all. Wait tRP. */
@@ -1035,7 +1035,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 12
print_spew("SEND: ");
- read32(0x0);
+ read32((void *)0x0);
print_spew("OK\n");
/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
@@ -1046,7 +1046,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 16: Repeat Step 14 and 15 another 7 times
for (i = 0; i < 8; i++) {
// Step 14
- read32(0);
+ read32((void *)0);
print_spew(".");
// Step 15
@@ -1076,7 +1076,7 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(MEMCTRL, 0x61);
val = val >> 6;
i |= DDR2_Twr_table[val];
- read32(i);
+ read32((void *)i);
printk(BIOS_DEBUG, "MRS = %08x\n", i);
@@ -1085,9 +1085,9 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 19
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x103e00); //EMRS OCD Default
+ read32((void *)0x103e00); //EMRS OCD Default
else
- read32(0x103c20);
+ read32((void *)0x103c20);
}
static void sdram_set_vr(const struct mem_controller *ctrl, u8 num)
@@ -1133,45 +1133,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
u8 ca, ra, ba, reg;
ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
if (ba == 8) {
- write8(0, 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12_8bk), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09_8bk), 0x0c);
- ca = read8(0);
-
- write8(0, 0x03);
- ba = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- ba = read8(0);
+ write8((void *)0, 0x0d);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c);
+ ra = read8((void *)0);
+
+ write8((void *)0, 0x0a);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c);
+ ca = read8((void *)0);
+
+ write8((void *)0, 0x03);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+ ba = read8((void *)0);
} else {
- write8(0, 0x0f);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_14), 0x0e);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_13), 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0c);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_12), 0x0b);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_11), 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09), 0x09);
- ca = read8(0);
-
- write8(0, 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- ba = read8(0);
+ write8((void *)0, 0x0f);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_14), 0x0e);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_13), 0x0d);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_12), 0x0c);
+ ra = read8((void *)0);
+
+ write8((void *)0, 0x0c);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_12), 0x0b);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_11), 0x0a);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_09), 0x09);
+ ca = read8((void *)0);
+
+ write8((void *)0, 0x02);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1), 0x01);
+ ba = read8((void *)0);
}
if (ra < 10 || ra > 15)
@@ -1277,19 +1277,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
if (reg8) {
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32((void *)0, 0x55555555);
+ write32((void *)4, 0x55555555);
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)0) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)4) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32((void *)0, 0xaaaaaaaa);
+ write32((void *)4, 0xaaaaaaaa);
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)0) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)4) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1310,19 +1310,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32((void *)0, 0x55555555);
+ write32((void *)4, 0x55555555);
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)0) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)4) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32((void *)0, 0xaaaaaaaa);
+ write32((void *)4, 0xaaaaaaaa);
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)0) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)4) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1364,17 +1364,17 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
if (reg8 == 4) {
- write8(0, 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- val = read8(0);
+ write8((void *)0, 0x02);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1), 0x01);
+ val = read8((void *)0);
} else {
- write8(0, 0x03);
- val = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- val = read8(0);
+ write8((void *)0, 0x03);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+ val = read8((void *)0);
}
if (val < dl)
dl = val;
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index ac5e4c8..828d1d3 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -139,10 +139,10 @@ static void vx900_lpc_ioapic_setup(device_t dev)
/* The base address of this IOAPIC _must_ be at 0xfec00000.
* Don't move this value to a #define, as people might think it's
* configurable. It is not. */
- const u32 base = config->base;
- if (base != 0xfec00000) {
+ const void *base = config->base;
+ if (base != (void *)0xfec00000) {
printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at "
- "0xfec00000\n but we found it at 0x%.8x\n", base);
+ "0xfec00000\n but we found it at %p\n", base);
return;
}
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index 2e73ea4..001d7e7 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -80,24 +80,24 @@ static void vx900_north_ioapic_setup(device_t dev)
* be between 0xfec00000 and 0xfecfff00
* be 256-byte aligned
*/
- if ((config->base < 0xfec0000 || config->base > 0xfecfff00)
- || ((config->base & 0xff) != 0)) {
+ if ((config->base < (void *)0xfec0000 || config->base > (void *)0xfecfff00)
+ || (((uintptr_t)config->base & 0xff) != 0)) {
printk(BIOS_ERR, "ERROR: North module IOAPIC base should be "
"between 0xfec00000 and 0xfecfff00\n"
"and must be aligned to a 256-byte boundary, "
- "but we found it at 0x%.8x\n", config->base);
+ "but we found it at 0x%p\n", config->base);
return;
}
printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC "
- "at 0%.8x\n", config->base);
+ "at %p\n", config->base);
/* First register of the IOAPIC base */
- base_val = (config->base >> 8) & 0xff;
+ base_val = (((uintptr_t)config->base) >> 8) & 0xff;
pci_write_config8(dev, 0x41, base_val);
/* Second register of the base.
* Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */
- base_val = (config->base >> 16) & 0xf;
+ base_val = (((uintptr_t)config->base) >> 16) & 0xf;
pci_mod_config8(dev, 0x40, 0, base_val | (1 << 7) | (1 << 5));
}
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index aae0c99..cefc215 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -106,7 +106,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
static int acpi_sci_irq(void)
{
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
int scis;
static int sci_irq;
diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h
index 09e45a1..820d32e 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/baytrail/gpio.h
@@ -345,20 +345,20 @@ struct soc_gpio_config* mainboard_get_gpios(void);
#define PCU_SMB_CLK_PAD 88
#define PCU_SMB_DATA_PAD 90
-static inline unsigned int score_pconf0(int pad_num)
+static inline u32 *score_pconf0(int pad_num)
{
- return GPSCORE_PAD_BASE + pad_num * 16;
+ return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16);
}
-static inline unsigned int ssus_pconf0(int pad_num)
+static inline u32 *ssus_pconf0(int pad_num)
{
- return GPSSUS_PAD_BASE + pad_num * 16;
+ return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16);
}
static inline void score_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = score_pconf0(pad);
+ uint32_t *pconf0_addr = score_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -369,7 +369,7 @@ static inline void score_select_func(int pad, int func)
static inline void ssus_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = ssus_pconf0(pad);
+ uint32_t *pconf0_addr = ssus_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -380,14 +380,14 @@ static inline void ssus_select_func(int pad, int func)
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
- uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
- uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 4cce877..5b57cc3 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -59,7 +59,7 @@ static void gfx_lock_pcbase(device_t dev)
pcbase += (gmsize-1) * wopcmsz - pcsize;
pcbase |= 1; /* Lock */
- write32(res->base + 0x182120, pcbase);
+ write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase);
}
static const struct reg_script gfx_init_script[] = {
@@ -308,7 +308,7 @@ static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
divider = 25 * 1000 * 1000 / (16 * req_hz);
/* Do not set duty cycle (lower 16 bits). Just set the divider. */
- write32(res->base + bklt_reg, divider << 16);
+ write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);
}
static void gfx_panel_setup(device_t dev)
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 43e52ef..6a971ea 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -142,9 +142,9 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
reg, pad_conf0, config->pad_conf1, config->pad_val);
#endif
- write32(reg + PAD_CONF0_REG, pad_conf0);
- write32(reg + PAD_CONF1_REG, config->pad_conf1);
- write32(reg + PAD_VAL_REG, config->pad_val);
+ write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0);
+ write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1);
+ write32((u32 *)(reg + PAD_VAL_REG), config->pad_val);
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -198,7 +198,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
const struct gpio_bank *bank)
{
- u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
+ u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
u32 val;
int i;
@@ -206,10 +206,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
- write32(reg + i * 4, val);
+ write32(reg + i, val);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
- reg + i * 4, val);
+ reg + i, val);
#endif
}
}
@@ -233,8 +233,8 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
*/
if (!enable_xdp_tap) {
printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
- write32(GPSSUS_PAD_BASE + 0x2fc, 0xc);
- write32(GPSSUS_PAD_BASE + 0x2cc, 0xc);
+ write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc);
+ write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc);
}
}
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
index c5de654..75a35ec 100644
--- a/src/soc/intel/baytrail/hda.c
+++ b/src/soc/intel/baytrail/hda.c
@@ -83,6 +83,7 @@ static void hda_init(device_t dev)
struct resource *res;
int codec_mask;
int i;
+ u8 *base;
reg_script_run_on_dev(dev, init_ops);
@@ -90,7 +91,8 @@ static void hda_init(device_t dev)
if (res == NULL)
return;
- codec_mask = hda_codec_detect(res->base);
+ base = (u8 *)(uintptr_t)res->base;
+ codec_mask = hda_codec_detect(base);
printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
if (!codec_mask)
@@ -99,7 +101,7 @@ static void hda_init(device_t dev)
for (i = 3; i >= 0; i--) {
if (!((1 << i) & codec_mask))
continue;
- hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table),
+ hda_codec_init(base, i, sizeof(hdmi_codec_verb_table),
hdmi_codec_verb_table);
}
}
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index 2b07e2b..0834f4b 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -25,11 +25,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
- write32(IOSF_PCI_BASE + reg, value);
+ write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
- return read32(IOSF_PCI_BASE + reg);
+ return read32((u32 *)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 581f42b..bc467ea 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -90,7 +90,7 @@ static void lpe_enable_acpi_mode(device_t dev)
static void setup_codec_clock(device_t dev)
{
uint32_t reg;
- int clk_reg;
+ u32 *clk_reg;
struct soc_intel_baytrail_config *config;
const char *freq_str;
@@ -119,8 +119,8 @@ static void setup_codec_clock(device_t dev)
printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
- clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0;
- clk_reg += 4 * config->lpe_codec_clk_num;
+ clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
+ clk_reg += config->lpe_codec_clk_num;
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
@@ -144,8 +144,10 @@ static void lpe_stash_firmware_info(device_t dev)
/* C0 and later steppings use an offset in the MMIO space. */
if (pattrs->stepping >= STEP_C0) {
mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
- write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base);
- write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size);
+ write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
+ res->base);
+ write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
+ res->size);
}
}
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index aee3726..8295b69 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -355,10 +355,10 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
- prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
- write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
- write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+ write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
+ write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index b69b532..72ed6f7 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -98,8 +98,8 @@ static void program_base_addresses(void)
static void spi_init(void)
{
- const unsigned long scs = SPI_BASE_ADDRESS + SCS;
- const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
+ u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
+ u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
@@ -190,9 +190,9 @@ static struct chipset_power_state *fill_power_state(void)
ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
- ps->prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- ps->gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
- ps->gen_pmcon2 = read32(PMC_BASE_ADDRESS + GEN_PMCON2);
+ ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
+ ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
+ ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2));
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index 28a2f8c..bed57c7 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -92,7 +92,7 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, 0x92, reg16);
if (config->sata_ahci) {
- u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
/* Enable CR memory space decoding */
reg16 = pci_read_config16(dev, 0x04);
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index daf759d..9349dfa 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -66,7 +66,7 @@ void southcluster_smm_clear_state(void)
static void southcluster_smm_route_gpios(void)
{
- const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
+ u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
uint32_t alt_gpio_reg = 0;
uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 5274b03..d0569b4 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -134,7 +134,7 @@ static void sc_rtc_init(void)
if (ps != NULL) {
gen_pmcon1 = ps->gen_pmcon1;
} else {
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
}
rtc_fail = !!(gen_pmcon1 & RPS);
@@ -185,20 +185,20 @@ static void com1_configure_resume(device_t dev)
static void sc_init(device_t dev)
{
int i;
- const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
- const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
- const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1;
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
+ u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20;
+ u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1);
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
struct soc_intel_baytrail_config *config = dev->chip_info;
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++) {
- write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+ write8(pr_base + i, ir->pic[i]);
}
/* Set up the per device PIRQ routing base on static config. */
for (i = 0; i < NUM_IR_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir_base + i, ir->pcidev[i]);
}
/* Route SCI to IRQ9 */
@@ -226,8 +226,8 @@ static void sc_init(device_t dev)
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(device_t dev)
{
- const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
- const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+ u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
+ u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t mask = 0;
uint32_t mask2 = 0;
@@ -347,7 +347,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
* the audio paths work for LPE audio. */
static void hda_work_around(device_t dev)
{
- unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
+ u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
@@ -534,11 +534,11 @@ int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg)
static void finalize_chipset(void *unused)
{
- const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
- const unsigned long gcs = RCBA_BASE_ADDRESS + GCS;
- const unsigned long gen_pmcon2 = PMC_BASE_ADDRESS + GEN_PMCON2;
- const unsigned long etr = PMC_BASE_ADDRESS + ETR;
- const unsigned long spi = SPI_BASE_ADDRESS;
+ u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
+ u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS);
+ u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2);
+ u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR);
+ u8 *spi = (u8 *)SPI_BASE_ADDRESS;
struct spi_config cfg;
/* Set the lock enable on the BIOS control register. */
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 8605dfc..a83fb8e 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -196,33 +196,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 394a9d7..54123f4 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -53,7 +53,7 @@ static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
@@ -62,13 +62,13 @@ static void pch_enable_ioapic(struct device *dev)
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c
index 6404ee2..dd61793 100644
--- a/src/soc/intel/common/hda_verb.c
+++ b/src/soc/intel/common/hda_verb.c
@@ -27,7 +27,7 @@
/**
* Set bits in a register and wait for status
*/
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
/**
* Probe for supported codecs
*/
-int hda_codec_detect(u32 base)
+int hda_codec_detect(u8 *base)
{
u8 reg8;
@@ -90,7 +90,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int hda_wait_for_ready(u32 base)
+static int hda_wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -112,7 +112,7 @@ static int hda_wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int hda_wait_for_valid(u32 base)
+static int hda_wait_for_valid(u8 *base)
{
u32 reg32;
@@ -184,7 +184,7 @@ static u32 hda_find_verb(u32 verb_table_bytes,
/**
* Write a supplied verb table
*/
-int hda_codec_write(u32 base, u32 size, const u32 *data)
+int hda_codec_write(u8 *base, u32 size, const u32 *data)
{
int i;
@@ -204,7 +204,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
/**
* Initialize codec, then find the verb table and write it
*/
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data)
{
const u32 *verb;
u32 reg32, size;
diff --git a/src/soc/intel/common/hda_verb.h b/src/soc/intel/common/hda_verb.h
index a9c93c6..e062f28 100644
--- a/src/soc/intel/common/hda_verb.h
+++ b/src/soc/intel/common/hda_verb.h
@@ -32,8 +32,8 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-int hda_codec_detect(u32 base);
-int hda_codec_write(u32 base, u32 size, const u32 *data);
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
+int hda_codec_detect(u8 *base);
+int hda_codec_write(u8 *base, u32 size, const u32 *data);
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data);
#endif /* _COMMON_HDA_VERB_H_ */
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index fb0dc87..11c4493 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -105,7 +105,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
static int acpi_sci_irq(void)
{
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
int scis;
static int sci_irq;
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index e13b663..1aa64d0 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -339,20 +339,20 @@ void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
#define PCU_SMB_CLK_PAD 88
#define PCU_SMB_DATA_PAD 90
-static inline unsigned int score_pconf0(int pad_num)
+static inline uint32_t *score_pconf0(int pad_num)
{
- return GPSCORE_PAD_BASE + pad_num * 16;
+ return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16);
}
-static inline unsigned int ssus_pconf0(int pad_num)
+static inline uint32_t *ssus_pconf0(int pad_num)
{
- return GPSSUS_PAD_BASE + pad_num * 16;
+ return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16);
}
static inline void score_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = score_pconf0(pad);
+ uint32_t *pconf0_addr = score_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -363,7 +363,7 @@ static inline void score_select_func(int pad, int func)
static inline void ssus_select_func(int pad, int func)
{
uint32_t reg;
- uint32_t pconf0_addr = ssus_pconf0(pad);
+ uint32_t *pconf0_addr = ssus_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -376,14 +376,14 @@ static inline void ssus_select_func(int pad, int func)
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
- uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
- uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
+ uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index e8f5572..843e741 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -63,7 +63,7 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
*/
static void enable_spi_prefetch(void)
{
- uint32_t bcr = SPI_BASE_ADDRESS + BCR;
+ u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
/* Enable caching and prefetching in the SPI controller. */
write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH);
}
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index aeb0998..ee62d78 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -99,7 +99,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
{
const struct soc_gpio_map *config;
int gpio = 0;
- u32 reg, pad_conf0;
+ u32 reg, pad_conf0, *regmmio;
u8 set, bit;
u32 use_sel[4] = {0};
@@ -134,7 +134,8 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
/* Pad configuration registers */
- reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
+ regmmio = (u32 *)(bank->pad_base + 16 *
+ bank->gpio_to_pad[gpio]);
/* Add correct func to GPIO pad config */
pad_conf0 = config->pad_conf0;
@@ -148,13 +149,14 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
#ifdef GPIO_DEBUG
- printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
- reg, pad_conf0, config->pad_conf1, config->pad_val);
+ printk(BIOS_DEBUG, "Write Pad: Base(%p) - %x %x %x\n",
+ regmmio, pad_conf0, config->pad_conf1, config->pad_val);
#endif
- write32(reg + PAD_CONF0_REG, pad_conf0);
- write32(reg + PAD_CONF1_REG, config->pad_conf1);
- write32(reg + PAD_VAL_REG, config->pad_val);
+ write32(regmmio + (PAD_CONF0_REG/sizeof(u32)), pad_conf0);
+ write32(regmmio + (PAD_CONF1_REG/sizeof(u32)),
+ config->pad_conf1);
+ write32(regmmio + (PAD_VAL_REG/sizeof(u32)), config->pad_val);
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -211,7 +213,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
const struct gpio_bank *bank)
{
- u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
+ u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
u32 val;
int i;
@@ -219,10 +221,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
- write32(reg + i * 4, val);
+ write32(reg + i, val);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
- reg + i * 4, val);
+ reg + i, val);
#endif
}
}
@@ -295,7 +297,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
uint32_t pconf0, uint32_t pad_val)
{
uint32_t reg;
- uint32_t pad_addr;
+ uint32_t *pad_addr;
if (ssus_gpio)
pad_addr = ssus_pconf0(gpssus_gpio_to_pad[gpio_num]);
else
@@ -317,7 +319,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
*/
reg = PAD_CONFIG0_DEFAULT;
reg |= pconf0 & 0x787;
- write32(pad_addr + PAD_CONF0_REG, reg);
+ write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg);
/*
* Pad Value Register
@@ -325,10 +327,10 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
* 1: output enable (0 is enabled)
* 2: input enable (0 is enabled)
*/
- reg = read32(pad_addr + PAD_VAL_REG);
+ reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32)));
reg &= ~0x7;
reg |= pad_val & 0x7;
- write32(pad_addr + PAD_VAL_REG, reg);
+ write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg);
}
/** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO
diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c
index f892b20..eee7c64 100644
--- a/src/soc/intel/fsp_baytrail/iosf.c
+++ b/src/soc/intel/fsp_baytrail/iosf.c
@@ -29,11 +29,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
- write32(IOSF_PCI_BASE + reg, value);
+ write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
- return read32(IOSF_PCI_BASE + reg);
+ return read32((u32 *)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index aee3726..8295b69 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -355,10 +355,10 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
- prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
- write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
- write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+ write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
+ write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 2619c96..653e039 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -57,7 +57,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
/* Read Power State */
pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
pm1_sts, pm1_cnt, gen_pmcon1);
@@ -119,8 +119,8 @@ static void program_base_addresses(void)
static void spi_init(void)
{
- const uint32_t scs = SPI_BASE_ADDRESS + SCS;
- const uint32_t bcr = SPI_BASE_ADDRESS + BCR;
+ uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS);
+ uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
@@ -136,8 +136,8 @@ static void spi_init(void)
static void baytrail_rtc_init(void)
{
- uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0;
- uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+ uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0);
+ uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32)));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
@@ -145,7 +145,7 @@ static void baytrail_rtc_init(void)
"RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
- write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+ write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
@@ -154,8 +154,8 @@ static void baytrail_rtc_init(void)
/* Entry from cache-as-ram.inc. */
void main(FSP_INFO_HEADER *fsp_info_header)
{
- const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
- const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+ uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS);
+ uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t fd_mask = 0;
uint32_t fd2_mask = 0;
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index d4b3d58..2a8892d 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -67,7 +67,7 @@ void southcluster_smm_clear_state(void)
static void southcluster_smm_route_gpios(void)
{
- const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
+ u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
uint32_t alt_gpio_reg = 0;
uint32_t route_reg = gpio_route;
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index d87935b..3f61934 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -82,17 +82,17 @@ static void sc_enable_ioapic(struct device *dev)
{
int i;
u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
- volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
- u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f;
+ volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR);
+ volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10);
+ u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/*
* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/
- write32(ilb_base + ILB_OIC, 0x100); /* AEN */
- reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
- write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
+ write32(ilb_base + (ILB_OIC/sizeof(u32)), 0x100); /* AEN */
+ reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */
+ write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0;
*ioapic_data = (1 << 25);
@@ -131,7 +131,7 @@ static void sc_enable_serial_irqs(struct device *dev)
* until we understand how it needs to be configured.
*/
u8 reg8;
- u32 ibase = pci_read_config32(dev, IBASE) & ~0xF;
+ u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
/*
* Disable the IOCHK# NMI. Let the NMI handler enable it if it needs.
@@ -259,9 +259,9 @@ static void sc_pirq_init(device_t dev)
{
int i, j;
int pirq;
- const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
- const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
- const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
+ u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
+ u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20);
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
/* Set up the PIRQ PIC routing based on static config. */
@@ -269,7 +269,7 @@ static void sc_pirq_init(device_t dev)
"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
"IRQ ");
for (i = 0; i < NUM_PIRQS; i++) {
- write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+ write8(pr_base + i, ir->pic[i]);
printk(BIOS_SPEW, "\t%d", ir->pic[i]);
}
printk(BIOS_SPEW, "\n\n");
@@ -278,7 +278,7 @@ static void sc_pirq_init(device_t dev)
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
@@ -372,11 +372,11 @@ static void enable_hpet(void)
static void sc_init(struct device *dev)
{
- u32 ibase;
+ u8 *ibase;
printk(BIOS_DEBUG, "soc: southcluster_init\n");
- ibase = pci_read_config32(dev, IBASE) & ~0xF;
+ ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
write8(ibase + ILB_MC, 0);
@@ -411,8 +411,8 @@ static void sc_init(struct device *dev)
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(device_t dev)
{
- const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
- const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
+ u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
+ u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t fd_mask = 0;
uint32_t fd2_mask = 0;
@@ -471,7 +471,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
* the audio paths work for LPE audio. */
static void hda_work_around(device_t dev)
{
- unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
+ u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 0c3c63d..abcc62c 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -193,33 +193,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 258267e..d8a49b3 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -40,15 +40,15 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
- u32 base_regs = pci_ehci_base_regs(dev);
+ u32 *base_regs = (u32 *)pci_ehci_base_regs(dev);
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
+ reg32 = read32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)));
reg32 &= ~(0xf << 28);
reg32 |= (port << 28);
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32);
}
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index be8aa69..cb2b4e4 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -64,22 +64,22 @@ void backup_top_of_ram(uint64_t ramtop)
void pm_write8(u8 reg, u8 value)
{
- write8(PM_MMIO_BASE + reg, value);
+ write8((void *)(PM_MMIO_BASE + reg), value);
}
u8 pm_read8(u8 reg)
{
- return read8(PM_MMIO_BASE + reg);
+ return read8((void *)(PM_MMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
- write16(PM_MMIO_BASE + reg, value);
+ write16((void *)(PM_MMIO_BASE + reg), value);
}
u16 pm_read16(u16 reg)
{
- return read16(PM_MMIO_BASE + reg);
+ return read16((void *)(PM_MMIO_BASE + reg));
}
#define PM_REG_USB_ENABLE 0xef
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index d706292..0493009 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -31,18 +31,18 @@ void imc_reg_init(void)
{
/* Init Power Management Block 2 (PM2) Registers.
* Check BKDG for AMD Family 16h for details. */
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x00), 0x06);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x01), 0x06);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x02), 0xf7);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x03), 0xff);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x04), 0xff);
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x10), 0x06);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x11), 0x06);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x12), 0xf7);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x13), 0xff);
+ write8((void *)(ACPI_MMIO_BASE + PMIO2_BASE + 0x14), 0xff);
#endif
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index d6ca215..0df045a 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -82,7 +82,7 @@
static void sm_init(device_t dev)
{
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+ setup_ioapic((void *)IO_APIC_ADDR, CONFIG_MAX_CPUS);
}
static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h
index 53da00a..520c65f 100644
--- a/src/southbridge/amd/agesa/hudson/smi.h
+++ b/src/southbridge/amd/agesa/hudson/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
static inline uint32_t smi_read32(uint8_t offset)
{
- return read32(SMI_BASE + offset);
+ return read32((void *)(SMI_BASE + offset));
}
static inline void smi_write32(uint8_t offset, uint32_t value)
{
- write32(SMI_BASE + offset, value);
+ write32((void *)(SMI_BASE + offset), value);
}
static inline uint16_t smi_read16(uint8_t offset)
{
- return read16(SMI_BASE + offset);
+ return read16((void *)(SMI_BASE + offset));
}
static inline void smi_write16(uint8_t offset, uint16_t value)
{
- write16(SMI_BASE + offset, value);
+ write16((void *)(SMI_BASE + offset), value);
}
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 735ab7e..fe6ea50 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -53,12 +53,12 @@ static u32 spibar;
static inline uint8_t spi_read(uint8_t reg)
{
- return read8(spibar + reg);
+ return read8((void *)(spibar + reg));
}
static inline void spi_write(uint8_t reg, uint8_t val)
{
- write8(spibar + reg, val);
+ write8((void *)(spibar + reg), val);
}
static void reset_internal_fifo_pointer(void)
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 718b40b..829eff7 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -42,7 +42,7 @@ static void lpc_init(struct device *dev)
byte |= 1;
pci_write_config8(dev, 0x4B, byte);
/* Don't rename IO APIC */
- setup_ioapic(IO_APIC_ADDR, 0);
+ setup_ioapic((void *)IO_APIC_ADDR, 0);
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index 5352705..253448c 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -11,7 +11,7 @@
#include "amd8111.h"
-#define CMD3 0x54
+#define CMD3 (0x54/(sizeof(u32)))
typedef enum {
VAL3 = (1 << 31), /* VAL bit for byte 3 */
@@ -45,11 +45,11 @@ static void nic_init(struct device *dev)
{
struct southbridge_amd_amd8111_config *conf;
struct resource *resource;
- unsigned long mmio;
+ u32 *mmio;
conf = dev->chip_info;
resource = find_resource(dev, PCI_BASE_ADDRESS_0);
- mmio = resource->base;
+ mmio = (u32 *)(uintptr_t)resource->base;
/* Hard Reset PHY */
printk(BIOS_DEBUG, "Resetting PHY... ");
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 9c70482..439ebb6 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -237,12 +237,12 @@ static void sb700_enable(device_t dev)
u32 ioapic_base;
printk(BIOS_DEBUG, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
- clear_ioapic(ioapic_base);
+ clear_ioapic((void *)ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
if (CONFIG_MAX_CPUS >= 16)
- setup_ioapic(ioapic_base, 0);
+ setup_ioapic((void *)ioapic_base, 0);
else
- setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
+ setup_ioapic((void *)ioapic_base, CONFIG_MAX_CPUS + 1);
}
break;
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 9c4047f..995bde6 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -408,18 +408,18 @@ static void sb800_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
printk(BIOS_INFO, "sm_init().\n");
- clear_ioapic(IO_APIC_ADDR);
+ clear_ioapic((void *)IO_APIC_ADDR);
#if CONFIG_CPU_AMD_AGESA
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+ setup_ioapic((void *)IO_APIC_ADDR, CONFIG_MAX_CPUS);
#else
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+ setup_ioapic((void *)IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
- setup_ioapic(IO_APIC_ADDR, 0);
+ setup_ioapic((void *)IO_APIC_ADDR, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index c84eee2..48820bc 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -40,15 +40,17 @@ static u32 spibar;
static void reset_internal_fifo_pointer(void)
{
do {
- write8(spibar + 2, read8(spibar + 2) | 0x10);
- } while (read8(spibar + 0xD) & 0x7);
+ write8((void *)(spibar + 2),
+ read8((void *)(spibar + 2)) | 0x10);
+ } while (read8((void *)(spibar + 0xD)) & 0x7);
}
static void execute_command(void)
{
- write8(spibar + 2, read8(spibar + 2) | 1);
+ write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
- while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
+ while ((read8((void *)(spibar + 2)) & 1) &&
+ (read8((void *)(spibar+3)) & 0x80));
}
void spi_init()
@@ -91,12 +93,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
readwrite = (bytesin + readoffby1) << 4 | bytesout;
- write8(spibar + 1, readwrite);
- write8(spibar + 0, cmd);
+ write8((void *)(spibar + 1), readwrite);
+ write8((void *)(spibar + 0), cmd);
reset_internal_fifo_pointer();
for (count = 0; count < bytesout; count++, dout++) {
- write8(spibar + 0x0C, *(u8 *)dout);
+ write8((void *)(spibar + 0x0C), *(u8 *)dout);
}
reset_internal_fifo_pointer();
@@ -105,12 +107,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
reset_internal_fifo_pointer();
/* Skip the bytes we sent. */
for (count = 0; count < bytesout; count++) {
- cmd = read8(spibar + 0x0C);
+ cmd = read8((void *)(spibar + 0x0C));
}
reset_internal_fifo_pointer();
for (count = 0; count < bytesin; count++, din++) {
- *(u8 *)din = read8(spibar + 0x0C);
+ *(u8 *)din = read8((void *)(spibar + 0x0C));
}
return 0;
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 3d873d0..da79a67 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -429,7 +429,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
- u32 bar;
+ void *bar;
msr_t msr;
device_t dev;
@@ -445,7 +445,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
/* write to clear diag register */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writable */
write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
@@ -457,7 +457,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
@@ -485,7 +485,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev,
+ PCI_BASE_ADDRESS_0);
write32(bar + UDCDEVCTL,
read32(bar + UDCDEVCTL) | UDC_SD_SET);
@@ -494,7 +495,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ bar = (void *)pci_read_config32(dev,
+ PCI_BASE_ADDRESS_0);
write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
}
diff --git a/src/southbridge/amd/pi/avalon/hudson.c b/src/southbridge/amd/pi/avalon/hudson.c
index 84eaf30..6aefa79 100644
--- a/src/southbridge/amd/pi/avalon/hudson.c
+++ b/src/southbridge/amd/pi/avalon/hudson.c
@@ -63,22 +63,22 @@ void backup_top_of_ram(uint64_t ramtop)
void pm_write8(u8 reg, u8 value)
{
- write8(PM_MMIO_BASE + reg, value);
+ write8((void *)(PM_MMIO_BASE + reg), value);
}
u8 pm_read8(u8 reg)
{
- return read8(PM_MMIO_BASE + reg);
+ return read8((void *)(PM_MMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
- write16(PM_MMIO_BASE + reg, value);
+ write16((void *)(PM_MMIO_BASE + reg), value);
}
u16 pm_read16(u16 reg)
{
- return read16(PM_MMIO_BASE + reg);
+ return read16((void *)(PM_MMIO_BASE + reg));
}
void hudson_enable(device_t dev)
diff --git a/src/southbridge/amd/pi/avalon/sm.c b/src/southbridge/amd/pi/avalon/sm.c
index d6ca215..0df045a 100644
--- a/src/southbridge/amd/pi/avalon/sm.c
+++ b/src/southbridge/amd/pi/avalon/sm.c
@@ -82,7 +82,7 @@
static void sm_init(device_t dev)
{
- setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+ setup_ioapic((void *)IO_APIC_ADDR, CONFIG_MAX_CPUS);
}
static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/pi/avalon/smi.h b/src/southbridge/amd/pi/avalon/smi.h
index de987a9..2296c6e 100644
--- a/src/southbridge/amd/pi/avalon/smi.h
+++ b/src/southbridge/amd/pi/avalon/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
static inline uint32_t smi_read32(uint8_t offset)
{
- return read32(SMI_BASE + offset);
+ return read32((void *)(SMI_BASE + offset));
}
static inline void smi_write32(uint8_t offset, uint32_t value)
{
- write32(SMI_BASE + offset, value);
+ write32((void *)(SMI_BASE + offset), value);
}
static inline uint16_t smi_read16(uint8_t offset)
{
- return read16(SMI_BASE + offset);
+ return read16((void *)(SMI_BASE + offset));
}
static inline void smi_write16(uint8_t offset, uint16_t value)
{
- write16(SMI_BASE + offset, value);
+ write16((void *)(SMI_BASE + offset), value);
}
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index c65f324..5ef7991 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
{
u32 dword;
@@ -172,7 +172,7 @@ static u32 find_verb(u32 viddid, u32 ** verb)
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -194,7 +194,7 @@ static int wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -211,7 +211,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
{
u32 dword;
u32 *verb;
@@ -253,7 +253,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "verb loaded!\n");
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -266,7 +266,7 @@ static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
- u32 base;
+ void *base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
@@ -300,8 +300,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "base = 0x%x\n", base);
+ base = (void *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index a17aab8..2ff7182 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -63,7 +63,7 @@ static void sata_init(struct device *dev)
u8 byte;
u16 word;
u32 dword;
- u32 sata_bar5;
+ void *sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
@@ -88,7 +88,7 @@ static void sata_init(struct device *dev)
pci_write_config8(sm_dev, 0xaf, byte);
/* get base address */
- sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -100,7 +100,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
- printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
+ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* SERR-Enable */
word = pci_read_config16(dev, 0x04);
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index a8e72c2..3ce5f02 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -57,7 +57,7 @@ static void sm_init(device_t dev)
ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
/* Don't rename APIC ID */
- clear_ioapic(ioapic_base);
+ clear_ioapic((void *)ioapic_base);
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index 137a8da..1b2b9ff 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -88,13 +88,13 @@ static void usb_init2(struct device *dev)
u8 byte;
u16 word;
u32 dword;
- u32 usb2_bar0;
+ void *usb2_bar0;
/* dword = pci_read_config32(dev, 0xf8); */
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
- usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
- printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+ printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 308b08c..6e3077c 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
{
u32 dword;
@@ -94,7 +94,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -116,7 +116,7 @@ static int wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -133,7 +133,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
{
u32 dword;
@@ -153,7 +153,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -166,7 +166,7 @@ static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
- u32 base;
+ void *base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
@@ -202,8 +202,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "base = 0x%x\n", base);
+ base = (void *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 7fa924b..9df6d48 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -82,7 +82,7 @@ static void sata_init(struct device *dev)
u16 word;
u32 dword;
u8 rev_id;
- u32 sata_bar5;
+ void *sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
@@ -108,7 +108,7 @@ static void sata_init(struct device *dev)
rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
/* get base address */
- sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -120,7 +120,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
- printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
+ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* disable combined mode */
byte = pci_read_config8(sm_dev, 0xAD);
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 5aa4eb1..1db637b 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -50,14 +50,14 @@ static void sm_init(device_t dev)
u8 byte_old;
u8 rev;
u32 dword;
- u32 ioapic_base;
+ void *ioapic_base;
u32 on;
u32 nmi_option;
printk(BIOS_INFO, "sm_init().\n");
rev = get_sb700_revision(dev);
- ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
+ ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); /* some like mem resource, but does not have enable bit */
/* Don't rename APIC ID */
/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
* We need to check out why and change back. */
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index 77dcf2e..dd8b390 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -81,7 +81,7 @@ static void usb_init(struct device *dev)
static void usb_init2(struct device *dev)
{
u32 dword;
- u32 usb2_bar0;
+ void *usb2_bar0;
device_t sm_dev;
u8 rev;
@@ -92,8 +92,8 @@ static void usb_init2(struct device *dev)
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
- usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
- printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+ printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
index 5265684..dd8f342 100644
--- a/src/southbridge/amd/sb800/hda.c
+++ b/src/southbridge/amd/sb800/hda.c
@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
{
u32 dword;
@@ -96,7 +96,7 @@ no_codec:
* Wait 50usec for for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -118,7 +118,7 @@ static int wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -135,7 +135,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
{
u32 dword;
@@ -155,7 +155,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -167,7 +167,7 @@ static void codecs_init(u32 base, u32 codec_mask)
static void hda_init(struct device *dev)
{
u32 dword;
- u32 base;
+ void *base;
struct resource *res;
u32 codec_mask;
@@ -183,8 +183,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "base = 0x%x\n", base);
+ base = (void *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index a1aa6e0..cb685d1 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -82,7 +82,7 @@ static void sata_init(struct device *dev)
u16 word;
u32 dword;
u8 rev_id;
- u32 sata_bar5;
+ void *sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
@@ -98,7 +98,7 @@ static void sata_init(struct device *dev)
rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F;
/* get base address */
- sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+ sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -110,7 +110,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
- printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
+ printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
/* SERR-Enable */
word = pci_read_config16(dev, 0x04);
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 662a82e..f2ef74a 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -89,7 +89,7 @@ static void sm_init(device_t dev)
/* Don't rename APIC ID */
/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
* We need to check out why and change back. */
- clear_ioapic(IO_APIC_ADDR);
+ clear_ioapic((void *)IO_APIC_ADDR);
//setup_ioapic(IO_APIC_ADDR, 0);
/* enable serial irq */
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index 55be7b8..9cd6397 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -58,7 +58,7 @@ static void usb_init(struct device *dev)
static void usb_init2(struct device *dev)
{
u32 dword;
- u32 usb2_bar0;
+ void *usb2_bar0;
device_t sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -68,8 +68,8 @@ static void usb_init2(struct device *dev)
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
- usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
- printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+ usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+ printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
/* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index 737eed2..816800f 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -128,7 +128,7 @@ static void sr5690_apic_init(struct device *dev)
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
/* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the
* 2nd one. We need to check if it also is on your board. */
- setup_ioapic(dword, 1);
+ setup_ioapic((void *)dword, 1);
}
static void pcie_init(struct device *dev)
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 62eab45..dc389f9 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -31,9 +31,9 @@ static void sata_init(struct device *dev)
{
uint8_t byte;
- u32 mmio;
+ u8 *mmio;
struct resource *res;
- u32 mmio_base;
+ u32 *mmio_base;
int i;
if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
@@ -42,24 +42,23 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, 0x78, byte);
res = find_resource(dev, 0x24);
- mmio_base = res->base;
- mmio_base &= 0xfffffffc;
+ mmio_base = (u32 *)(uintptr_t)(res->base & 0xfffffffc);
- write32(mmio_base + 0x10f0, 0x40000001);
- write32(mmio_base + 0x8c, 0x00ff2007);
+ write32(mmio_base + (0x10f0/sizeof(u32)), 0x40000001);
+ write32(mmio_base + (0x8c/sizeof(u32)), 0x00ff2007);
mdelay( 10 );
- write32(mmio_base + 0x8c, 0x78592009);
+ write32(mmio_base + (0x8c/sizeof(u32)), 0x78592009);
mdelay( 10 );
- write32(mmio_base + 0x8c, 0x00082004);
+ write32(mmio_base + (0x8c/sizeof(u32)), 0x00082004);
mdelay( 10 );
- write32(mmio_base + 0x8c, 0x00002004);
+ write32(mmio_base + (0x8c/sizeof(u32)), 0x00002004);
mdelay( 10 );
//init PHY
printk(BIOS_DEBUG, "init PHY...\n");
for(i=0; i<4; i++) {
- mmio = res->base + 0x100 * i;
+ mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
byte = read8(mmio + 0x40);
printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
if(byte & 0x4) {// bit 2 is set
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index bef88ab..d5d4273 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -35,7 +35,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -64,19 +64,20 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(base + (0x0 / sizeof(u32)),
+ read16(base + (0x0 / sizeof(u32))));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + 0xe);
+ reg8 = read8(base + (0xe / sizeof(u32)));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -86,7 +87,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
@@ -114,14 +115,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -136,20 +137,20 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(base + (HDA_ICII_REG / sizeof(u32)), reg32);
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -159,7 +160,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -175,14 +176,14 @@ static void codec_init(struct device *dev, u32 base, int addr)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n");
return;
}
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -199,7 +200,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -207,7 +208,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -219,7 +220,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(base + (0x60 / sizeof(u32)), pc_beep_verbs[i]);
if (wait_for_valid(base) == -1)
return;
@@ -228,7 +229,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -242,7 +243,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = (u32 *)(uintptr_t)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c
index 0863f34..e739c36 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_native.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_native.c
@@ -37,7 +37,7 @@
static void
wait_2338 (void)
{
- while (read8 (DEFAULT_RCBA | 0x2338) & 1);
+ while (read8((void *)(DEFAULT_RCBA | 0x2338)) & 1);
}
static u32
@@ -45,13 +45,13 @@ read_2338 (u32 edx)
{
u32 ret;
- write32 (DEFAULT_RCBA | 0x2330, edx);
- write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
- & 0x1ff) | 0x600);
+ write32((void *)(DEFAULT_RCBA | 0x2330), edx);
+ write16((void *)(DEFAULT_RCBA | 0x2338),
+ (read16((void *)(DEFAULT_RCBA | 0x2338)) & 0x1ff) | 0x600);
wait_2338 ();
- ret = read32 (DEFAULT_RCBA | 0x2334);
+ ret = read32((void *)(DEFAULT_RCBA | 0x2334));
wait_2338 ();
- read8 (DEFAULT_RCBA | 0x2338);
+ read8((void *)(DEFAULT_RCBA | 0x2338));
return ret;
}
@@ -59,15 +59,15 @@ static void
write_2338 (u32 edx, u32 val)
{
read_2338 (edx);
- write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
- & 0x1ff) | 0x600);
+ write16((void *)(DEFAULT_RCBA | 0x2338),
+ (read16((void *)(DEFAULT_RCBA | 0x2338)) & 0x1ff) | 0x600);
wait_2338 ();
- write32 (DEFAULT_RCBA | 0x2334, val);
+ write32((void *)(DEFAULT_RCBA | 0x2334), val);
wait_2338 ();
- write16 (DEFAULT_RCBA | 0x2338,
- (read16 (DEFAULT_RCBA | 0x2338) & 0x1ff) | 0x600);
- read8 (DEFAULT_RCBA | 0x2338);
+ write16((void *)(DEFAULT_RCBA | 0x2338),
+ (read16((void *)(DEFAULT_RCBA | 0x2338)) & 0x1ff) | 0x600);
+ read8((void *)(DEFAULT_RCBA | 0x2338));
}
@@ -76,214 +76,214 @@ init_dmi (void)
{
int i;
- write32 (DEFAULT_DMIBAR | 0x0914,
- read32 (DEFAULT_DMIBAR | 0x0914) | 0x80000000);
- write32 (DEFAULT_DMIBAR | 0x0934,
- read32 (DEFAULT_DMIBAR | 0x0934) | 0x80000000);
+ write32((void *)(DEFAULT_DMIBAR | 0x0914),
+ read32((void *)(DEFAULT_DMIBAR | 0x0914)) | 0x80000000);
+ write32((void *)(DEFAULT_DMIBAR | 0x0934),
+ read32((void *)(DEFAULT_DMIBAR | 0x0934)) | 0x80000000);
for (i = 0; i < 4; i++)
{
- write32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4),
- read32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4)) & 0xf3ffffff);
- write32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4),
- read32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4)) | 0x800);
+ write32((void *)(DEFAULT_DMIBAR | 0x0a00 | (i << 4)),
+ read32((void *)(DEFAULT_DMIBAR | 0x0a00 | (i << 4))) & 0xf3ffffff);
+ write32((void *)(DEFAULT_DMIBAR | 0x0a04 | (i << 4)),
+ read32((void *)(DEFAULT_DMIBAR | 0x0a04 | (i << 4))) | 0x800);
}
- write32 (DEFAULT_DMIBAR | 0x0c30, (read32 (DEFAULT_DMIBAR | 0x0c30)
- & 0xfffffff) | 0x40000000);
+ write32((void *)(DEFAULT_DMIBAR | 0x0c30),
+ (read32((void *)(DEFAULT_DMIBAR | 0x0c30)) & 0xfffffff) | 0x40000000);
for (i = 0; i < 2; i++)
{
- write32 (DEFAULT_DMIBAR | 0x0904 | (i << 5),
- read32 (DEFAULT_DMIBAR | 0x0904 | (i << 5)) & 0xfe3fffff);
- write32 (DEFAULT_DMIBAR | 0x090c | (i << 5),
- read32 (DEFAULT_DMIBAR | 0x090c | (i << 5)) & 0xfff1ffff);
+ write32((void *)(DEFAULT_DMIBAR | 0x0904 | (i << 5)),
+ read32((void *)(DEFAULT_DMIBAR | 0x0904 | (i << 5))) & 0xfe3fffff);
+ write32((void *)(DEFAULT_DMIBAR | 0x090c | (i << 5)),
+ read32((void *)(DEFAULT_DMIBAR | 0x090c | (i << 5))) & 0xfff1ffff);
}
- write32 (DEFAULT_DMIBAR | 0x090c,
- read32 (DEFAULT_DMIBAR | 0x090c) & 0xfe1fffff);
- write32 (DEFAULT_DMIBAR | 0x092c,
- read32 (DEFAULT_DMIBAR | 0x092c) & 0xfe1fffff);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x7a1842ec);
- read32 (DEFAULT_DMIBAR | 0x090c); // !!! = 0x00000208
- write32 (DEFAULT_DMIBAR | 0x090c, 0x00000128);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x7a1842ec);
- read32 (DEFAULT_DMIBAR | 0x092c); // !!! = 0x00000208
- write32 (DEFAULT_DMIBAR | 0x092c, 0x00000128);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0c04); // !!! = 0x2e680008
- write32 (DEFAULT_DMIBAR | 0x0c04, 0x2e680008);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1842ec);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1842ec);
- read32 (DEFAULT_DMIBAR | 0x0910); // !!! = 0x00006300
- write32 (DEFAULT_DMIBAR | 0x0910, 0x00004300);
- read32 (DEFAULT_DMIBAR | 0x0930); // !!! = 0x00006300
- write32 (DEFAULT_DMIBAR | 0x0930, 0x00004300);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
- write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
- read32 (DEFAULT_DMIBAR | 0x0a04); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a04, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a14); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a14, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a24); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a24, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a34); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a34, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0900); // !!! = 0x50000000
- write32 (DEFAULT_DMIBAR | 0x0900, 0x50000000);
- read32 (DEFAULT_DMIBAR | 0x0920); // !!! = 0x50000000
- write32 (DEFAULT_DMIBAR | 0x0920, 0x50000000);
- read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
- write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
- read32 (DEFAULT_DMIBAR | 0x0c0c); // !!! = 0x16063400
- write32 (DEFAULT_DMIBAR | 0x0c0c, 0x00063400);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46339008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46339008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46339008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45339008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46339008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45339008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45339008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x453b9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45339008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x453b9008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x453b9008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45bb9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x453b9008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45bb9008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45bb9008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45fb9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45bb9008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45fb9008);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a080
- write32 (DEFAULT_DMIBAR | 0x0914, 0x9021a280);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a080
- write32 (DEFAULT_DMIBAR | 0x0934, 0x9021a280);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a280
- write32 (DEFAULT_DMIBAR | 0x0914, 0x9821a280);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a280
- write32 (DEFAULT_DMIBAR | 0x0934, 0x9821a280);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0258); // !!! = 0x40000600
- write32 (DEFAULT_DMIBAR | 0x0258, 0x60000600);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1846ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x2a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9821a280
- write32 (DEFAULT_DMIBAR | 0x0914, 0x98200280);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1846ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x2a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9821a280
- write32 (DEFAULT_DMIBAR | 0x0934, 0x98200280);
- read32 (DEFAULT_DMIBAR | 0x022c); // !!! = 0x00c26460
- write32 (DEFAULT_DMIBAR | 0x022c, 0x00c2403c);
- read8 (DEFAULT_RCBA | 0x21a4); // !!! = 0x42
+ write32((void *)(DEFAULT_DMIBAR | 0x090c),
+ read32((void *)(DEFAULT_DMIBAR | 0x090c)) & 0xfe1fffff);
+ write32((void *)(DEFAULT_DMIBAR | 0x092c),
+ read32((void *)(DEFAULT_DMIBAR | 0x092c)) & 0xfe1fffff);
+ read32((void *)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x7a1842ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0904), 0x7a1842ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x090c)); // !!! = 0x00000208
+ write32((void *)(DEFAULT_DMIBAR | 0x090c), 0x00000128);
+ read32((void *)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x7a1842ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0924), 0x7a1842ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x092c)); // !!! = 0x00000208
+ write32((void *)(DEFAULT_DMIBAR | 0x092c), 0x00000128);
+ read32((void *)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46139008
+ write32((void *)(DEFAULT_DMIBAR | 0x0700), 0x46139008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46139008
+ write32((void *)(DEFAULT_DMIBAR | 0x0720), 0x46139008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0c04)); // !!! = 0x2e680008
+ write32((void *)(DEFAULT_DMIBAR | 0x0c04), 0x2e680008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x7a1842ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0904), 0x3a1842ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x7a1842ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0924), 0x3a1842ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x0910)); // !!! = 0x00006300
+ write32((void *)(DEFAULT_DMIBAR | 0x0910), 0x00004300);
+ read32((void *)(DEFAULT_DMIBAR | 0x0930)); // !!! = 0x00006300
+ write32((void *)(DEFAULT_DMIBAR | 0x0930), 0x00004300);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042010
+ write32((void *)(DEFAULT_DMIBAR | 0x0a00), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042010
+ write32((void *)(DEFAULT_DMIBAR | 0x0a10), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042010
+ write32((void *)(DEFAULT_DMIBAR | 0x0a20), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042010
+ write32((void *)(DEFAULT_DMIBAR | 0x0a30), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0c00)); // !!! = 0x29700c08
+ write32((void *)(DEFAULT_DMIBAR | 0x0c00), 0x29700c08);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a04)); // !!! = 0x0c0708f0
+ write32((void *)(DEFAULT_DMIBAR | 0x0a04), 0x0c0718f0);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a14)); // !!! = 0x0c0708f0
+ write32((void *)(DEFAULT_DMIBAR | 0x0a14), 0x0c0718f0);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a24)); // !!! = 0x0c0708f0
+ write32((void *)(DEFAULT_DMIBAR | 0x0a24), 0x0c0718f0);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a34)); // !!! = 0x0c0708f0
+ write32((void *)(DEFAULT_DMIBAR | 0x0a34), 0x0c0718f0);
+ read32((void *)(DEFAULT_DMIBAR | 0x0900)); // !!! = 0x50000000
+ write32((void *)(DEFAULT_DMIBAR | 0x0900), 0x50000000);
+ read32((void *)(DEFAULT_DMIBAR | 0x0920)); // !!! = 0x50000000
+ write32((void *)(DEFAULT_DMIBAR | 0x0920), 0x50000000);
+ read32((void *)(DEFAULT_DMIBAR | 0x0908)); // !!! = 0x51ffffff
+ write32((void *)(DEFAULT_DMIBAR | 0x0908), 0x51ffffff);
+ read32((void *)(DEFAULT_DMIBAR | 0x0928)); // !!! = 0x51ffffff
+ write32((void *)(DEFAULT_DMIBAR | 0x0928), 0x51ffffff);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a00), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a10), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a20), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a30), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46139008
+ write32((void *)(DEFAULT_DMIBAR | 0x0700), 0x46139008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46139008
+ write32((void *)(DEFAULT_DMIBAR | 0x0720), 0x46139008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x3a1842ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0904), 0x3a1846ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x3a1842ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0924), 0x3a1846ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a00), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a10), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a20), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a30), 0x03042018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0908)); // !!! = 0x51ffffff
+ write32((void *)(DEFAULT_DMIBAR | 0x0908), 0x51ffffff);
+ read32((void *)(DEFAULT_DMIBAR | 0x0928)); // !!! = 0x51ffffff
+ write32((void *)(DEFAULT_DMIBAR | 0x0928), 0x51ffffff);
+ read32((void *)(DEFAULT_DMIBAR | 0x0c00)); // !!! = 0x29700c08
+ write32((void *)(DEFAULT_DMIBAR | 0x0c00), 0x29700c08);
+ read32((void *)(DEFAULT_DMIBAR | 0x0c0c)); // !!! = 0x16063400
+ write32((void *)(DEFAULT_DMIBAR | 0x0c0c), 0x00063400);
+ read32((void *)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46139008
+ write32((void *)(DEFAULT_DMIBAR | 0x0700), 0x46339008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46139008
+ write32((void *)(DEFAULT_DMIBAR | 0x0720), 0x46339008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46339008
+ write32((void *)(DEFAULT_DMIBAR | 0x0700), 0x45339008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46339008
+ write32((void *)(DEFAULT_DMIBAR | 0x0720), 0x45339008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x45339008
+ write32((void *)(DEFAULT_DMIBAR | 0x0700), 0x453b9008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x45339008
+ write32((void *)(DEFAULT_DMIBAR | 0x0720), 0x453b9008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x453b9008
+ write32((void *)(DEFAULT_DMIBAR | 0x0700), 0x45bb9008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x453b9008
+ write32((void *)(DEFAULT_DMIBAR | 0x0720), 0x45bb9008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x45bb9008
+ write32((void *)(DEFAULT_DMIBAR | 0x0700), 0x45fb9008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x45bb9008
+ write32((void *)(DEFAULT_DMIBAR | 0x0720), 0x45fb9008);
+ read32((void *)(DEFAULT_DMIBAR | 0x0914)); // !!! = 0x9021a080
+ write32((void *)(DEFAULT_DMIBAR | 0x0914), 0x9021a280);
+ read32((void *)(DEFAULT_DMIBAR | 0x0934)); // !!! = 0x9021a080
+ write32((void *)(DEFAULT_DMIBAR | 0x0934), 0x9021a280);
+ read32((void *)(DEFAULT_DMIBAR | 0x0914)); // !!! = 0x9021a280
+ write32((void *)(DEFAULT_DMIBAR | 0x0914), 0x9821a280);
+ read32((void *)(DEFAULT_DMIBAR | 0x0934)); // !!! = 0x9021a280
+ write32((void *)(DEFAULT_DMIBAR | 0x0934), 0x9821a280);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a00), 0x03242018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a10), 0x03242018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a20), 0x03242018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042018
+ write32((void *)(DEFAULT_DMIBAR | 0x0a30), 0x03242018);
+ read32((void *)(DEFAULT_DMIBAR | 0x0258)); // !!! = 0x40000600
+ write32((void *)(DEFAULT_DMIBAR | 0x0258), 0x60000600);
+ read32((void *)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x3a1846ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0904), 0x2a1846ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x0914)); // !!! = 0x9821a280
+ write32((void *)(DEFAULT_DMIBAR | 0x0914), 0x98200280);
+ read32((void *)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x3a1846ec
+ write32((void *)(DEFAULT_DMIBAR | 0x0924), 0x2a1846ec);
+ read32((void *)(DEFAULT_DMIBAR | 0x0934)); // !!! = 0x9821a280
+ write32((void *)(DEFAULT_DMIBAR | 0x0934), 0x98200280);
+ read32((void *)(DEFAULT_DMIBAR | 0x022c)); // !!! = 0x00c26460
+ write32((void *)(DEFAULT_DMIBAR | 0x022c), 0x00c2403c);
+ read8((void *)(DEFAULT_RCBA | 0x21a4)); // !!! = 0x42
- read32 (DEFAULT_RCBA | 0x21a4); // !!! = 0x00012c42
- read32 (DEFAULT_RCBA | 0x2340); // !!! = 0x0013001b
- write32 (DEFAULT_RCBA | 0x2340, 0x003a001b);
- read8 (DEFAULT_RCBA | 0x21b0); // !!! = 0x01
- write8 (DEFAULT_RCBA | 0x21b0, 0x02);
- read32 (DEFAULT_DMIBAR | 0x0084); // !!! = 0x0041ac41
- write32 (DEFAULT_DMIBAR | 0x0084, 0x0041ac42);
- read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0041
- read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
+ read32((void *)(DEFAULT_RCBA | 0x21a4)); // !!! = 0x00012c42
+ read32((void *)(DEFAULT_RCBA | 0x2340)); // !!! = 0x0013001b
+ write32((void *)(DEFAULT_RCBA | 0x2340), 0x003a001b);
+ read8((void *)(DEFAULT_RCBA | 0x21b0)); // !!! = 0x01
+ write8((void *)(DEFAULT_RCBA | 0x21b0), 0x02);
+ read32((void *)(DEFAULT_DMIBAR | 0x0084)); // !!! = 0x0041ac41
+ write32((void *)(DEFAULT_DMIBAR | 0x0084), 0x0041ac42);
+ read8((void *)(DEFAULT_DMIBAR | 0x0088)); // !!! = 0x00
+ write8((void *)(DEFAULT_DMIBAR | 0x0088), 0x20);
+ read16((void *)(DEFAULT_DMIBAR | 0x008a)); // !!! = 0x0041
+ read8((void *)(DEFAULT_DMIBAR | 0x0088)); // !!! = 0x00
+ write8((void *)(DEFAULT_DMIBAR | 0x0088), 0x20);
+ read16((void *)(DEFAULT_DMIBAR | 0x008a)); // !!! = 0x0042
+ read16((void *)(DEFAULT_DMIBAR | 0x008a)); // !!! = 0x0042
- read32 (DEFAULT_DMIBAR | 0x0014); // !!! = 0x8000007f
- write32 (DEFAULT_DMIBAR | 0x0014, 0x80000019);
- read32 (DEFAULT_DMIBAR | 0x0020); // !!! = 0x01000000
- write32 (DEFAULT_DMIBAR | 0x0020, 0x81000022);
- read32 (DEFAULT_DMIBAR | 0x002c); // !!! = 0x02000000
- write32 (DEFAULT_DMIBAR | 0x002c, 0x82000044);
- read32 (DEFAULT_DMIBAR | 0x0038); // !!! = 0x07000080
- write32 (DEFAULT_DMIBAR | 0x0038, 0x87000080);
- read8 (DEFAULT_DMIBAR | 0x0004); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0004, 0x01);
+ read32((void *)(DEFAULT_DMIBAR | 0x0014)); // !!! = 0x8000007f
+ write32((void *)(DEFAULT_DMIBAR | 0x0014), 0x80000019);
+ read32((void *)(DEFAULT_DMIBAR | 0x0020)); // !!! = 0x01000000
+ write32((void *)(DEFAULT_DMIBAR | 0x0020), 0x81000022);
+ read32((void *)(DEFAULT_DMIBAR | 0x002c)); // !!! = 0x02000000
+ write32((void *)(DEFAULT_DMIBAR | 0x002c), 0x82000044);
+ read32((void *)(DEFAULT_DMIBAR | 0x0038)); // !!! = 0x07000080
+ write32((void *)(DEFAULT_DMIBAR | 0x0038), 0x87000080);
+ read8((void *)(DEFAULT_DMIBAR | 0x0004)); // !!! = 0x00
+ write8((void *)(DEFAULT_DMIBAR | 0x0004), 0x01);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
- write32 (DEFAULT_RCBA | 0x0050, 0x01200654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
- write32 (DEFAULT_RCBA | 0x0050, 0x012a0654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
- read8 (DEFAULT_RCBA | 0x1114); // !!! = 0x00
- write8 (DEFAULT_RCBA | 0x1114, 0x05);
- read32 (DEFAULT_RCBA | 0x2014); // !!! = 0x80000011
- write32 (DEFAULT_RCBA | 0x2014, 0x80000019);
- read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2020, 0x81000022);
- read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x81000022
- read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2030, 0x82000044);
- read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x82000044
- read32 (DEFAULT_RCBA | 0x2040); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2040, 0x87000080);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
- write32 (DEFAULT_RCBA | 0x0050, 0x812a0654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x812a0654
- read16 (DEFAULT_RCBA | 0x201a); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2026); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2036); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2046); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x001a); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x0026); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x0032); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x003e); // !!! = 0x0000
+ read32((void *)(DEFAULT_RCBA | 0x0050)); // !!! = 0x01200654
+ write32((void *)(DEFAULT_RCBA | 0x0050), 0x01200654);
+ read32((void *)(DEFAULT_RCBA | 0x0050)); // !!! = 0x01200654
+ write32((void *)(DEFAULT_RCBA | 0x0050), 0x012a0654);
+ read32((void *)(DEFAULT_RCBA | 0x0050)); // !!! = 0x012a0654
+ read8((void *)(DEFAULT_RCBA | 0x1114)); // !!! = 0x00
+ write8((void *)(DEFAULT_RCBA | 0x1114), 0x05);
+ read32((void *)(DEFAULT_RCBA | 0x2014)); // !!! = 0x80000011
+ write32((void *)(DEFAULT_RCBA | 0x2014), 0x80000019);
+ read32((void *)(DEFAULT_RCBA | 0x2020)); // !!! = 0x00000000
+ write32((void *)(DEFAULT_RCBA | 0x2020), 0x81000022);
+ read32((void *)(DEFAULT_RCBA | 0x2020)); // !!! = 0x81000022
+ read32((void *)(DEFAULT_RCBA | 0x2030)); // !!! = 0x00000000
+ write32((void *)(DEFAULT_RCBA | 0x2030), 0x82000044);
+ read32((void *)(DEFAULT_RCBA | 0x2030)); // !!! = 0x82000044
+ read32((void *)(DEFAULT_RCBA | 0x2040)); // !!! = 0x00000000
+ write32((void *)(DEFAULT_RCBA | 0x2040), 0x87000080);
+ read32((void *)(DEFAULT_RCBA | 0x0050)); // !!! = 0x012a0654
+ write32((void *)(DEFAULT_RCBA | 0x0050), 0x812a0654);
+ read32((void *)(DEFAULT_RCBA | 0x0050)); // !!! = 0x812a0654
+ read16((void *)(DEFAULT_RCBA | 0x201a)); // !!! = 0x0000
+ read16((void *)(DEFAULT_RCBA | 0x2026)); // !!! = 0x0000
+ read16((void *)(DEFAULT_RCBA | 0x2036)); // !!! = 0x0000
+ read16((void *)(DEFAULT_RCBA | 0x2046)); // !!! = 0x0000
+ read16((void *)(DEFAULT_DMIBAR | 0x001a)); // !!! = 0x0000
+ read16((void *)(DEFAULT_DMIBAR | 0x0026)); // !!! = 0x0000
+ read16((void *)(DEFAULT_DMIBAR | 0x0032)); // !!! = 0x0000
+ read16((void *)(DEFAULT_DMIBAR | 0x003e)); // !!! = 0x0000
}
void
@@ -292,21 +292,21 @@ early_pch_init_native (void)
pcie_write_config8 (SOUTHBRIDGE, 0xa6,
pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
- write32 (DEFAULT_RCBA | 0x2088, 0x00109000);
- read32 (DEFAULT_RCBA | 0x20ac); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x20ac, 0x40000000);
- write32 (DEFAULT_RCBA | 0x100c, 0x01110000);
- write8 (DEFAULT_RCBA | 0x2340, 0x1b);
- read32 (DEFAULT_RCBA | 0x2314); // !!! = 0x0a080000
- write32 (DEFAULT_RCBA | 0x2314, 0x0a280000);
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xc809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
- write32 (DEFAULT_RCBA | 0x2324, 0x00854c74);
- read8 (DEFAULT_RCBA | 0x0400); // !!! = 0x00
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
+ write32((void *)(DEFAULT_RCBA | 0x2088), 0x00109000);
+ read32((void *)(DEFAULT_RCBA | 0x20ac)); // !!! = 0x00000000
+ write32((void *)(DEFAULT_RCBA | 0x20ac), 0x40000000);
+ write32((void *)(DEFAULT_RCBA | 0x100c), 0x01110000);
+ write8((void *)(DEFAULT_RCBA | 0x2340), 0x1b);
+ read32((void *)(DEFAULT_RCBA | 0x2314)); // !!! = 0x0a080000
+ write32((void *)(DEFAULT_RCBA | 0x2314), 0x0a280000);
+ read32((void *)(DEFAULT_RCBA | 0x2310)); // !!! = 0xc809605b
+ write32((void *)(DEFAULT_RCBA | 0x2310), 0xa809605b);
+ write32((void *)(DEFAULT_RCBA | 0x2324), 0x00854c74);
+ read8((void *)(DEFAULT_RCBA | 0x0400)); // !!! = 0x00
+ read32((void *)(DEFAULT_RCBA | 0x2310)); // !!! = 0xa809605b
+ write32((void *)(DEFAULT_RCBA | 0x2310), 0xa809605b);
+ read32((void *)(DEFAULT_RCBA | 0x2310)); // !!! = 0xa809605b
+ write32((void *)(DEFAULT_RCBA | 0x2310), 0xa809605b);
write_2338 (0xea007f62, 0x00590133);
write_2338 (0xec007f62, 0x00590133);
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index 02ec9a7..11af24d 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -41,30 +41,31 @@ void early_thermal_init(void)
pci_read_config32(dev, 0x40) | 5);
- write16 (0x40000004, 0x3a2b);
- write8 (0x4000000c, 0xff);
- write8 (0x4000000d, 0x00);
- write8 (0x4000000e, 0x40);
- write8 (0x40000082, 0x00);
- write8 (0x40000001, 0xba);
+ write16((void *)0x40000004, 0x3a2b);
+ write8((void *)0x4000000c, 0xff);
+ write8((void *)0x4000000d, 0x00);
+ write8((void *)0x4000000e, 0x40);
+ write8((void *)0x40000082, 0x00);
+ write8((void *)0x40000001, 0xba);
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
- write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
+ write16((void *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
/* Northbridge temperature slope and offset. */
- write16(0x40000016, 0x808c);
+ write16((void *)0x40000016, 0x808c);
- write16 (0x40000014, 0xde87);
+ write16((void *)0x40000014, 0xde87);
/* Enable thermal data reporting, processor, PCH and northbridge. */
- write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+ write16((void *)0x4000001a,
+ (read16((void *)0x4000001a) & ~0xf) | 0x10f0);
/* Disable temporary BAR. */
pci_write_config32(dev, 0x40,
pci_read_config32(dev, 0x40) & ~1);
pci_write_config32(dev, 0x40, 0);
- write32 (DEFAULT_RCBA | 0x38b0,
- (read32 (DEFAULT_RCBA | 0x38b0) & 0xffff8003) | 0x403c);
+ write32((void *)(DEFAULT_RCBA | 0x38b0),
+ (read32((void *)(DEFAULT_RCBA | 0x38b0)) & 0xffff8003) | 0x403c);
}
diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c
index b1f8447..55d6aab 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_native.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_native.c
@@ -43,32 +43,33 @@ early_usb_init (const struct southbridge_usb_port *portmap)
/* Unlock registers. */
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
for (i = 0; i < 14; i++)
- write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i),
- currents[portmap[i].current]);
+ write32((void *)(DEFAULT_RCBABASE | (0x3500 + 4 * i)),
+ currents[portmap[i].current]);
for (i = 0; i < 10; i++)
- write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0);
+ write32((void *)(DEFAULT_RCBABASE | (0x3538 + 4 * i)), 0);
for (i = 0; i < 8; i++)
- write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]);
+ write32((void *)(DEFAULT_RCBABASE | (0x3560 + 4 * i)),
+ rcba_dump[i]);
for (i = 0; i < 8; i++)
- write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0);
+ write32((void *)(DEFAULT_RCBABASE | (0x3580 + 4 * i)), 0);
reg32 = 0;
for (i = 0; i < 14; i++)
if (!portmap[i].enabled)
reg32 |= (1 << i);
- write32 (DEFAULT_RCBABASE | 0x359c, reg32);
+ write32((void *)(DEFAULT_RCBABASE | 0x359c), reg32);
reg32 = 0;
for (i = 0; i < 8; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
- write32 (DEFAULT_RCBABASE | 0x35a0, reg32);
+ write32((void *)(DEFAULT_RCBABASE | 0x35a0), reg32);
reg32 = 0;
for (i = 8; i < 14; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
- write32 (DEFAULT_RCBABASE | 0x35a4, reg32);
+ write32((void *)(DEFAULT_RCBABASE | 0x35a4), reg32);
for (i = 0; i < 22; i++)
- write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0);
+ write32((void *)(DEFAULT_RCBABASE | (0x35a8 + 4 * i)), 0);
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 11b765a..ababcd0 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -59,17 +59,17 @@ static void pch_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 901e71d..df18830 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -64,7 +64,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -501,11 +501,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -627,7 +627,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32*)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index e25b3b8..3fa3269 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -66,7 +66,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -108,7 +108,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -147,13 +147,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -495,11 +495,11 @@ void intel_me8_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (void *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -614,7 +614,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..ef6278c 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -66,7 +66,7 @@ static void sata_init(struct device *dev)
/* AHCI */
if (sata_mode == 0) {
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -100,10 +100,10 @@ static void sata_init(struct device *dev)
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
+ reg32 = read32(abar + (0x00/sizeof(u32)));
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
/* Set ISS, if available */
@@ -113,19 +113,19 @@ static void sata_init(struct device *dev)
reg32 |= (config->sata_interface_speed_support & 0x03)
<< 20;
}
- write32(abar + 0x00, reg32);
+ write32(abar + (0x00/sizeof(u32)), reg32);
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ write32(abar + (0x0c/sizeof(u32)), config->sata_port_map);
+ (void) read32(abar + (0x0c/sizeof(u32))); /* Read back 1 */
+ (void) read32(abar + (0x0c/sizeof(u32))); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x24);
+ reg32 = read32(abar + (0x24/sizeof(u32)));
reg32 &= ~0x00000002;
- write32(abar + 0x24, reg32);
+ write32(abar + (0x24/sizeof(u32)), reg32);
/* VSP (Vendor Specific Register */
- reg32 = read32(abar + 0xa0);
+ reg32 = read32(abar + (0xa0/sizeof(u32)));
reg32 &= ~0x00000005;
- write32(abar + 0xa0, reg32);
+ write32(abar + (0xa0/sizeof(u32)), reg32);
} else {
/* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 9850fee..b76963f 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -66,8 +66,9 @@ static void usb_ehci_init(struct device *dev)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
- reg32 = read32(res->base + 4);
- write32(res->base + 4, (reg32 & 0xfff00000) | 3);
+ reg32 = read32((void *)(uintptr_t)(res->base + 4));
+ write32((void *)(uintptr_t)(res->base + 4),
+ (reg32 & 0xfff00000) | 3);
}
/* Restore protection. */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 3f22bc7..d6ab01a 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -199,7 +199,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -207,7 +207,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -215,41 +215,41 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
}
-static void writeb_(u8 b, const void *addr)
+static void writeb_(u8 b, void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
-static void writew_(u16 b, const void *addr)
+static void writew_(u16 b, void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
-static void writel_(u32 b, const void *addr)
+static void writel_(u32 b, void *addr)
{
- write32((unsigned long)addr, b);
+ write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index b5b77ef..b80a77e 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -242,7 +242,7 @@ static void lpc_init(struct device *dev)
value |= (1 << 8)|(1<<7);
value |= (6 << 0)|(1<<13)|(1<<11);
pci_write_config32(dev, 0xd0, value);
- setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID
+ setup_ioapic((void *)IO_APIC_ADDR, 0); // don't rename IO APIC ID
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
diff --git a/src/southbridge/intel/esb6300/pic.c b/src/southbridge/intel/esb6300/pic.c
index e3fc2b2..c453ca3 100644
--- a/src/southbridge/intel/esb6300/pic.c
+++ b/src/southbridge/intel/esb6300/pic.c
@@ -23,7 +23,7 @@ static void pic_init(struct device *dev)
pci_write_config8(dev, 0x3c, 0xff);
/* Setup the ioapic */
- clear_ioapic(IO_APIC_ADDR + 0x10000);
+ clear_ioapic((void *)(IO_APIC_ADDR + 0x10000));
}
static void pic_read_resources(device_t dev)
diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c
index 7a280c5..6c6b3d8 100644
--- a/src/southbridge/intel/fsp_bd82x6x/azalia.c
+++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c
@@ -34,7 +34,7 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -63,19 +63,20 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(base + (0x0 / sizeof(u32)),
+ read16(base + (0x0 / sizeof(u32))));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + 0xe);
+ reg8 = read8(base + (0xe / sizeof(u32)));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -85,7 +86,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
@@ -118,7 +119,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -126,7 +127,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -141,21 +142,21 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(base + (HDA_ICII_REG / sizeof(u32)), reg32);
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -165,7 +166,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -181,14 +182,14 @@ static void codec_init(struct device *dev, u32 base, int addr)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n");
return;
}
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -205,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -213,7 +214,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -225,7 +226,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(base + (0x60 / sizeof(u32)), pc_beep_verbs[i]);
if (wait_for_valid(base) == -1)
return;
@@ -234,7 +235,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -248,7 +249,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = (u32 *)(uintptr_t)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index 5326eb5..edca0a1 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -144,13 +144,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -500,11 +500,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -626,7 +626,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (void *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index d673ac7..9af5f93 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -64,7 +64,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -494,11 +494,11 @@ void intel_me8_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -613,7 +613,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c
index 591bdbc..ff0e20b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/sata.c
+++ b/src/southbridge/intel/fsp_bd82x6x/sata.c
@@ -57,7 +57,7 @@ static void sata_init(struct device *dev)
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
} else if(config->sata_ahci) {
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -66,12 +66,12 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, INTR_LN, 0x0a);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Enable AHCI Mode */
- reg32 = read32(abar + 0x04);
+ reg32 = read32(abar + 0x01);
reg32 |= (1 << 31);
- write32(abar + 0x04, reg32);
+ write32(abar + 0x01, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 844f4b8..1e6a155 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -41,8 +41,8 @@ static void rangeley_setup_bars(void)
printk(BIOS_DEBUG, "Disabling Watchdog timer...");
/* Disable the watchdog reboot and turn off the watchdog timer */
- write8(DEFAULT_PBASE + PMC_CFG, read8(DEFAULT_PBASE + PMC_CFG) |
- NO_REBOOT); // disable reboot on timer trigger
+ write8((void *)(DEFAULT_PBASE + PMC_CFG),
+ read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger
outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) |
TCO_TMR_HALT); // disable watchdog timer
@@ -54,7 +54,7 @@ static void reset_rtc(void)
{
uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) &
0xfffffff0;
- uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+ uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
@@ -63,7 +63,8 @@ static void reset_rtc(void)
coreboot_dmi_date);
/* Clear the power failure flag */
- write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+ write32((void *)(DEFAULT_PBASE + GEN_PMCON1),
+ gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 8569b96..6ea9c2e 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -30,7 +30,7 @@
void setup_soc_gpios(const struct soc_gpio_map *gpio)
{
u16 gpiobase = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf;
- u32 cfiobase = pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf;
+ u32 *cfiobase = (u32 *)(pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf);
u32 cfio_cnt = 0;
@@ -67,30 +67,30 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* GPIO PAD settings */
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
- write32(cfiobase + 0x0700, (u32)0x01001002);
+ write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
continue;
- write32(cfiobase + CFIO_PAD_CONF0 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
- write32(cfiobase + CFIO_PAD_CONF1 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
- write32(cfiobase + CFIO_PAD_VAL + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
- write32(cfiobase + CFIO_PAD_DFT + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
+ write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
+ write32(cfiobase + ((CFIO_PAD_CONF1 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
+ write32(cfiobase + ((CFIO_PAD_VAL + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
+ write32(cfiobase + ((CFIO_PAD_DFT + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
}
- write32(cfiobase + 0x0700, (u32)0x01041002);
+ write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01041002);
}
/* CFIO SUS Well Set 1 */
if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
- write32(cfiobase + 0x1700, (u32)0x01001002);
+ write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
continue;
- write32(cfiobase + CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
- write32(cfiobase + CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
- write32(cfiobase + CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
- write32(cfiobase + CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
+ write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
+ write32(cfiobase + ((CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
+ write32(cfiobase + ((CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
+ write32(cfiobase + ((CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
}
- write32(cfiobase + 0x1700, (u32)0x01041002);
+ write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01041002);
}
}
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 9644067..8f29670 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev)
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
- u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f;
+ u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/*
* Enable ACPI I/O and power management.
@@ -91,9 +91,9 @@ static void soc_enable_apic(struct device *dev)
static void soc_enable_serial_irqs(struct device *dev)
{
- u32 ibase;
+ u8 *ibase;
- ibase = pci_read_config32(dev, IBASE) & ~0xF;
+ ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
/* Set packet length and toggle silent mode bit for one frame. */
write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
@@ -206,10 +206,10 @@ static void soc_pirq_init(device_t dev)
{
int i, j;
int pirq;
- const u32 ibase = pci_read_config32(dev, IBASE) & ~0xF;
- const unsigned long pr_base = ibase + 0x08;
- const unsigned long ir_base = ibase + 0x20;
- const unsigned long actl = ibase;
+ u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
+ u8 *pr_base = ibase + 0x08;
+ u16 *ir_base = (u16 *)(ibase + 0x20);
+ u32 *actl = (u32 *)ibase;
const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
/* Set up the PIRQ PIC routing based on static config. */
@@ -226,7 +226,7 @@ static void soc_pirq_init(device_t dev)
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
@@ -293,10 +293,10 @@ static void soc_power_options(device_t dev)
/* Disable the HPET, Clear the counter, and re-enable it. */
static void enable_hpet(void)
{
- write8(HPET_GCFG, 0x00);
- write32(HPET_MCV, 0x00000000);
- write32(HPET_MCV + 0x04, 0x00000000);
- write8(HPET_GCFG, 0x01);
+ write8((u8 *)HPET_GCFG, 0x00);
+ write32((u32 *)HPET_MCV, 0x00000000);
+ write32((u32 *)(HPET_MCV + 0x04), 0x00000000);
+ write8((u8 *)HPET_GCFG, 0x01);
}
static void soc_disable_smm_only_flashing(struct device *dev)
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 6c5751e..01f16ef 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -42,7 +42,7 @@
void main(FSP_INFO_HEADER *fsp_info_header)
{
uint32_t fd_mask = 0;
- uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;
+ uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS);
/*
* Do not use the Serial Console before it is setup.
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index f672e4c..4648ac7 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -32,7 +32,7 @@ static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
- u32 abar;
+ u32 *abar;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -74,13 +74,13 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, SATA_MAP, reg16);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Enable AHCI Mode */
- reg32 = read32(abar + 0x04);
+ reg32 = read32(abar + 0x01);
reg32 |= (1 << 31);
- write32(abar + 0x04, reg32);
+ write32(abar + 0x01, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
}
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index ee22019..b813d07 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -231,7 +231,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -239,7 +239,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -247,7 +247,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -255,14 +255,14 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
@@ -276,12 +276,12 @@ static void writel_(u32 b, const void *addr)
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index ba74f30..aa57517 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -358,7 +358,7 @@ static void lpc_init(struct device *dev)
// TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
// (register 0x10/0x11) while the old code used int 1 (register 0x12)
// ... Why?
- setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
+ setup_ioapic((void *)IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
pci_write_config32(dev, 0xd0, 0x00000000);
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index 11519c1..1603700 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -103,13 +103,13 @@ static void i82801ax_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static void i82801ax_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 278d65c..ac44dd3 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -104,13 +104,13 @@ static void i82801bx_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static void i82801bx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index f6c33b7..992e6a2 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -41,13 +41,13 @@ static void i82801cx_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
// This is how interrupts are received from the Super I/O chip
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 1b23fad..907a466 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -67,13 +67,13 @@ static void i82801dx_enable_ioapic(struct device *dev)
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static void i82801dx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 1823e65..0ca193e 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -281,7 +281,7 @@ static void lpc_init(struct device *dev)
i82801ex_general_cntl(dev);
/* IO APIC initialization. */
- setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
+ setup_ioapic((void *)IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index f6628e7..dd633b4 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -34,7 +34,7 @@
typedef struct southbridge_intel_i82801gx_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -63,20 +63,20 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u32 reg32;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 0) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 0) == -1)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg32 = read32(base + 0xe);
+ reg32 = read32(base + (0xe / sizeof(u32)));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -86,7 +86,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
@@ -114,7 +114,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -122,7 +122,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -137,21 +137,21 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + 0x68);
+ reg32 = read32(base + (0x68 / sizeof(u32)));
reg32 |= (1 << 0) | (1 << 1);
- write32(base + 0x68, reg32);
+ write32(base + (0x68 / sizeof(u32)), reg32);
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -161,7 +161,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -175,12 +175,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -197,7 +197,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -205,7 +205,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -216,7 +216,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -297,7 +297,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = (u32 *)(uintptr_t)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 6b9d11e..d64600d 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -53,13 +53,13 @@ static void i82801gx_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static void i82801gx_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index bb176c7..cf31f8b 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -29,7 +29,7 @@
static void usb_ehci_init(struct device *dev)
{
struct resource *res;
- u32 base;
+ u32 *base;
u32 reg32;
u8 reg8;
@@ -50,9 +50,9 @@ static void usb_ehci_init(struct device *dev)
/* Clear any pending port changes */
res = find_resource(dev, 0x10);
- base = res->base;
- reg32 = read32(base + 0x24) | (1 << 2);
- write32(base + 0x24, reg32);
+ base = (void *)(uintptr_t)res->base;
+ reg32 = read32(base + (0x24/sizeof(u32))) | (1 << 2);
+ write32(base + (0x24/sizeof(u32)), reg32);
/* workaround */
reg8 = pci_read_config8(dev, 0x84);
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index dd817b9..909a1e7 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -35,7 +35,7 @@
typedef struct southbridge_intel_i82801ix_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -64,20 +64,20 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u32 reg32;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 0) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 0) == -1)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg32 = read32(base + 0xe);
+ reg32 = read32(base + (0xe / sizeof(u32)));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -87,7 +87,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
@@ -115,7 +115,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -123,7 +123,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -138,21 +138,21 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + 0x68);
+ reg32 = read32(base + (0x68 / sizeof(u32)));
reg32 |= (1 << 0) | (1 << 1);
- write32(base + 0x68, reg32);
+ write32(base + (0x68 / sizeof(u32)), reg32);
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -162,7 +162,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -176,12 +176,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -198,7 +198,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -206,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -218,7 +218,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(base + (0x60 / sizeof(u32)), pc_beep_verbs[i]);
if (wait_for_valid(base) == -1)
return;
@@ -227,7 +227,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -281,7 +281,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = (u32 *)(uintptr_t)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 6038eff..465b479 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -62,7 +62,7 @@ static void i82801ix_enable_apic(struct device *dev)
*ioapic_index = 0x01;
*ioapic_data = reg32;
- setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */
+ setup_ioapic((void *)IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */
}
static void i82801ix_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index 10c8a2b..41f649d 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -36,38 +36,38 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
u32 reg32;
/* Initialize AHCI memory-mapped space */
- const u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ u32 *abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* Set AHCI access mode.
No other ABAR registers should be accessed before this. */
- reg32 = read32(abar + 0x04);
+ reg32 = read32(abar + (0x04/sizeof(u32)));
reg32 |= 1 << 31;
- write32(abar + 0x04, reg32);
+ write32(abar + (0x04/sizeof(u32)), reg32);
/* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
+ reg32 = read32(abar + (0x00/sizeof(u32)));
/* CCCS must be set. */
reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */
reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
- write32(abar + 0x00, reg32);
+ write32(abar + (0x00/sizeof(u32)), reg32);
/* PI (Ports implemented) */
- write32(abar + 0x0c, port_map);
+ write32(abar + (0x0c/sizeof(u32)), port_map);
/* PCH code reads back twice, do we need it, too? */
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ (void) read32(abar + (0x0c/sizeof(u32))); /* Read back 1 */
+ (void) read32(abar + (0x0c/sizeof(u32))); /* Read back 2 */
/* VSP (Vendor Specific Register) */
- reg32 = read32(abar + 0xa0);
+ reg32 = read32(abar + (0xa0/sizeof(u32)));
reg32 &= ~0x00000001; /* clear SLPD */
- write32(abar + 0xa0, reg32);
+ write32(abar + (0xa0/sizeof(u32)), reg32);
/* Lock R/WO bits in Port command registers. */
for (i = 0; i < 6; ++i) {
if (((i == 2) || (i == 3)) && is_mobile)
continue;
- const u32 addr = abar + 0x118 + (i * 0x80);
+ u32 *addr = abar + ((0x118 + (i * 0x80))/sizeof(u32));
write32(addr, read32(addr));
}
}
diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c
index 3245a27..803e455 100644
--- a/src/southbridge/intel/i82801ix/thermal.c
+++ b/src/southbridge/intel/i82801ix/thermal.c
@@ -38,16 +38,16 @@ static void thermal_init(struct device *dev)
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 | (1 << 1));
- write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
- write32(DEFAULT_TBAR + 0x44, 0);
+ write32((void *)(DEFAULT_TBAR + 0x04), 0); /* Clear thermal trip points. */
+ write32((void *)(DEFAULT_TBAR + 0x44), 0);
- write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */
- write8(DEFAULT_TBAR + 0x41, 0xba);
+ write8((void *)(DEFAULT_TBAR + 0x01), 0xba); /* Enable sensor 0 + 1. */
+ write8((void *)(DEFAULT_TBAR + 0x41), 0xba);
- reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */
- write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7));
- reg8 = read8(DEFAULT_TBAR + 0x48);
- write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
+ reg8 = read8((void *)(DEFAULT_TBAR + 0x08)); /* Lock thermal registers. */
+ write8((void *)(DEFAULT_TBAR + 0x08), reg8 | (1 << 7));
+ reg8 = read8((void *)(DEFAULT_TBAR + 0x48));
+ write8((void *)(DEFAULT_TBAR + 0x48), reg8 | (1 << 7));
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 & ~(1 << 1));
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 314a1b1..56c6c1b 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -33,7 +33,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -62,19 +62,20 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(base + (0x0 / sizeof(u32)),
+ read16(base + (0x0 / sizeof(u32))));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + 0xe);
+ reg8 = read8(base + (0xe / sizeof(u32)));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -84,7 +85,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
@@ -112,14 +113,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -134,20 +135,20 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(base + (HDA_ICII_REG / sizeof(u32)), reg32);
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -157,7 +158,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -173,14 +174,14 @@ static void codec_init(struct device *dev, u32 base, int addr)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n");
return;
}
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -197,7 +198,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -205,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
@@ -217,7 +218,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(base + (0x60 / sizeof(u32)), pc_beep_verbs[i]);
if (wait_for_valid(base) == -1)
return;
@@ -226,7 +227,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
u8 reg8;
@@ -240,7 +241,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
+ base = (u32 *)(uintptr_t)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c
index d23749e..e765943 100644
--- a/src/southbridge/intel/ibexpeak/early_thermal.c
+++ b/src/southbridge/intel/ibexpeak/early_thermal.c
@@ -43,11 +43,12 @@ void early_thermal_init(void)
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
- write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
+ write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
/* Northbridge temperature slope and offset. */
- write16(0x40000016, 0x7746);
+ write16((u16 *)0x40000016, 0x7746);
/* Enable thermal data reporting, processor, PCH and northbridge. */
- write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+ write16((u16 *)0x4000001a,
+ (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
/* Disable temporary BAR. */
pci_write_config32(dev, 0x40,
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 2124711..aa6977e 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -59,16 +59,16 @@ static void pch_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x01);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x01);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)
@@ -394,7 +394,7 @@ static void enable_hpet(void)
reg32 &= ~(3 << 0);
RCBA32(HPTC) = reg32;
- write32(0xfed00010, read32(0xfed00010) | 1);
+ write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
}
static void enable_clock_gating(device_t dev)
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index f94b17f..9592b23 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -382,11 +382,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -508,7 +508,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 5f3c4d3..c8450ad 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -67,7 +67,7 @@ static void sata_init(struct device *dev)
if (sata_mode == 0) {
/* AHCI */
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -103,8 +103,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x98, 0x00590200);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
@@ -118,16 +118,16 @@ static void sata_init(struct device *dev)
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
write32(abar + 0x0c, config->sata_port_map);
- (void)read32(abar + 0x0c); /* Read back 1 */
- (void)read32(abar + 0x0c); /* Read back 2 */
+ (void)read32(abar + 0x03); /* Read back 1 */
+ (void)read32(abar + 0x03); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended) */
- reg32 = read32(abar + 0x24);
+ reg32 = read32(abar + 0x09);
reg32 &= ~0x00000002;
- write32(abar + 0x24, reg32);
+ write32(abar + 0x09, reg32);
/* VSP (Vendor Specific Register */
- reg32 = read32(abar + 0xa0);
+ reg32 = read32(abar + 0x28);
reg32 &= ~0x00000005;
- write32(abar + 0xa0, reg32);
+ write32(abar + 0x28, reg32);
} else {
/* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index fa39626..f11f678 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -28,21 +28,22 @@
static void thermal_init(struct device *dev)
{
struct resource *res;
-
+ u8 *base;
printk(BIOS_DEBUG, "Thermal init start.\n");
res = find_resource(dev, 0x10);
if (!res)
return;
- write32(res->base + 4, 0x3a2b);
- write8(res->base + 0xe, 0x40);
- write16(res->base + 0x56, 0xffff);
- write16(res->base + 0x64, 0xffff);
- write16(res->base + 0x66, 0xffff);
- write16(res->base + 0x68, 0xfa);
+ base = (u8 *)(uintptr_t)res->base;
+ write32(base + 4, 0x3a2b);
+ write8(base + 0xe, 0x40);
+ write16(base + 0x56, 0xffff);
+ write16(base + 0x64, 0xffff);
+ write16(base + 0x66, 0xffff);
+ write16(base + 0x68, 0xfa);
- write8(res->base + 1, 0xb8);
+ write8(base + 1, 0xb8);
printk(BIOS_DEBUG, "Thermal init done.\n");
}
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 868a068..6a48d13 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -60,8 +60,9 @@ static void usb_ehci_init(struct device *dev)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
- reg32 = read32(res->base + 4);
- write32(res->base + 4, (reg32 & 0xfff00000) | 2);
+ reg32 = read32((u32 *)(uintptr_t)(res->base + 4));
+ write32((u32 *)(uintptr_t)(res->base + 4),
+ (reg32 & 0xfff00000) | 2);
}
/* Restore protection. */
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index be056be..7693637 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -30,7 +30,7 @@
#include "pch.h"
#include "hda_verb.h"
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(u8 *base, u32 codec_mask)
{
int i;
@@ -46,7 +46,7 @@ static void codecs_init(u32 base, u32 codec_mask)
hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
}
-static void azalia_pch_init(struct device *dev, u32 base)
+static void azalia_pch_init(struct device *dev, u8 *base)
{
u8 reg8;
u16 reg16;
@@ -131,7 +131,7 @@ static void azalia_pch_init(struct device *dev, u32 base)
static void azalia_init(struct device *dev)
{
- u32 base;
+ u8 *base;
struct resource *res;
u32 codec_mask;
u32 reg32;
@@ -141,8 +141,8 @@ static void azalia_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ base = (u8 *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
index 234a1ab..b1508b9 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.c
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -28,7 +28,7 @@
/**
* Set bits in a register and wait for status
*/
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -60,7 +60,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
/**
* Probe for supported codecs
*/
-int hda_codec_detect(u32 base)
+int hda_codec_detect(u8 *base)
{
u8 reg8;
@@ -91,7 +91,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
-static int hda_wait_for_ready(u32 base)
+static int hda_wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -113,7 +113,7 @@ static int hda_wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
-static int hda_wait_for_valid(u32 base)
+static int hda_wait_for_valid(u8 *base)
{
u32 reg32;
@@ -185,7 +185,7 @@ static u32 hda_find_verb(u32 verb_table_bytes,
/**
* Write a supplied verb table
*/
-int hda_codec_write(u32 base, u32 size, const u32 *data)
+int hda_codec_write(u8 *base, u32 size, const u32 *data)
{
int i;
@@ -205,7 +205,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
/**
* Initialize codec, then find the verb table and write it
*/
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data)
{
const u32 *verb;
u32 reg32, size;
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h
index 8b3d27e..52c1468 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.h
+++ b/src/southbridge/intel/lynxpoint/hda_verb.h
@@ -30,8 +30,8 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-int hda_codec_detect(u32 base);
-int hda_codec_write(u32 base, u32 size, const u32 *data);
-int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
+int hda_codec_detect(u8 *base);
+int hda_codec_write(u8 *base, u32 size, const u32 *data);
+int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data);
#endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 563cb0a..e27724d 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -57,22 +57,22 @@ static void pch_enable_ioapic(struct device *dev)
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
- set_ioapic_id(IO_APIC_ADDR, 0x02);
+ set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+ reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
if (pch_is_lp()) {
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
}
- io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+ io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
- io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
}
static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index dfed6de..5c777f4 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
void intel_me_mbp_clear(device_t dev);
#if CONFIG_DEBUG_INTEL_ME
@@ -104,7 +104,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -113,7 +113,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -141,13 +141,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -599,11 +599,11 @@ void intel_me_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
#if CONFIG_ME_MBP_CLEAR_LATE
@@ -743,7 +743,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 43a99c8..89a72f4 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -96,7 +96,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
} else if(config->sata_ahci) {
- u32 abar;
+ u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -156,8 +156,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94, reg32);
/* Initialize AHCI memory-mapped space */
- abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
- printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+ abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
@@ -166,11 +166,11 @@ static void sata_init(struct device *dev)
reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ write32(abar + 0x03, config->sata_port_map);
+ (void) read32(abar + 0x03); /* Read back 1 */
+ (void) read32(abar + 0x03); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x24);
+ reg32 = read32(abar + 0x09);
/* Enable DEVSLP */
if (pch_is_lp()) {
if (config->sata_devslp_disable)
@@ -180,7 +180,7 @@ static void sata_init(struct device *dev)
} else {
reg32 &= ~0x00000002;
}
- write32(abar + 0x24, reg32);
+ write32(abar + 0x09, reg32);
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 75edf5c..23a0edb 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -32,9 +32,9 @@
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
+ u32 reg32 = read32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_CLOCK));
reg32 |= SIO_REG_PPR_CLOCK_EN;
- write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_CLOCK), reg32);
}
/* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -85,22 +85,22 @@ static void serialio_d21_ltr(struct resource *bar0)
u32 reg;
/* 1. Program BAR0 + 808h[2] = 0b */
- reg = read32(bar0->base + SIO_REG_PPR_GEN);
+ reg = read32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_PPR_GEN, reg);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN), reg);
/* 2. Program BAR0 + 804h[1:0] = 00b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
reg &= ~SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST), reg);
/* 3. Program BAR0 + 804h[1:0] = 11b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
reg |= SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST), reg);
/* 4. Program BAR0 + 814h[31:0] = 00000000h */
- write32(bar0->base + SIO_REG_AUTO_LTR, 0);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_AUTO_LTR), 0);
}
/* Enable LTR Auto Mode for D23:F0. */
@@ -109,26 +109,26 @@ static void serialio_d23_ltr(struct resource *bar0)
u32 reg;
/* Program BAR0 + 1008h[2] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
+ reg = read32((u32 *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_GEN));
reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_GEN), reg);
/* Program BAR0 + 1010h = 0x00000000 */
- write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_SW_LTR), 0);
/* Program BAR0 + 3Ch[30] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
+ reg = read32((u32 *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_CMD12));
reg |= SIO_REG_SDIO_PPR_CMD12_B30;
- write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_CMD12), reg);
}
/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
+ u32 reg32 = read32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
- write32(bar0->base + SIO_REG_PPR_GEN, reg32);
+ write32((u32 *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN), reg32);
}
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 845129f..a1a0c29 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -64,13 +64,13 @@ void usb_ehci_disable(device_t dev)
void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
{
u32 reg32;
- u32 bar0_base;
+ u32 *bar0_base;
u16 pwr_state;
u16 pci_cmd;
/* Check if the controller is disabled or not present */
- bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- if (bar0_base == 0 || bar0_base == 0xffffffff)
+ bar0_base = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ if (bar0_base == 0 || bar0_base == (u32 *)0xffffffff)
return;
pci_cmd = pci_read_config32(dev, PCI_COMMAND);
@@ -86,7 +86,7 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state);
/* Make sure memory bar is set */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base);
/* Make sure memory space is enabled */
pci_write_config16(dev, PCI_COMMAND, pci_cmd |
@@ -99,29 +99,29 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
* - Clear Periodic Schedule Enable (bit4) and
* - Set Run/Stop (bit0)
*/
- reg32 = read32(bar0_base + EHCI_USB_CMD);
+ reg32 = read32(bar0_base + (EHCI_USB_CMD/sizeof(u32)));
if (reg32 & EHCI_USB_CMD_RUN) {
reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE);
reg32 |= EHCI_USB_CMD_RUN;
- write32(bar0_base + EHCI_USB_CMD, reg32);
+ write32(bar0_base + (EHCI_USB_CMD/sizeof(u32)), reg32);
}
/* Check for Port Enabled in PORTSC(0) (RMH) */
- reg32 = read32(bar0_base + EHCI_PORTSC(0));
+ reg32 = read32(bar0_base + (EHCI_PORTSC(0)/sizeof(u32)));
if (reg32 & EHCI_PORTSC_ENABLED) {
/* Set suspend bit in PORTSC if not already set */
if (!(reg32 & EHCI_PORTSC_SUSPEND)) {
reg32 |= EHCI_PORTSC_SUSPEND;
- write32(bar0_base + EHCI_PORTSC(0), reg32);
+ write32(bar0_base + (EHCI_PORTSC(0)/sizeof(u32)), reg32);
}
/* Delay 25ms !! */
udelay(25 * 1000);
/* Clear Run/Stop bit */
- reg32 = read32(bar0_base + EHCI_USB_CMD);
+ reg32 = read32(bar0_base + (EHCI_USB_CMD/sizeof(u32)));
reg32 &= EHCI_USB_CMD_RUN;
- write32(bar0_base + EHCI_USB_CMD, reg32);
+ write32(bar0_base + (EHCI_USB_CMD/sizeof(u32)), reg32);
}
/* Restore state to D3 if that is what it was at the start */
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 6c7bf04..5619a25 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -28,7 +28,7 @@
typedef struct southbridge_intel_lynxpoint_config config_t;
-static u32 usb_xhci_mem_base(device_t dev)
+static u32 *usb_xhci_mem_base(device_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -36,7 +36,7 @@ static u32 usb_xhci_mem_base(device_t dev)
if (mem_base == 0 || mem_base == 0xffffffff)
return 0;
- return mem_base & ~0xf;
+ return (u32 *)(mem_base & ~0xf);
}
static int usb_xhci_port_count_usb3(device_t dev)
@@ -46,8 +46,8 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 4;
} else {
/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
- u32 mem_base = usb_xhci_mem_base(dev);
- u32 fus = read32(mem_base + XHCI_USB3FUS);
+ u32 *mem_base = usb_xhci_mem_base(dev);
+ u32 fus = read32(mem_base + (XHCI_USB3FUS/sizeof(u32)));
fus >>= XHCI_USB3FUS_SS_SHIFT;
fus &= XHCI_USB3FUS_SS_MASK;
switch (fus) {
@@ -60,9 +60,9 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 0;
}
-static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_status_usb3(u32 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u32 *portsc = mem_base + (XHCI_USB3_PORTSC(port)/sizeof(u32));
u32 status = read32(portsc);
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
@@ -71,9 +71,9 @@ static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
write32(portsc, status);
}
-static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_port_usb3(u32 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u32 *portsc = mem_base + (XHCI_USB3_PORTSC(port)/sizeof(u32));
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
@@ -92,7 +92,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
- u32 mem_base = usb_xhci_mem_base(dev);
+ u32 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
@@ -108,7 +108,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
if (port_disabled & (1 << port))
continue;
/* Read port link status field */
- status = read32(mem_base + XHCI_USB3_PORTSC(port));
+ status = read32(mem_base + (XHCI_USB3_PORTSC(port)/sizeof(u32)));
status &= XHCI_USB3_PORTSC_PLS;
if (status == XHCI_PLSR_POLLING)
complete = 0;
@@ -121,7 +121,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u32 *portsc = mem_base + (XHCI_USB3_PORTSC(port)/sizeof(u32));
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
@@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
if (port_disabled & (1 << port))
continue;
/* Check if warm reset is complete */
- status = read32(mem_base + XHCI_USB3_PORTSC(port));
+ status = read32(mem_base + (XHCI_USB3_PORTSC(port)/sizeof(u32)));
if (!(status & XHCI_USB3_PORTSC_WRC))
complete = 0;
}
@@ -164,7 +164,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u32 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < 3)
return;
@@ -182,17 +182,17 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
pci_write_config32(dev, 0xb0, reg32);
/* Clear MMIO 0x816c[14,2] */
- reg32 = read32(mem_base + 0x816c);
+ reg32 = read32(mem_base + (0x816c/sizeof(u32)));
reg32 &= ~((1 << 14) | (1 << 2));
- write32(mem_base + 0x816c, reg32);
+ write32(mem_base + (0x816c/sizeof(u32)), reg32);
/* Reset disconnected USB3 ports */
usb_xhci_reset_usb3(dev, 0);
/* Set MMIO 0x80e0[15] */
- reg32 = read32(mem_base + 0x80e0);
+ reg32 = read32(mem_base + (0x80e0/sizeof(u32)));
reg32 |= (1 << 15);
- write32(mem_base + 0x80e0, reg32);
+ write32(mem_base + (0x80e0/sizeof(u32)), reg32);
}
/* Set D3Hot state and enable PME */
@@ -295,7 +295,7 @@ static void usb_xhci_init(device_t dev)
{
u32 reg32;
u16 reg16;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u32 *mem_base = usb_xhci_mem_base(dev);
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */
@@ -307,7 +307,7 @@ static void usb_xhci_init(device_t dev)
/* Enable clock gating first */
usb_xhci_clock_gating(dev);
- reg32 = read32(mem_base + 0x8144);
+ reg32 = read32(mem_base + (0x8144/sizeof(u32)));
if (pch_is_lp()) {
/* XHCIBAR + 8144h[8,7,6] = 111b */
reg32 |= (1 << 8) | (1 << 7) | (1 << 6);
@@ -316,14 +316,14 @@ static void usb_xhci_init(device_t dev)
reg32 &= ~((1 << 7) | (1 << 6));
reg32 |= (1 << 8);
}
- write32(mem_base + 0x8144, reg32);
+ write32(mem_base + (0x8144/sizeof(u32)), reg32);
if (pch_is_lp()) {
/* XHCIBAR + 816Ch[19:0] = 000e0038h */
- reg32 = read32(mem_base + 0x816c);
+ reg32 = read32(mem_base + (0x816c/sizeof(u32)));
reg32 &= ~0x000fffff;
reg32 |= 0x000e0038;
- write32(mem_base + 0x816c, reg32);
+ write32(mem_base + (0x816c/sizeof(u32)), reg32);
/* D20:F0:B0h[17,14,13] = 100b */
reg32 = pci_read_config32(dev, 0xb0);
diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c
index 9c77937..9adeaf8 100644
--- a/src/southbridge/intel/sch/audio.c
+++ b/src/southbridge/intel/sch/audio.c
@@ -32,7 +32,7 @@
typedef struct southbridge_intel_sch_config config_t;
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -61,19 +61,19 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u32 reg32;
int count;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* clear STATESTS bits (BAR + 0xE)[2:0] */
- reg32 = read32(base + 0x0E);
+ reg32 = read32(base + (0x0E / sizeof(u32)));
reg32 |= 7;
- write32(base + 0x0E, reg32);
+ write32(base + (0x0E / sizeof(u32)), reg32);
/* Wait for readback of register to
* match what was just written to it
@@ -82,22 +82,22 @@ static int codec_detect(u32 base)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(base + 0x0E);
+ reg32 = read32(base + (0x0E / sizeof(u32)));
} while ((reg32 != 0) && --count);
/* Timeout occured */
if (!count)
goto no_codec;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 0) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 0) == -1)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
- reg32 = read32(base + 0xe);
+ reg32 = read32(base + (0xe / sizeof(u32)));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -107,7 +107,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "sch_audio: No codec!\n");
return 0;
}
@@ -142,7 +142,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
* no response would imply that the codec is non-operative
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -150,7 +150,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -165,23 +165,23 @@ static int wait_for_ready(u32 base)
* is non-operative
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 25;
- write32(base + 0x68, 1);
+ write32(base + (0x68 / sizeof(u32)), 1);
while (timeout--) {
udelay(1);
}
timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + 0x68);
+ u32 reg32 = read32(base + (0x68 / sizeof(u32)));
if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) {
- write32(base + 0x68, 2);
+ write32(base + (0x68 / sizeof(u32)), 2);
return 0;
}
udelay(1);
@@ -190,7 +190,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32;
const u32 *verb;
@@ -204,20 +204,20 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x0);
+ reg32 = read32(base + (0x0 / sizeof(u32)));
printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32);
- reg32 = read32(base + 0x4);
+ reg32 = read32(base + (0x4 / sizeof(u32)));
printk(BIOS_DEBUG, "sch_audio: OUTPAY: %08x\n", reg32);
- reg32 = read32(base + 0x6);
+ reg32 = read32(base + (0x6 / sizeof(u32)));
printk(BIOS_DEBUG, "sch_audio: INPAY: %08x\n", reg32);
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "sch_audio: codec viddid: %08x\n", reg32);
@@ -234,7 +234,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -242,7 +242,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "sch_audio: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
@@ -254,7 +254,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void sch_audio_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
u32 reg32;
@@ -268,8 +268,8 @@ static void sch_audio_init(struct device *dev)
// NOTE this will break as soon as the sch_audio get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32) res->base;
- printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base);
+ base = (u32 *)(uintptr_t) res->base;
+ printk(BIOS_DEBUG, "sch_audio: base = %px\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 9b6049c..9c294a0 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -60,7 +60,7 @@ static void lpc_common_init(device_t dev)
/* I/O APIC initialization. */
res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */
ASSERT(res != NULL);
- setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
+ setup_ioapic((void *)(uintptr_t)res->base, 0); /* Don't rename IOAPIC ID. */
#if 1
dword = pci_read_config32(dev, 0xe4);
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index e285644..a7805c9 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -33,16 +33,16 @@ static void nic_init(struct device *dev)
int eeprom_valid = 0;
struct southbridge_nvidia_ck804_config *conf;
static u32 nic_index = 0;
- unsigned long base;
+ u32 *base;
struct resource *res;
res = find_resource(dev, 0x10);
- base = (unsigned long)res->base;
+ base = (u32 *)(uintptr_t)res->base;
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
- write32(base + NvRegPhyInterface, PHY_RGMII);
+ write32(base + (NvRegPhyInterface/sizeof(u32)), PHY_RGMII);
old = dword = pci_read_config32(dev, 0x30);
dword &= ~(0xf);
@@ -89,17 +89,17 @@ static void nic_init(struct device *dev)
/* If that is invalid we will read that from romstrap. */
if (!eeprom_valid) {
- unsigned long mac_pos;
- mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
+ u32 *mac_pos;
+ mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */
mac_l = read32(mac_pos) + nic_index;
- mac_h = read32(mac_pos + 4);
+ mac_h = read32(mac_pos + 1);
}
#if 1
/* Set that into NIC MMIO. */
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
- write32(base + NvRegMacAddrA, mac_l);
- write32(base + NvRegMacAddrB, mac_h);
+ write32(base + (NvRegMacAddrA/sizeof(u32)), mac_l);
+ write32(base + (NvRegMacAddrB/sizeof(u32)), mac_h);
#else
/* Set that into NIC. */
pci_write_config32(dev, 0xa8, mac_l);
diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c
index 67433d3..d151176 100644
--- a/src/southbridge/nvidia/mcp55/azalia.c
+++ b/src/southbridge/nvidia/mcp55/azalia.c
@@ -31,7 +31,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -58,20 +58,20 @@ static int set_bits(u32 port, u32 mask, u32 val)
return 0;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u32 reg32;
/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0]. */
- if (set_bits(base + 0x08, 1, 0) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 0) == -1)
goto no_codec;
/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0]. */
- if (set_bits(base + 0x08, 1, 1) == -1)
+ if (set_bits(base + (0x08 / sizeof(u32)), 1, 1) == -1)
goto no_codec;
/* Read in codec location (BAR + 0xe)[2..0]. */
- reg32 = read32(base + 0xe);
+ reg32 = read32(base + (0xe / sizeof(u32)));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -81,7 +81,7 @@ static int codec_detect(u32 base)
no_codec:
/* Codec not found. */
/* Put HDA back in reset (BAR + 0x8)[0]. */
- set_bits(base + 0x08, 1, 0);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
@@ -111,13 +111,13 @@ static u32 find_verb(struct device *dev, u32 viddid, u32 **verb)
* Wait 50usec for the codec to indicate it is ready.
* No response would imply that the codec is non-operative.
*/
-static int wait_for_ready(u32 base)
+static int wait_for_ready(u32 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
int timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -130,19 +130,19 @@ static int wait_for_ready(u32 base)
* Wait 50usec for the codec to indicate that it accepted the previous command.
* No response would imply that the code is non-operative.
*/
-static int wait_for_valid(u32 base)
+static int wait_for_valid(u32 *base)
{
u32 reg32;
/* Send the verb to the codec. */
- reg32 = read32(base + 0x68);
+ reg32 = read32(base + (0x68 / sizeof(u32)));
reg32 |= (1 << 0) | (1 << 1);
- write32(base + 0x68, reg32);
+ write32(base + (0x68 / sizeof(u32)), reg32);
/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
int timeout = 50;
while (timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32(base + (HDA_ICII_REG / sizeof(u32)));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -152,7 +152,7 @@ static int wait_for_valid(u32 base)
return -1;
}
-static void codec_init(struct device *dev, u32 base, int addr)
+static void codec_init(struct device *dev, u32 *base, int addr)
{
u32 reg32, verb_size;
u32 *verb;
@@ -165,12 +165,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(base + (0x60 / sizeof(u32)), reg32);
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32(base + (0x64 / sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -187,7 +187,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(base + (0x60 / sizeof(u32)), verb[i]);
if (wait_for_valid(base) == -1)
return;
@@ -195,7 +195,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(struct device *dev, u32 *base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -206,7 +206,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
static void azalia_init(struct device *dev)
{
- u32 base, codec_mask, reg32;
+ u32 *base, codec_mask, reg32;
struct resource *res;
u8 reg8;
@@ -244,7 +244,7 @@ static void azalia_init(struct device *dev)
* NOTE: This will break as soon as the Azalia gets a BAR above
* 4G. Is there anything we can do about it?
*/
- base = (u32)res->base;
+ base = (u32 *)(uintptr_t)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 11c2c4f..5f190b8 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -60,13 +60,13 @@
static void lpc_common_init(device_t dev, int master)
{
u8 byte;
- u32 ioapic_base;
+ void *ioapic_base;
/* IOAPIC initialization. */
byte = pci_read_config8(dev, 0x74);
byte |= (1 << 0); /* Enable IOAPIC. */
pci_write_config8(dev, 0x74, byte);
- ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
+ ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
if (master)
setup_ioapic(ioapic_base, 0);
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index fd736e6..e9c55bd 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -31,43 +31,43 @@
#include <delay.h>
#include "mcp55.h"
-static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u32 *base, unsigned phy_addr, unsigned phy_reg)
{
u32 dword;
unsigned loop = 0x100;
- write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */
+ write32(base + (0x190/sizeof(u32)), 0x8000); /* Clear MDIO lock bit. */
mdelay(1);
- dword = read32(base + 0x190);
+ dword = read32(base + (0x190/sizeof(u32)));
if (dword & (1 << 15))
return -1;
- write32(base + 0x180, 1);
- write32(base + 0x190, (phy_addr << 5) | (phy_reg));
+ write32(base + (0x180/sizeof(u32)), 1);
+ write32(base + (0x190/sizeof(u32)), (phy_addr << 5) | (phy_reg));
do {
- dword = read32(base + 0x190);
+ dword = read32(base + (0x190/sizeof(u32)));
if (--loop==0)
return -4;
} while ((dword & (1 << 15)));
- dword = read32(base + 0x180);
+ dword = read32(base + (0x180/sizeof(u32)));
if (dword & 1)
return -3;
- dword = read32(base + 0x194);
+ dword = read32(base + (0x194/sizeof(u32)));
return dword;
}
-static void phy_detect(u32 base)
+static void phy_detect(u32 *base)
{
u32 dword;
int i, val;
unsigned id;
- dword = read32(base + 0x188);
+ dword = read32(base + (0x188/sizeof(u32)));
dword &= ~(1 << 20);
- write32(base + 0x188, dword);
+ write32(base + (0x188/sizeof(u32)), dword);
phy_read(base, 0, 1);
@@ -103,7 +103,7 @@ static void phy_detect(u32 base)
static void nic_init(struct device *dev)
{
- u32 mac_h = 0, mac_l = 0, base;
+ u32 mac_h = 0, mac_l = 0, *base;
int eeprom_valid = 0;
struct southbridge_nvidia_mcp55_config *conf;
static u32 nic_index = 0;
@@ -114,14 +114,14 @@ static void nic_init(struct device *dev)
if (!res)
return;
- base = res->base;
+ base = (u32 *)(uintptr_t)res->base;
phy_detect(base);
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
- write32(base + NvRegPhyInterface, PHY_RGMII);
+ write32(base + (NvRegPhyInterface/sizeof(u32)), PHY_RGMII);
conf = dev->chip_info;
@@ -160,18 +160,18 @@ static void nic_init(struct device *dev)
}
// if that is invalid we will read that from romstrap
if(!eeprom_valid) {
- unsigned long mac_pos;
- mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
+ u32 *mac_pos;
+ mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.lds
mac_l = read32(mac_pos) + nic_index; // overflow?
- mac_h = read32(mac_pos + 4);
+ mac_h = read32(mac_pos + 1);
}
#if 1
// set that into NIC MMIO
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
- write32(base + NvRegMacAddrA, mac_l);
- write32(base + NvRegMacAddrB, mac_h);
+ write32(base + (NvRegMacAddrA/sizeof(u32)), mac_l);
+ write32(base + (NvRegMacAddrB/sizeof(u32)), mac_h);
#else
// set that into NIC
pci_write_config32(dev, 0xa8, mac_l);
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index 7e148cf..50aa7a9 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -42,7 +42,7 @@ u8 SiS_SiS7502_init[7][3]={
{0x00, 0x00, 0x00} //End of table
};
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -67,32 +67,32 @@ static int set_bits(u32 port, u32 mask, u32 val)
}
-static u32 send_verb(u32 base, u32 verb)
+static u32 send_verb(u32 *base, u32 verb)
{
u32 dword;
- dword = read32(base + 0x68);
+ dword = read32(base + (0x68/sizeof(u32)));
dword=dword|(unsigned long)0x0002;
- write32(base + 0x68, dword);
+ write32(base + (0x68/sizeof(u32)), dword);
do {
- dword = read32(base + 0x68);
+ dword = read32(base + (0x68/sizeof(u32)));
} while ((dword & 1)!=0);
- write32(base + 0x60, verb);
+ write32(base + (0x60/sizeof(u32)), verb);
udelay(500);
- dword = read32(base + 0x68);
+ dword = read32(base + (0x68/sizeof(u32)));
dword =(dword |0x1);
- write32(base + 0x68, dword);
+ write32(base + (0x68/sizeof(u32)), dword);
do {
udelay(100);
- dword = read32(base + 0x68);
+ dword = read32(base + (0x68/sizeof(u32)));
} while ((dword & 3) != 2);
- dword = read32(base + 0x64);
+ dword = read32(base + (0x64/sizeof(u32)));
return dword;
}
-static int codec_detect(u32 base)
+static int codec_detect(u32 *base)
{
u32 dword;
int idx=0;
@@ -100,10 +100,10 @@ static int codec_detect(u32 base)
/* 1 */ // controller reset
printk(BIOS_DEBUG, "controller reset\n");
- set_bits(base + 0x08, 1, 1);
+ set_bits(base + (0x08 / sizeof(u32)), 1, 1);
do{
- dword = read32(base + 0x08)&0x1;
+ dword = read32(base + (0x08 / sizeof(u32)))&0x1;
if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!! \n"); break;}
} while (dword !=1);
@@ -194,7 +194,7 @@ static unsigned find_verb(u32 viddid, u32 **verb)
}
-static void codec_init(u32 base, int addr)
+static void codec_init(u32 *base, int addr)
{
u32 dword;
u32 *verb;
@@ -203,17 +203,17 @@ static void codec_init(u32 base, int addr)
/* 1 */
do {
- dword = read32(base + 0x68);
+ dword = read32(base + (0x68/sizeof(u32)));
} while (dword & 1);
dword = (addr<<28) | 0x000f0000;
- write32(base + 0x60, dword);
+ write32(base + (0x60/sizeof(u32)), dword);
do {
- dword = read32(base + 0x68);
+ dword = read32(base + (0x68/sizeof(u32)));
} while ((dword & 3)!=2);
- dword = read32(base + 0x64);
+ dword = read32(base + (0x64/sizeof(u32)));
/* 2 */
printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
@@ -232,7 +232,7 @@ static void codec_init(u32 base, int addr)
printk(BIOS_DEBUG, "verb loaded!\n");
}
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(u32 *base, u32 codec_mask)
{
codec_init(base, 0);
return;
@@ -240,7 +240,7 @@ static void codecs_init(u32 base, u32 codec_mask)
static void aza_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
u32 codec_mask;
@@ -289,8 +289,8 @@ static void aza_init(struct device *dev)
if(!res)
return;
- base = res->base;
- printk(BIOS_DEBUG, "base = 0x%08x\n", base);
+ base = (void *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index a61883b..c9f1ff6 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -59,13 +59,13 @@
static void lpc_common_init(device_t dev)
{
uint8_t byte;
- uint32_t ioapic_base;
+ void *ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
- ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ ioapic_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
}
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index 18ed75e..2f5ff36 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -133,7 +133,7 @@ static void set_apc(struct device *dev)
* @return Contents of EEPROM word (Reg).
*/
#define LoopNum 200
-static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
+static unsigned long ReadEEprom( struct device *dev, u32 *base, u32 Reg)
{
u32 data;
u32 i;
@@ -142,13 +142,13 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
- write32(base+0x3c, ulValue);
+ write32(base+(0x3c/sizeof(u32)), ulValue);
mdelay(10);
for(i=0 ; i <= LoopNum; i++)
{
- ulValue=read32(base+0x3c);
+ ulValue=read32(base+(0x3c/sizeof(u32)));
if(!(ulValue & 0x0080)) //BIT_7
break;
@@ -160,14 +160,14 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
if(i==LoopNum) data=0x10000;
else{
- ulValue=read32(base+0x3c);
+ ulValue=read32(base+(0x3c/sizeof(u32)));
data = ((ulValue & 0xffff0000) >> 16);
}
return data;
}
-static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u32 *base, unsigned phy_addr, unsigned phy_reg)
{
u32 ulValue;
u32 Read_Cmd;
@@ -181,14 +181,14 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
SMI_REQUEST);
// SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
- write32(base+0x44, Read_Cmd);
+ write32(base+(0x44/sizeof(u32)), Read_Cmd);
// Polling SMI_REQ bit to be deasserted indicated read command completed
do
{
// Wait 20 usec before checking status
mdelay(20);
- ulValue = read32(base+0x44);
+ ulValue = read32(base+(0x44/sizeof(u32)));
} while((ulValue & SMI_REQUEST) != 0);
//printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
usData=(ulValue>>16);
@@ -201,7 +201,7 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
// Detect a valid PHY
// If there exist a valid PHY then return TRUE, else return FALSE
-static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect()
+static int phy_detect(u32 *base,u16 *PhyAddr) //BOOL PHY_Detect()
{
int bFoundPhy = FALSE;
u16 usData;
@@ -238,7 +238,7 @@ static void nic_init(struct device *dev)
{
int val;
u16 PhyAddr;
- u32 base;
+ u32 *base;
struct resource *res;
print_debug("NIC_INIT:---------->\n");
@@ -269,8 +269,8 @@ static void nic_init(struct device *dev)
printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
}
- base = res->base;
- printk(BIOS_DEBUG, "NIC base address %x\n",base);
+ base = (u32 *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "NIC base address %p\n",base);
if(!(val=phy_detect(base,&PhyAddr)))
{
@@ -278,7 +278,7 @@ static void nic_init(struct device *dev)
return;
}
- ulValue=read32(base + 0x38L); // check EEPROM existing
+ ulValue=read32(base + (0x38L/sizeof(u32))); // check EEPROM existing
if((ulValue & 0x0002))
{
@@ -299,9 +299,9 @@ static void nic_init(struct device *dev)
}else{
// read MAC address from firmware
printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
- MacAddr[0]=read16(0xffffffc0); // mac address store at here
- MacAddr[1]=read16(0xffffffc2);
- MacAddr[2]=read16(0xffffffc4);
+ MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
+ MacAddr[1]=read16((u16 *)0xffffffc2);
+ MacAddr[2]=read16((u16 *)0xffffffc4);
}
set_apc(dev);
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index e2112eb..ad76bc2 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -66,7 +66,7 @@ static const u8 SiS_SiS7002_init[22][3]={
static void usb2_init(struct device *dev)
{
- u32 base;
+ u32 *base;
struct resource *res;
int i;
u8 temp8;
@@ -89,9 +89,9 @@ static void usb2_init(struct device *dev)
if(!res)
return;
- base = res->base;
- printk(BIOS_DEBUG, "base = 0x%08x\n", base);
- write32(base+0x20, 0x2);
+ base = (void *)(uintptr_t)res->base;
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
+ write32(base+(0x20/sizeof(u32)), 0x2);
//-------------------------------------------------------------
#if DEBUG_USB2
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 92eaa39..f42cf3f 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -634,7 +634,7 @@ static void southbridge_init_common(struct device *dev)
{
vt8237_common_init(dev);
pci_routing_fixup(dev);
- setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID);
+ setup_ioapic((void *)IO_APIC_ADDR, VT8237R_APIC_ID);
setup_i8259();
init_keyboard(dev);
}
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