[coreboot-gerrit] New patch to review for coreboot: 54fc56a soc/samsung/exynos5250/clock.c: Trivial whitespace fixes

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7926

-gerrit

commit 54fc56af136cd9047c8a74c6ddde4465a48336fb
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Fri Dec 26 12:36:47 2014 +1100

    soc/samsung/exynos5250/clock.c: Trivial whitespace fixes
    
    Reduce difference with exynos5420/clock.c by fixing some whitespace
    and an include directive.
    
    Change-Id: Ifbdd61c8300f3988f5f729fe7d6124ac8a9b7821
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/soc/samsung/exynos5250/clock.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c
index 8a731be..1de2ab2 100644
--- a/src/soc/samsung/exynos5250/clock.c
+++ b/src/soc/samsung/exynos5250/clock.c
@@ -19,11 +19,11 @@
 
 #include <assert.h>
 #include <stdlib.h>
+#include <timer.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include "clk.h"
 #include "periph.h"
-#include "timer.h"
 
 /* input clock of PLL: SMDK5250 has 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ            24000000
@@ -635,12 +635,10 @@ int clock_epll_set_rate(unsigned long rate)
 	end = current;
 	mono_time_add_msecs(&end, TIMEOUT_EPLL_LOCK);
 
-	 while (!(readl(&exynos_clock->epll_con0) &
+	while (!(readl(&exynos_clock->epll_con0) &
 			(0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
 		if (mono_time_after(&current, &end)) {
-			printk(BIOS_DEBUG,
-				"%s: Timeout waiting for EPLL lock\n",
-				__func__);
+			printk(BIOS_DEBUG, "%s: Timeout waiting for EPLL lock\n", __func__);
 			return -1;
 		}
 		timer_monotonic_get(&current);