[coreboot-gerrit] Patch merged into coreboot/master: 16f64af AMD cimx/sb800: Set SPI frequency and prefetch

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 16f64af25cc2b79975698598ab57a40ff8110d15
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jan 31 20:32:54 2014 +0200

    AMD cimx/sb800: Set SPI frequency and prefetch
    
    Broken with/since commit d1cb0eec.
    
    Original intention was to set the frequency for 'Fast Read' command
    in bits 15..14, and enable 'Fast Read' command.
    
    Modified register contains SPI frequency for 'Normal Read' command
    in bits 13..12. Default for this is 11b for 16.5 MHz. Existing code
    unintentionally clears these bits, increasing SPI frequency to 66MHz
    for 'Normal Read' command.
    
    This is above specifications for many common SPI flash components
    and also makes flashrom older than 0.9.7-r1750 to operate unreliably
    on read/write/erase for these platforms.
    
    Change-Id: I30109e2a0410c0bb0bdc968ea71787396b32e761
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>


See http://review.coreboot.org/5089 for details.

-gerrit